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-rw-r--r--arch/mips/include/asm/asm-offsets.h1
-rw-r--r--arch/mips/include/asm/bootinfo.h8
-rw-r--r--arch/mips/include/asm/clock.h64
-rw-r--r--arch/mips/include/asm/cop2.h23
-rw-r--r--arch/mips/include/asm/cpu.h2
-rw-r--r--arch/mips/include/asm/fcntl.h2
-rw-r--r--arch/mips/include/asm/fpu.h8
-rw-r--r--arch/mips/include/asm/fpu_emulator.h24
-rw-r--r--arch/mips/include/asm/ftrace.h91
-rw-r--r--arch/mips/include/asm/irq.h29
-rw-r--r--arch/mips/include/asm/mach-excite/cpu-feature-overrides.h48
-rw-r--r--arch/mips/include/asm/mach-excite/excite.h154
-rw-r--r--arch/mips/include/asm/mach-excite/excite_fpga.h80
-rw-r--r--arch/mips/include/asm/mach-excite/excite_nandflash.h7
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_eth.h23
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_wdt.h12
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_xicap.h16
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536.h305
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h35
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h153
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h31
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h290
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h9
-rw-r--r--arch/mips/include/asm/mach-loongson/mem.h27
-rw-r--r--arch/mips/include/asm/mach-loongson/pci.h34
-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h107
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h155
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h119
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h254
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/irq.h25
-rw-r--r--arch/mips/include/asm/mach-powertv/powertv-clock.h29
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h (renamed from arch/mips/include/asm/mach-excite/war.h)19
-rw-r--r--arch/mips/include/asm/mips-boards/bonito64.h5
-rw-r--r--arch/mips/include/asm/mmu_context.h29
-rw-r--r--arch/mips/include/asm/octeon/cvmx-agl-defs.h1194
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mixx-defs.h248
-rw-r--r--arch/mips/include/asm/octeon/cvmx-smix-defs.h178
-rw-r--r--arch/mips/include/asm/octeon/octeon.h1
-rw-r--r--arch/mips/include/asm/pgtable.h13
-rw-r--r--arch/mips/include/asm/sgialib.h3
-rw-r--r--arch/mips/include/asm/stackframe.h40
43 files changed, 3537 insertions, 452 deletions
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/mips/include/asm/asm-offsets.h
@@ -0,0 +1 @@
#include <generated/asm-offsets.h>
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index f5dfaf6a1606..09eee09780f2 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -67,9 +67,9 @@
67#define MACH_LEMOTE_ML2F7 3 67#define MACH_LEMOTE_ML2F7 3
68#define MACH_LEMOTE_YL2F89 4 68#define MACH_LEMOTE_YL2F89 4
69#define MACH_DEXXON_GDIUM2F10 5 69#define MACH_DEXXON_GDIUM2F10 5
70#define MACH_LOONGSON_END 6 70#define MACH_LEMOTE_NAS 6
71 71#define MACH_LEMOTE_LL2F 7
72#define CL_SIZE COMMAND_LINE_SIZE 72#define MACH_LOONGSON_END 8
73 73
74extern char *system_type; 74extern char *system_type;
75const char *get_system_type(void); 75const char *get_system_type(void);
@@ -107,7 +107,7 @@ extern void free_init_pages(const char *what,
107/* 107/*
108 * Initial kernel command line, usually setup by prom_init() 108 * Initial kernel command line, usually setup by prom_init()
109 */ 109 */
110extern char arcs_cmdline[CL_SIZE]; 110extern char arcs_cmdline[COMMAND_LINE_SIZE];
111 111
112/* 112/*
113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware 113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
new file mode 100644
index 000000000000..83894aa7932c
--- /dev/null
+++ b/arch/mips/include/asm/clock.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_MIPS_CLOCK_H
2#define __ASM_MIPS_CLOCK_H
3
4#include <linux/kref.h>
5#include <linux/list.h>
6#include <linux/seq_file.h>
7#include <linux/clk.h>
8
9extern void (*cpu_wait) (void);
10
11struct clk;
12
13struct clk_ops {
14 void (*init) (struct clk *clk);
15 void (*enable) (struct clk *clk);
16 void (*disable) (struct clk *clk);
17 void (*recalc) (struct clk *clk);
18 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
19 long (*round_rate) (struct clk *clk, unsigned long rate);
20};
21
22struct clk {
23 struct list_head node;
24 const char *name;
25 int id;
26 struct module *owner;
27
28 struct clk *parent;
29 struct clk_ops *ops;
30
31 struct kref kref;
32
33 unsigned long rate;
34 unsigned long flags;
35};
36
37#define CLK_ALWAYS_ENABLED (1 << 0)
38#define CLK_RATE_PROPAGATES (1 << 1)
39
40/* Should be defined by processor-specific code */
41void arch_init_clk_ops(struct clk_ops **, int type);
42
43int clk_init(void);
44
45int __clk_enable(struct clk *);
46void __clk_disable(struct clk *);
47
48void clk_recalc_rate(struct clk *);
49
50int clk_register(struct clk *);
51void clk_unregister(struct clk *);
52
53/* the exported API, in addition to clk_set_rate */
54/**
55 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
56 * @clk: clock source
57 * @rate: desired clock rate in Hz
58 * @algo_id: algorithm id to be passed down to ops->set_rate
59 *
60 * Returns success (0) or negative errno.
61 */
62int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
63
64#endif /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
new file mode 100644
index 000000000000..6b04c98b7fad
--- /dev/null
+++ b/arch/mips/include/asm/cop2.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Wind River Systems,
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_COP2_H
10#define __ASM_COP2_H
11
12enum cu2_ops {
13 CU2_EXCEPTION,
14 CU2_LWC2_OP,
15 CU2_LDC2_OP,
16 CU2_SWC2_OP,
17 CU2_SDC2_OP,
18};
19
20extern int register_cu2_notifier(struct notifier_block *nb);
21extern int cu2_notifier_call_chain(unsigned long val, void *v);
22
23#endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4b96d1a36056..cf373a95fe4a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -154,6 +154,8 @@
154#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 154#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
155#define PRID_REV_VR4130 0x0080 155#define PRID_REV_VR4130 0x0080
156#define PRID_REV_34K_V1_0_2 0x0022 156#define PRID_REV_34K_V1_0_2 0x0022
157#define PRID_REV_LOONGSON2E 0x0002
158#define PRID_REV_LOONGSON2F 0x0003
157 159
158/* 160/*
159 * Older processors used to encode processor version and revision in two 161 * Older processors used to encode processor version and revision in two
diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h
index 7c6681aa2ab8..e482fe90fe88 100644
--- a/arch/mips/include/asm/fcntl.h
+++ b/arch/mips/include/asm/fcntl.h
@@ -19,7 +19,7 @@
19#define FASYNC 0x1000 /* fcntl, for BSD compatibility */ 19#define FASYNC 0x1000 /* fcntl, for BSD compatibility */
20#define O_LARGEFILE 0x2000 /* allow large file opens */ 20#define O_LARGEFILE 0x2000 /* allow large file opens */
21/* 21/*
22 * Before Linux 2.6.32 only O_DSYNC semantics were implemented, but using 22 * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
23 * the O_SYNC flag. We continue to use the existing numerical value 23 * the O_SYNC flag. We continue to use the existing numerical value
24 * for O_DSYNC semantics now, but using the correct symbolic name for it. 24 * for O_DSYNC semantics now, but using the correct symbolic name for it.
25 * This new value is used to request true Posix O_SYNC semantics. It is 25 * This new value is used to request true Posix O_SYNC semantics. It is
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 8a3ef247659a..7fcef8ef3fab 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -28,15 +28,7 @@
28struct sigcontext; 28struct sigcontext;
29struct sigcontext32; 29struct sigcontext32;
30 30
31extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
32extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
33
34extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
35extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
36
37extern void fpu_emulator_init_fpu(void); 31extern void fpu_emulator_init_fpu(void);
38extern int fpu_emulator_save_context(struct sigcontext __user *sc);
39extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
40extern void _init_fpu(void); 32extern void _init_fpu(void);
41extern void _save_fp(struct task_struct *); 33extern void _save_fp(struct task_struct *);
42extern void _restore_fp(struct task_struct *); 34extern void _restore_fp(struct task_struct *);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index e5189572956c..aecada6f6117 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -25,17 +25,27 @@
25 25
26#include <asm/break.h> 26#include <asm/break.h>
27#include <asm/inst.h> 27#include <asm/inst.h>
28#include <asm/local.h>
29
30#ifdef CONFIG_DEBUG_FS
28 31
29struct mips_fpu_emulator_stats { 32struct mips_fpu_emulator_stats {
30 unsigned int emulated; 33 local_t emulated;
31 unsigned int loads; 34 local_t loads;
32 unsigned int stores; 35 local_t stores;
33 unsigned int cp1ops; 36 local_t cp1ops;
34 unsigned int cp1xops; 37 local_t cp1xops;
35 unsigned int errors; 38 local_t errors;
36}; 39};
37 40
38extern struct mips_fpu_emulator_stats fpuemustats; 41DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
42
43#define MIPS_FPU_EMU_INC_STATS(M) \
44 cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M))
45
46#else
47#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
48#endif /* CONFIG_DEBUG_FS */
39 49
40extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, 50extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
41 unsigned long cpc); 51 unsigned long cpc);
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 40a8c178f10d..3986cd8704f3 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -1 +1,90 @@
1/* empty */ 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive for
4 * more details.
5 *
6 * Copyright (C) 2009 DSLab, Lanzhou University, China
7 * Author: Wu Zhangjin <wuzj@lemote.com>
8 */
9
10#ifndef _ASM_MIPS_FTRACE_H
11#define _ASM_MIPS_FTRACE_H
12
13#ifdef CONFIG_FUNCTION_TRACER
14
15#define MCOUNT_ADDR ((unsigned long)(_mcount))
16#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
17
18#ifndef __ASSEMBLY__
19extern void _mcount(void);
20#define mcount _mcount
21
22#define safe_load(load, src, dst, error) \
23do { \
24 asm volatile ( \
25 "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
26 " li %[" STR(error) "], 0\n" \
27 "2:\n" \
28 \
29 ".section .fixup, \"ax\"\n" \
30 "3: li %[" STR(error) "], 1\n" \
31 " j 2b\n" \
32 ".previous\n" \
33 \
34 ".section\t__ex_table,\"a\"\n\t" \
35 STR(PTR) "\t1b, 3b\n\t" \
36 ".previous\n" \
37 \
38 : [dst] "=&r" (dst), [error] "=r" (error)\
39 : [src] "r" (src) \
40 : "memory" \
41 ); \
42} while (0)
43
44#define safe_store(store, src, dst, error) \
45do { \
46 asm volatile ( \
47 "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
48 " li %[" STR(error) "], 0\n" \
49 "2:\n" \
50 \
51 ".section .fixup, \"ax\"\n" \
52 "3: li %[" STR(error) "], 1\n" \
53 " j 2b\n" \
54 ".previous\n" \
55 \
56 ".section\t__ex_table,\"a\"\n\t"\
57 STR(PTR) "\t1b, 3b\n\t" \
58 ".previous\n" \
59 \
60 : [error] "=r" (error) \
61 : [dst] "r" (dst), [src] "r" (src)\
62 : "memory" \
63 ); \
64} while (0)
65
66#define safe_load_code(dst, src, error) \
67 safe_load(STR(lw), src, dst, error)
68#define safe_store_code(src, dst, error) \
69 safe_store(STR(sw), src, dst, error)
70
71#define safe_load_stack(dst, src, error) \
72 safe_load(STR(PTR_L), src, dst, error)
73
74#define safe_store_stack(src, dst, error) \
75 safe_store(STR(PTR_S), src, dst, error)
76
77
78#ifdef CONFIG_DYNAMIC_FTRACE
79static inline unsigned long ftrace_call_adjust(unsigned long addr)
80{
81 return addr;
82}
83
84struct dyn_arch_ftrace {
85};
86
87#endif /* CONFIG_DYNAMIC_FTRACE */
88#endif /* __ASSEMBLY__ */
89#endif /* CONFIG_FUNCTION_TRACER */
90#endif /* _ASM_MIPS_FTRACE_H */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 09b08d05ff72..06960364c96b 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -113,36 +113,11 @@ do { \
113 113
114#endif 114#endif
115 115
116/* 116extern void do_IRQ(unsigned int irq);
117 * do_IRQ handles all normal device IRQ's (the special
118 * SMP cross-CPU interrupts have their own specific
119 * handlers).
120 *
121 * Ideally there should be away to get this into kernel/irq/handle.c to
122 * avoid the overhead of a call for just a tiny function ...
123 */
124#define do_IRQ(irq) \
125do { \
126 irq_enter(); \
127 __DO_IRQ_SMTC_HOOK(irq); \
128 generic_handle_irq(irq); \
129 irq_exit(); \
130} while (0)
131 117
132#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 118#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
133/*
134 * To avoid inefficient and in some cases pathological re-checking of
135 * IRQ affinity, we have this variant that skips the affinity check.
136 */
137
138 119
139#define do_IRQ_no_affinity(irq) \ 120extern void do_IRQ_no_affinity(unsigned int irq);
140do { \
141 irq_enter(); \
142 __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
143 generic_handle_irq(irq); \
144 irq_exit(); \
145} while (0)
146 121
147#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 122#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
148 123
diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
deleted file mode 100644
index 107104c3cd12..000000000000
--- a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
7 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
11
12/*
13 * Basler eXcite has an RM9122 processor.
14 */
15#define cpu_has_watch 1
16#define cpu_has_mips16 0
17#define cpu_has_divec 0
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 0
23#define cpu_has_ejtag 0
24
25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0
30#define cpu_icache_snoops_remote_store 0
31#define cpu_has_mipsmt 0
32#define cpu_has_userlocal 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_mips32r1 0
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 0
40#define cpu_has_mips64r2 0
41
42#define cpu_has_inclusive_pcaches 0
43
44#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32
46#define cpu_scache_line_size() 32
47
48#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
deleted file mode 100644
index 4c29ba44992c..000000000000
--- a/arch/mips/include/asm/mach-excite/excite.h
+++ /dev/null
@@ -1,154 +0,0 @@
1#ifndef __EXCITE_H__
2#define __EXCITE_H__
3
4#include <linux/init.h>
5#include <asm/addrspace.h>
6#include <asm/types.h>
7
8#define EXCITE_CPU_EXT_CLOCK 100000000
9
10#if !defined(__ASSEMBLY__)
11void __init excite_kgdb_init(void);
12void excite_procfs_init(void);
13extern unsigned long memsize;
14extern char modetty[];
15extern u32 unit_id;
16#endif
17
18/* Base name for XICAP devices */
19#define XICAP_NAME "xicap_gpi"
20
21/* OCD register offsets */
22#define LKB0 0x0038
23#define LKB5 0x0128
24#define LKM5 0x012C
25#define LKB7 0x0138
26#define LKM7 0x013c
27#define LKB8 0x0140
28#define LKM8 0x0144
29#define LKB9 0x0148
30#define LKM9 0x014c
31#define LKB10 0x0150
32#define LKM10 0x0154
33#define LKB11 0x0158
34#define LKM11 0x015c
35#define LKB12 0x0160
36#define LKM12 0x0164
37#define LKB13 0x0168
38#define LKM13 0x016c
39#define LDP0 0x0200
40#define LDP1 0x0210
41#define LDP2 0x0220
42#define LDP3 0x0230
43#define INTPIN0 0x0A40
44#define INTPIN1 0x0A44
45#define INTPIN2 0x0A48
46#define INTPIN3 0x0A4C
47#define INTPIN4 0x0A50
48#define INTPIN5 0x0A54
49#define INTPIN6 0x0A58
50#define INTPIN7 0x0A5C
51
52
53
54
55/* TITAN register offsets */
56#define CPRR 0x0004
57#define CPDSR 0x0008
58#define CPTC0R 0x000c
59#define CPTC1R 0x0010
60#define CPCFG0 0x0020
61#define CPCFG1 0x0024
62#define CPDST0A 0x0028
63#define CPDST0B 0x002c
64#define CPDST1A 0x0030
65#define CPDST1B 0x0034
66#define CPXDSTA 0x0038
67#define CPXDSTB 0x003c
68#define CPXCISRA 0x0048
69#define CPXCISRB 0x004c
70#define CPGIG0ER 0x0050
71#define CPGIG1ER 0x0054
72#define CPGRWL 0x0068
73#define CPURSLMT 0x00f8
74#define UACFG 0x0200
75#define UAINTS 0x0204
76#define SDRXFCIE 0x4828
77#define SDTXFCIE 0x4928
78#define INTP0Status0 0x1B00
79#define INTP0Mask0 0x1B04
80#define INTP0Set0 0x1B08
81#define INTP0Clear0 0x1B0C
82#define GXCFG 0x5000
83#define GXDMADRPFX 0x5018
84#define GXDMA_DESCADR 0x501c
85#define GXCH0TDESSTRT 0x5054
86
87/* IRQ definitions */
88#define NMICONFIG 0xac0
89#define TITAN_MSGINT 0xc4
90#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
91#define FPGA0_MSGINT 0x5a
92#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
93#define FPGA1_MSGINT 0x7b
94#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
95#define PHY_MSGINT 0x9c
96#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
97
98#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
99/* Pre-release units used interrupt pin #9 */
100#define USB_IRQ 11
101#else
102/* Re-designed units use interrupt pin #1 */
103#define USB_MSGINT 0x39
104#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
105#endif
106#define TIMER_IRQ 12
107
108
109/* Device address ranges */
110#define EXCITE_OFFS_OCD 0x1fffc000
111#define EXCITE_SIZE_OCD (16 * 1024)
112#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
113#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
114
115#define EXCITE_OFFS_SCRAM 0x1fffa000
116#define EXCITE_SIZE_SCRAM (8 << 10)
117#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
118#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
119
120#define EXCITE_OFFS_PCI_IO 0x1fff8000
121#define EXCITE_SIZE_PCI_IO (8 << 10)
122#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
123#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
124
125#define EXCITE_OFFS_TITAN 0x1fff0000
126#define EXCITE_SIZE_TITAN (32 << 10)
127#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
128#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
129
130#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
131#define EXCITE_SIZE_PCI_MEM (64 << 10)
132#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
133#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
134
135#define EXCITE_OFFS_FPGA 0x1ffdc000
136#define EXCITE_SIZE_FPGA (16 << 10)
137#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
138#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
139
140#define EXCITE_OFFS_NAND 0x1ffd8000
141#define EXCITE_SIZE_NAND (16 << 10)
142#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
143#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
144
145#define EXCITE_OFFS_BOOTROM 0x1f000000
146#define EXCITE_SIZE_BOOTROM (8 << 20)
147#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
148#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
149
150/* FPGA address offsets */
151#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
152#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
153
154#endif /* __EXCITE_H__ */
diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
deleted file mode 100644
index 0a1ef69bece7..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
1#ifndef EXCITE_FPGA_H_INCLUDED
2#define EXCITE_FPGA_H_INCLUDED
3
4
5/**
6 * Address alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform.
9 */
10#ifdef EXCITE_CCI_FPGA_MK2
11typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12#else
13typedef unsigned char excite_cci_fpga_align_t;
14#endif
15
16
17/**
18 * Size of Dual Ported RAM.
19 */
20#define EXCITE_DPR_SIZE 263
21
22
23/**
24 * Size of Reserved Status Fields in Dual Ported RAM.
25 */
26#define EXCITE_DPR_STATUS_SIZE 7
27
28
29
30/**
31 * FPGA.
32 * Hardware register layout of the FPGA interface. The FPGA must accessed
33 * byte wise solely.
34 * @see EXCITE_CCI_DPR_MK2
35 */
36typedef struct excite_fpga {
37
38 /**
39 * Dual Ported RAM.
40 */
41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42
43 /**
44 * Status.
45 */
46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47
48#ifdef EXCITE_CCI_FPGA_MK2
49 /**
50 * RM9000 Interrupt.
51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52 */
53 excite_cci_fpga_align_t rm9k_int;
54#else
55 /**
56 * MK2 Interrupt.
57 * Write access initiates interrupt at the ARM processor of the MK2.
58 */
59 excite_cci_fpga_align_t mk2_int;
60
61 excite_cci_fpga_align_t gap[0x1000-0x10f];
62
63 /**
64 * IRQ Source/Acknowledge.
65 */
66 excite_cci_fpga_align_t rm9k_irq_src;
67
68 /**
69 * IRQ Mask.
70 * Set bits enable the related interrupt.
71 */
72 excite_cci_fpga_align_t rm9k_irq_mask;
73#endif
74
75
76} excite_fpga;
77
78
79
80#endif /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
deleted file mode 100644
index c4cf6140622e..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_nandflash.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __EXCITE_NANDFLASH_H__
2#define __EXCITE_NANDFLASH_H__
3
4/* Resource names */
5#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
6
7#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
deleted file mode 100644
index 94705a46f72e..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_eth.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#if !defined(__RM9K_ETH_H__)
2#define __RM9K_ETH_H__
3
4#define RM9K_GE_NAME "rm9k_ge"
5
6/* Resource names */
7#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
8#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
9#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
10#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
11#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
12#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
13#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
14#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
15#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
16#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
17#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
18#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
19#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
20#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
21#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
22
23#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
deleted file mode 100644
index 3fa3c08d2da7..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_wdt.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __RM9K_WDT_H__
2#define __RM9K_WDT_H__
3
4/* Device name */
5#define WDT_NAME "wdt_gpi"
6
7/* Resource names */
8#define WDT_RESOURCE_REGS "excite_watchdog_regs"
9#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
10#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
11
12#endif /* __RM9K_WDT_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
deleted file mode 100644
index 009577734a8d..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_xicap.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __EXCITE_XICAP_H__
2#define __EXCITE_XICAP_H__
3
4
5/* Resource names */
6#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
7#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
8#define XICAP_RESOURCE_XDMA "xicap_xdma"
9#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
10#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
11#define XICAP_RESOURCE_IRQ "xicap_irq"
12#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
13#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
14#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
15
16#endif /* __EXCITE_XICAP_H__ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
new file mode 100644
index 000000000000..021f77ca59ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -0,0 +1,305 @@
1/*
2 * The header file of cs5536 sourth bridge.
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu <liujl@lemote.com>
6 */
7
8#ifndef _CS5536_H
9#define _CS5536_H
10
11#include <linux/types.h>
12
13extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
14extern void _wrmsr(u32 msr, u32 hi, u32 lo);
15
16/*
17 * MSR module base
18 */
19#define CS5536_SB_MSR_BASE (0x00000000)
20#define CS5536_GLIU_MSR_BASE (0x10000000)
21#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
22#define CS5536_USB_MSR_BASE (0x40000000)
23#define CS5536_IDE_MSR_BASE (0x60000000)
24#define CS5536_DIVIL_MSR_BASE (0x80000000)
25#define CS5536_ACC_MSR_BASE (0xa0000000)
26#define CS5536_UNUSED_MSR_BASE (0xc0000000)
27#define CS5536_GLCP_MSR_BASE (0xe0000000)
28
29#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
30#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
31#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
32#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
33#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
34#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
35#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
36#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
37#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
38
39/*
40 * BAR SPACE OF VIRTUAL PCI :
41 * range for pci probe use, length is the actual size.
42 */
43/* IO space for all DIVIL modules */
44#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
45#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
46#define CS5536_SMB_RANGE 0xfffffff8
47#define CS5536_SMB_LENGTH 0x08
48#define CS5536_GPIO_RANGE 0xffffff00
49#define CS5536_GPIO_LENGTH 0x100
50#define CS5536_MFGPT_RANGE 0xffffffc0
51#define CS5536_MFGPT_LENGTH 0x40
52#define CS5536_ACPI_RANGE 0xffffffe0
53#define CS5536_ACPI_LENGTH 0x20
54#define CS5536_PMS_RANGE 0xffffff80
55#define CS5536_PMS_LENGTH 0x80
56/* IO space for IDE */
57#define CS5536_IDE_RANGE 0xfffffff0
58#define CS5536_IDE_LENGTH 0x10
59/* IO space for ACC */
60#define CS5536_ACC_RANGE 0xffffff80
61#define CS5536_ACC_LENGTH 0x80
62/* MEM space for ALL USB modules */
63#define CS5536_OHCI_RANGE 0xfffff000
64#define CS5536_OHCI_LENGTH 0x1000
65#define CS5536_EHCI_RANGE 0xfffff000
66#define CS5536_EHCI_LENGTH 0x1000
67
68/*
69 * PCI MSR ACCESS
70 */
71#define PCI_MSR_CTRL 0xF0
72#define PCI_MSR_ADDR 0xF4
73#define PCI_MSR_DATA_LO 0xF8
74#define PCI_MSR_DATA_HI 0xFC
75
76/**************** MSR *****************************/
77
78/*
79 * GLIU STANDARD MSR
80 */
81#define GLIU_CAP 0x00
82#define GLIU_CONFIG 0x01
83#define GLIU_SMI 0x02
84#define GLIU_ERROR 0x03
85#define GLIU_PM 0x04
86#define GLIU_DIAG 0x05
87
88/*
89 * GLIU SPEC. MSR
90 */
91#define GLIU_P2D_BM0 0x20
92#define GLIU_P2D_BM1 0x21
93#define GLIU_P2D_BM2 0x22
94#define GLIU_P2D_BMK0 0x23
95#define GLIU_P2D_BMK1 0x24
96#define GLIU_P2D_BM3 0x25
97#define GLIU_P2D_BM4 0x26
98#define GLIU_COH 0x80
99#define GLIU_PAE 0x81
100#define GLIU_ARB 0x82
101#define GLIU_ASMI 0x83
102#define GLIU_AERR 0x84
103#define GLIU_DEBUG 0x85
104#define GLIU_PHY_CAP 0x86
105#define GLIU_NOUT_RESP 0x87
106#define GLIU_NOUT_WDATA 0x88
107#define GLIU_WHOAMI 0x8B
108#define GLIU_SLV_DIS 0x8C
109#define GLIU_IOD_BM0 0xE0
110#define GLIU_IOD_BM1 0xE1
111#define GLIU_IOD_BM2 0xE2
112#define GLIU_IOD_BM3 0xE3
113#define GLIU_IOD_BM4 0xE4
114#define GLIU_IOD_BM5 0xE5
115#define GLIU_IOD_BM6 0xE6
116#define GLIU_IOD_BM7 0xE7
117#define GLIU_IOD_BM8 0xE8
118#define GLIU_IOD_BM9 0xE9
119#define GLIU_IOD_SC0 0xEA
120#define GLIU_IOD_SC1 0xEB
121#define GLIU_IOD_SC2 0xEC
122#define GLIU_IOD_SC3 0xED
123#define GLIU_IOD_SC4 0xEE
124#define GLIU_IOD_SC5 0xEF
125#define GLIU_IOD_SC6 0xF0
126#define GLIU_IOD_SC7 0xF1
127
128/*
129 * SB STANDARD
130 */
131#define SB_CAP 0x00
132#define SB_CONFIG 0x01
133#define SB_SMI 0x02
134#define SB_ERROR 0x03
135#define SB_MAR_ERR_EN 0x00000001
136#define SB_TAR_ERR_EN 0x00000002
137#define SB_RSVD_BIT1 0x00000004
138#define SB_EXCEP_ERR_EN 0x00000008
139#define SB_SYSE_ERR_EN 0x00000010
140#define SB_PARE_ERR_EN 0x00000020
141#define SB_TAS_ERR_EN 0x00000040
142#define SB_MAR_ERR_FLAG 0x00010000
143#define SB_TAR_ERR_FLAG 0x00020000
144#define SB_RSVD_BIT2 0x00040000
145#define SB_EXCEP_ERR_FLAG 0x00080000
146#define SB_SYSE_ERR_FLAG 0x00100000
147#define SB_PARE_ERR_FLAG 0x00200000
148#define SB_TAS_ERR_FLAG 0x00400000
149#define SB_PM 0x04
150#define SB_DIAG 0x05
151
152/*
153 * SB SPEC.
154 */
155#define SB_CTRL 0x10
156#define SB_R0 0x20
157#define SB_R1 0x21
158#define SB_R2 0x22
159#define SB_R3 0x23
160#define SB_R4 0x24
161#define SB_R5 0x25
162#define SB_R6 0x26
163#define SB_R7 0x27
164#define SB_R8 0x28
165#define SB_R9 0x29
166#define SB_R10 0x2A
167#define SB_R11 0x2B
168#define SB_R12 0x2C
169#define SB_R13 0x2D
170#define SB_R14 0x2E
171#define SB_R15 0x2F
172
173/*
174 * GLCP STANDARD
175 */
176#define GLCP_CAP 0x00
177#define GLCP_CONFIG 0x01
178#define GLCP_SMI 0x02
179#define GLCP_ERROR 0x03
180#define GLCP_PM 0x04
181#define GLCP_DIAG 0x05
182
183/*
184 * GLCP SPEC.
185 */
186#define GLCP_CLK_DIS_DELAY 0x08
187#define GLCP_PM_CLK_DISABLE 0x09
188#define GLCP_GLB_PM 0x0B
189#define GLCP_DBG_OUT 0x0C
190#define GLCP_RSVD1 0x0D
191#define GLCP_SOFT_COM 0x0E
192#define SOFT_BAR_SMB_FLAG 0x00000001
193#define SOFT_BAR_GPIO_FLAG 0x00000002
194#define SOFT_BAR_MFGPT_FLAG 0x00000004
195#define SOFT_BAR_IRQ_FLAG 0x00000008
196#define SOFT_BAR_PMS_FLAG 0x00000010
197#define SOFT_BAR_ACPI_FLAG 0x00000020
198#define SOFT_BAR_IDE_FLAG 0x00000400
199#define SOFT_BAR_ACC_FLAG 0x00000800
200#define SOFT_BAR_OHCI_FLAG 0x00001000
201#define SOFT_BAR_EHCI_FLAG 0x00002000
202#define GLCP_RSVD2 0x0F
203#define GLCP_CLK_OFF 0x10
204#define GLCP_CLK_ACTIVE 0x11
205#define GLCP_CLK_DISABLE 0x12
206#define GLCP_CLK4ACK 0x13
207#define GLCP_SYS_RST 0x14
208#define GLCP_RSVD3 0x15
209#define GLCP_DBG_CLK_CTRL 0x16
210#define GLCP_CHIP_REV_ID 0x17
211
212/* PIC */
213#define PIC_YSEL_LOW 0x20
214#define PIC_YSEL_LOW_USB_SHIFT 8
215#define PIC_YSEL_LOW_ACC_SHIFT 16
216#define PIC_YSEL_LOW_FLASH_SHIFT 24
217#define PIC_YSEL_HIGH 0x21
218#define PIC_ZSEL_LOW 0x22
219#define PIC_ZSEL_HIGH 0x23
220#define PIC_IRQM_PRIM 0x24
221#define PIC_IRQM_LPC 0x25
222#define PIC_XIRR_STS_LOW 0x26
223#define PIC_XIRR_STS_HIGH 0x27
224#define PCI_SHDW 0x34
225
226/*
227 * DIVIL STANDARD
228 */
229#define DIVIL_CAP 0x00
230#define DIVIL_CONFIG 0x01
231#define DIVIL_SMI 0x02
232#define DIVIL_ERROR 0x03
233#define DIVIL_PM 0x04
234#define DIVIL_DIAG 0x05
235
236/*
237 * DIVIL SPEC.
238 */
239#define DIVIL_LBAR_IRQ 0x08
240#define DIVIL_LBAR_KEL 0x09
241#define DIVIL_LBAR_SMB 0x0B
242#define DIVIL_LBAR_GPIO 0x0C
243#define DIVIL_LBAR_MFGPT 0x0D
244#define DIVIL_LBAR_ACPI 0x0E
245#define DIVIL_LBAR_PMS 0x0F
246#define DIVIL_LEG_IO 0x14
247#define DIVIL_BALL_OPTS 0x15
248#define DIVIL_SOFT_IRQ 0x16
249#define DIVIL_SOFT_RESET 0x17
250
251/* MFGPT */
252#define MFGPT_IRQ 0x28
253
254/*
255 * IDE STANDARD
256 */
257#define IDE_CAP 0x00
258#define IDE_CONFIG 0x01
259#define IDE_SMI 0x02
260#define IDE_ERROR 0x03
261#define IDE_PM 0x04
262#define IDE_DIAG 0x05
263
264/*
265 * IDE SPEC.
266 */
267#define IDE_IO_BAR 0x08
268#define IDE_CFG 0x10
269#define IDE_DTC 0x12
270#define IDE_CAST 0x13
271#define IDE_ETC 0x14
272#define IDE_INTERNAL_PM 0x15
273
274/*
275 * ACC STANDARD
276 */
277#define ACC_CAP 0x00
278#define ACC_CONFIG 0x01
279#define ACC_SMI 0x02
280#define ACC_ERROR 0x03
281#define ACC_PM 0x04
282#define ACC_DIAG 0x05
283
284/*
285 * USB STANDARD
286 */
287#define USB_CAP 0x00
288#define USB_CONFIG 0x01
289#define USB_SMI 0x02
290#define USB_ERROR 0x03
291#define USB_PM 0x04
292#define USB_DIAG 0x05
293
294/*
295 * USB SPEC.
296 */
297#define USB_OHCI 0x08
298#define USB_EHCI 0x09
299
300/****************** NATIVE ***************************/
301/* GPIO : I/O SPACE; REG : 32BITS */
302#define GPIOL_OUT_VAL 0x00
303#define GPIOL_OUT_EN 0x04
304
305#endif /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
new file mode 100644
index 000000000000..4b493d6772c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
@@ -0,0 +1,35 @@
1/*
2 * cs5536 mfgpt header file
3 */
4
5#ifndef _CS5536_MFGPT_H
6#define _CS5536_MFGPT_H
7
8#include <cs5536/cs5536.h>
9#include <cs5536/cs5536_pci.h>
10
11#ifdef CONFIG_CS5536_MFGPT
12extern void setup_mfgpt0_timer(void);
13extern void disable_mfgpt0_counter(void);
14extern void enable_mfgpt0_counter(void);
15#else
16static inline void __maybe_unused setup_mfgpt0_timer(void)
17{
18}
19static inline void __maybe_unused disable_mfgpt0_counter(void)
20{
21}
22static inline void __maybe_unused enable_mfgpt0_counter(void)
23{
24}
25#endif
26
27#define MFGPT_TICK_RATE 14318000
28#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ)
29
30#define MFGPT_BASE mfgpt_base
31#define MFGPT0_CMP2 (MFGPT_BASE + 2)
32#define MFGPT0_CNT (MFGPT_BASE + 4)
33#define MFGPT0_SETUP (MFGPT_BASE + 6)
34
35#endif /*!_CS5536_MFGPT_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
new file mode 100644
index 000000000000..0dca9c89ee7c
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -0,0 +1,153 @@
1/*
2 * the definition file of cs5536 Virtual Support Module(VSM).
3 * pci configuration space can be accessed through the VSM, so
4 * there is no need of the MSR read/write now, except the spec.
5 * MSR registers which are not implemented yet.
6 *
7 * Copyright (C) 2007 Lemote Inc.
8 * Author : jlliu, liujl@lemote.com
9 */
10
11#ifndef _CS5536_PCI_H
12#define _CS5536_PCI_H
13
14#include <linux/types.h>
15#include <linux/pci_regs.h>
16
17extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
18extern u32 cs5536_pci_conf_read4(int function, int reg);
19
20#define CS5536_ACC_INTR 9
21#define CS5536_IDE_INTR 14
22#define CS5536_USB_INTR 11
23#define CS5536_MFGPT_INTR 5
24#define CS5536_UART1_INTR 4
25#define CS5536_UART2_INTR 3
26
27/************** PCI BUS DEVICE FUNCTION ***************/
28
29/*
30 * PCI bus device function
31 */
32#define PCI_BUS_CS5536 0
33#define PCI_IDSEL_CS5536 14
34
35/********** STANDARD PCI-2.2 EXPANSION ****************/
36
37/*
38 * PCI configuration space
39 * we have to virtualize the PCI configure space head, so we should
40 * define the necessary IDs and some others.
41 */
42
43/* CONFIG of PCI VENDOR ID*/
44#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
45 (((mod_dev_id) << 16) | (sys_vendor_id))
46
47/* VENDOR ID */
48#define CS5536_VENDOR_ID 0x1022
49
50/* DEVICE ID */
51#define CS5536_ISA_DEVICE_ID 0x2090
52#define CS5536_IDE_DEVICE_ID 0x209a
53#define CS5536_ACC_DEVICE_ID 0x2093
54#define CS5536_OHCI_DEVICE_ID 0x2094
55#define CS5536_EHCI_DEVICE_ID 0x2095
56
57/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
58#define CS5536_ISA_CLASS_CODE 0x060100
59#define CS5536_IDE_CLASS_CODE 0x010180
60#define CS5536_ACC_CLASS_CODE 0x040100
61#define CS5536_OHCI_CLASS_CODE 0x0C0310
62#define CS5536_EHCI_CLASS_CODE 0x0C0320
63
64/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
65
66#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \
67 ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
68 | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
69
70#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
71#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
72#define PCI_NORMAL_HEADER_TYPE 0x00
73#define PCI_NORMAL_LATENCY_TIMER 0x00
74#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
75
76/* BAR */
77#define PCI_BAR0_REG 0x10
78#define PCI_BAR1_REG 0x14
79#define PCI_BAR2_REG 0x18
80#define PCI_BAR3_REG 0x1c
81#define PCI_BAR4_REG 0x20
82#define PCI_BAR5_REG 0x24
83#define PCI_BAR_COUNT 6
84#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
85
86/* CARDBUS CIS POINTER */
87#define PCI_CARDBUS_CIS_POINTER 0x00000000
88
89/* SUBSYSTEM VENDOR ID */
90#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
91
92/* SUBSYSTEM ID */
93#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
94#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
95#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
96#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
97#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
98
99/* EXPANSION ROM BAR */
100#define PCI_EXPANSION_ROM_BAR 0x00000000
101
102/* CAPABILITIES POINTER */
103#define PCI_CAPLIST_POINTER 0x00000000
104#define PCI_CAPLIST_USB_POINTER 0x40
105/* INTERRUPT */
106
107#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
108 ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
109 ((pin) << 8) | (mod_intr))
110
111#define PCI_MAX_LATENCY 0x40
112#define PCI_MIN_GRANT 0x00
113#define PCI_DEFAULT_PIN 0x01
114
115/*********** EXPANSION PCI REG ************************/
116
117/*
118 * ISA EXPANSION
119 */
120#define PCI_UART1_INT_REG 0x50
121#define PCI_UART2_INT_REG 0x54
122#define PCI_ISA_FIXUP_REG 0x58
123
124/*
125 * IDE EXPANSION
126 */
127#define PCI_IDE_CFG_REG 0x40
128#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
129#define PCI_IDE_DTC_REG 0x48
130#define PCI_IDE_CAST_REG 0x4C
131#define PCI_IDE_ETC_REG 0x50
132#define PCI_IDE_PM_REG 0x54
133#define PCI_IDE_INT_REG 0x60
134
135/*
136 * ACC EXPANSION
137 */
138#define PCI_ACC_INT_REG 0x50
139
140/*
141 * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
142 */
143#define PCI_OHCI_PM_REG 0x40
144#define PCI_OHCI_INT_REG 0x50
145
146/*
147 * EHCI EXPANSION
148 */
149#define PCI_EHCI_LEGSMIEN_REG 0x50
150#define PCI_EHCI_LEGSMISTS_REG 0x54
151#define PCI_EHCI_FLADJ_REG 0x60
152
153#endif /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
new file mode 100644
index 000000000000..6305bea7e18e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -0,0 +1,31 @@
1/*
2 * the read/write interfaces for Virtual Support Module(VSM)
3 *
4 * Copyright (C) 2009 Lemote, Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 */
7
8#ifndef _CS5536_VSM_H
9#define _CS5536_VSM_H
10
11#include <linux/types.h>
12
13typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
14typedef u32 (*cs5536_pci_vsm_read)(int reg);
15
16#define DECLARE_CS5536_MODULE(name) \
17extern void pci_##name##_write_reg(int reg, u32 value); \
18extern u32 pci_##name##_read_reg(int reg);
19
20/* ide module */
21DECLARE_CS5536_MODULE(ide)
22/* acc module */
23DECLARE_CS5536_MODULE(acc)
24/* ohci module */
25DECLARE_CS5536_MODULE(ohci)
26/* isa module */
27DECLARE_CS5536_MODULE(isa)
28/* ehci module */
29DECLARE_CS5536_MODULE(ehci)
30
31#endif /* _CS5536_VSM_H */
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index 71a6851ba833..981c75f91a7d 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
28static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 28static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
29 dma_addr_t dma_addr) 29 dma_addr_t dma_addr)
30{ 30{
31#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
32 return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
33#else
31 return dma_addr & 0x7fffffff; 34 return dma_addr & 0x7fffffff;
35#endif
32} 36}
33 37
34static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, 38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index da70bcf2304e..ee8bc8376972 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -15,9 +15,6 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
19#include <asm/mips-boards/bonito64.h>
20
21/* loongson internal northbridge initialization */ 18/* loongson internal northbridge initialization */
22extern void bonito_irq_init(void); 19extern void bonito_irq_init(void);
23 20
@@ -32,7 +29,19 @@ extern unsigned long memsize, highmemsize;
32/* loongson-specific command line, env and memory initialization */ 29/* loongson-specific command line, env and memory initialization */
33extern void __init prom_init_memory(void); 30extern void __init prom_init_memory(void);
34extern void __init prom_init_cmdline(void); 31extern void __init prom_init_cmdline(void);
32extern void __init prom_init_machtype(void);
35extern void __init prom_init_env(void); 33extern void __init prom_init_env(void);
34#ifdef CONFIG_LOONGSON_UART_BASE
35extern unsigned long _loongson_uart_base, loongson_uart_base;
36extern void prom_init_loongson_uart_base(void);
37#endif
38
39static inline void prom_init_uart_base(void)
40{
41#ifdef CONFIG_LOONGSON_UART_BASE
42 prom_init_loongson_uart_base();
43#endif
44}
36 45
37/* irq operation functions */ 46/* irq operation functions */
38extern void bonito_irqdispatch(void); 47extern void bonito_irqdispatch(void);
@@ -40,25 +49,276 @@ extern void __init bonito_irq_init(void);
40extern void __init set_irq_trigger_mode(void); 49extern void __init set_irq_trigger_mode(void);
41extern void __init mach_init_irq(void); 50extern void __init mach_init_irq(void);
42extern void mach_irq_dispatch(unsigned int pending); 51extern void mach_irq_dispatch(unsigned int pending);
52extern int mach_i8259_irq(void);
53
54/* We need this in some places... */
55#define delay() ({ \
56 int x; \
57 for (x = 0; x < 100000; x++) \
58 __asm__ __volatile__(""); \
59})
60
61#define LOONGSON_REG(x) \
62 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
63
64#define LOONGSON_IRQ_BASE 32
65#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
66
67#define LOONGSON_FLASH_BASE 0x1c000000
68#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
69#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
70
71#define LOONGSON_LIO0_BASE 0x1e000000
72#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
73#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
74
75#define LOONGSON_BOOT_BASE 0x1fc00000
76#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
77#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
78#define LOONGSON_REG_BASE 0x1fe00000
79#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
80#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
81
82#define LOONGSON_LIO1_BASE 0x1ff00000
83#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
84#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
85
86#define LOONGSON_PCILO0_BASE 0x10000000
87#define LOONGSON_PCILO1_BASE 0x14000000
88#define LOONGSON_PCILO2_BASE 0x18000000
89#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
90#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
91#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
92
93#define LOONGSON_PCICFG_BASE 0x1fe80000
94#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
95#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
96#define LOONGSON_PCIIO_BASE 0x1fd00000
97#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
98#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
99
100/* Loongson Register Bases */
101
102#define LOONGSON_PCICONFIGBASE 0x00
103#define LOONGSON_REGBASE 0x100
43 104
44/* PCI Configuration Registers */ 105/* PCI Configuration Registers */
45#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) 106
107#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
108#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
109#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
110#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
111#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
112#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
113#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
114#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
115#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
116#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
117#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
118#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
119
120#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
121
122#define LOONGSON_PCICMD_PERR_CLR 0x80000000
123#define LOONGSON_PCICMD_SERR_CLR 0x40000000
124#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
125#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
126#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
127#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
128#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
129#define LOONGSON_PCICMD_ASTEPEN 0x00000080
130#define LOONGSON_PCICMD_SERREN 0x00000100
131#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
132#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
133
134/* Loongson h/w Configuration */
135
136#define LOONGSON_GENCFG_OFFSET 0x4
137#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
138
139#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
140#define LOONGSON_GENCFG_SNOOPEN 0x00000002
141#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
142
143#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
144#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
145#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
146#define LOONGSON_GENCFG_BYTESWAP 0x00000040
147
148#define LOONGSON_GENCFG_UNCACHED 0x00000080
149#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
150#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
151#define LOONGSON_GENCFG_CACHEALG 0x00000c00
152#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
153#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
154#define LOONGSON_GENCFG_CACHESTOP 0x00002000
155#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
156#define LOONGSON_GENCFG_BUSERREN 0x00008000
157#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
158#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
159
160/* PCI address map control */
161
162#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
163#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
164#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
165
166/* GPIO Regs - r/w */
167
168#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
169#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
170
171/* ICU Configuration Regs - r/w */
172
173#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
174#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
175#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
176
177/* ICU Enable Regs - IntEn & IntISR are r/o. */
178
179#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
180#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
181#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
182#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
183
184/* ICU */
185#define LOONGSON_ICU_MBOXES 0x0000000f
186#define LOONGSON_ICU_MBOXES_SHIFT 0
187#define LOONGSON_ICU_DMARDY 0x00000010
188#define LOONGSON_ICU_DMAEMPTY 0x00000020
189#define LOONGSON_ICU_COPYRDY 0x00000040
190#define LOONGSON_ICU_COPYEMPTY 0x00000080
191#define LOONGSON_ICU_COPYERR 0x00000100
192#define LOONGSON_ICU_PCIIRQ 0x00000200
193#define LOONGSON_ICU_MASTERERR 0x00000400
194#define LOONGSON_ICU_SYSTEMERR 0x00000800
195#define LOONGSON_ICU_DRAMPERR 0x00001000
196#define LOONGSON_ICU_RETRYERR 0x00002000
197#define LOONGSON_ICU_GPIOS 0x01ff0000
198#define LOONGSON_ICU_GPIOS_SHIFT 16
199#define LOONGSON_ICU_GPINS 0x7e000000
200#define LOONGSON_ICU_GPINS_SHIFT 25
201#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
202#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
203#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
204
205/* PCI prefetch window base & mask */
206
207#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
208#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
209#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
210#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
46 211
47/* PCI_Hit*_Sel_* */ 212/* PCI_Hit*_Sel_* */
48 213
49#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) 214#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
50#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) 215#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
51#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) 216#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
52#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) 217#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
53#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) 218#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
54#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) 219#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
55 220
56/* PXArb Config & Status */ 221/* PXArb Config & Status */
57 222
58#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) 223#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
59#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) 224#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
225
226/* pcimap */
227
228#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
229#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
230#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
231#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
232#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
233#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
234#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
235#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
236 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
237
238#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
239#include <linux/cpufreq.h>
240extern void loongson2_cpu_wait(void);
241extern struct cpufreq_frequency_table loongson2_clockmod_table[];
242
243/* Chip Config */
244#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
245#endif
246
247/*
248 * address windows configuration module
249 *
250 * loongson2e do not have this module
251 */
252#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
253
254/* address window config module base address */
255#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
256#define LOONGSON_ADDRWINCFG_SIZE 0x180
257
258extern unsigned long _loongson_addrwincfg_base;
259#define LOONGSON_ADDRWINCFG(offset) \
260 (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
261
262#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
263#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
264#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
265#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
266
267#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
268#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
269#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
270#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
271
272#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
273#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
274#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
275#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
276
277#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
278#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
279#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
280#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
281
282#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
283#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
284#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
285#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
286
287#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
288#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
289#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
290#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
291
292#define ADDRWIN_WIN0 0
293#define ADDRWIN_WIN1 1
294#define ADDRWIN_WIN2 2
295#define ADDRWIN_WIN3 3
296
297#define ADDRWIN_MAP_DST_DDR 0
298#define ADDRWIN_MAP_DST_PCI 1
299#define ADDRWIN_MAP_DST_LIO 1
300
301/*
302 * s: CPU, PCIDMA
303 * d: DDR, PCI, LIO
304 * win: 0, 1, 2, 3
305 * src: map source
306 * dst: map destination
307 * size: ~mask + 1
308 */
309#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
310 s##_WIN##w##_BASE = (src); \
311 s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
312 s##_WIN##w##_MASK = ~(size-1); \
313} while (0)
314
315#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
316 LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
317#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
318 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
319#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
320 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
60 321
61/* loongson2-specific perf counter IRQ */ 322#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
62#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6)
63 323
64#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ 324#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 206ea2067916..acf8359cb135 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -13,10 +13,15 @@
13 13
14#ifdef CONFIG_LEMOTE_FULOONG2E 14#ifdef CONFIG_LEMOTE_FULOONG2E
15 15
16#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
17
18#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E 16#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
19 17
20#endif 18#endif
21 19
20/* use fuloong2f as the default machine of LEMOTE_MACH2F */
21#ifdef CONFIG_LEMOTE_MACH2F
22
23#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
24
25#endif
26
22#endif /* __ASM_MACH_LOONGSON_MACHINE_H */ 27#endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index bd7b3cba7e35..e9960f341b96 100644
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -12,19 +12,30 @@
12#define __ASM_MACH_LOONGSON_MEM_H 12#define __ASM_MACH_LOONGSON_MEM_H
13 13
14/* 14/*
15 * On Lemote Loongson 2e 15 * high memory space
16 * 16 *
17 * the high memory space starts from 512M. 17 * in loongson2e, starts from 512M
18 * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. 18 * in loongson2f, starts from 2G 256M
19 */ 19 */
20#ifdef CONFIG_CPU_LOONGSON2E
21#define LOONGSON_HIGHMEM_START 0x20000000
22#else
23#define LOONGSON_HIGHMEM_START 0x90000000
24#endif
20 25
21#ifdef CONFIG_LEMOTE_FULOONG2E 26/*
22 27 * the peripheral registers(MMIO):
23#define LOONGSON_HIGHMEM_START 0x20000000 28 *
29 * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
30 * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
31 */
24 32
25#define LOONGSON_MMIO_MEM_START 0x10000000 33#define LOONGSON_MMIO_MEM_START 0x10000000
26#define LOONGSON_MMIO_MEM_END 0x20000000
27 34
35#ifdef CONFIG_CPU_LOONGSON2E
36#define LOONGSON_MMIO_MEM_END 0x20000000
37#else
38#define LOONGSON_MMIO_MEM_END 0x80000000
28#endif 39#endif
29 40
30#endif /* __ASM_MACH_LOONGSON_MEM_H */ 41#endif /* __ASM_MACH_LOONGSON_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index f1663ca81da0..a199a4f6de4e 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> 2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
3 * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
3 * 4 *
4 * This program is free software; you can redistribute it 5 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General 6 * and/or modify it under the terms of the GNU General
@@ -22,16 +23,39 @@
22#ifndef __ASM_MACH_LOONGSON_PCI_H_ 23#ifndef __ASM_MACH_LOONGSON_PCI_H_
23#define __ASM_MACH_LOONGSON_PCI_H_ 24#define __ASM_MACH_LOONGSON_PCI_H_
24 25
25extern struct pci_ops bonito64_pci_ops; 26extern struct pci_ops loongson_pci_ops;
26 27
27#ifdef CONFIG_LEMOTE_FULOONG2E 28/* this is an offset from mips_io_port_base */
29#define LOONGSON_PCI_IO_START 0x00004000UL
30
31#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
32
33/*
34 * we use address window2 to map cpu address space to pci space
35 * window2: cpu [1G, 2G] -> pci [1G, 2G]
36 * why not use window 0 & 1? because they are used by cpu when booting.
37 * window0: cpu [0, 256M] -> ddr [0, 256M]
38 * window1: cpu [256M, 512M] -> pci [256M, 512M]
39 */
40
41/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
42#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
43#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
44
45#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
46#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
47
48#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
49 LOONGSON_PCI_MEM_START + 1)
50
51#else /* loongson2f/32bit & loongson2e */
28 52
29/* this pci memory space is mapped by pcimap in pci.c */ 53/* this pci memory space is mapped by pcimap in pci.c */
30#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE 54#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
31#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) 55#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
32/* this is an offset from mips_io_port_base */ 56/* this is an offset from mips_io_port_base */
33#define LOONGSON_PCI_IO_START 0x00004000UL 57#define LOONGSON_PCI_IO_START 0x00004000UL
34 58
35#endif 59#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
36 60
37#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ 61#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
new file mode 100644
index 000000000000..bcad43a93ebf
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_ASIC_H
20#define _ASM_MACH_POWERTV_ASIC_H
21
22#include <linux/ioport.h>
23#include <asm/mach-powertv/asic_regs.h>
24
25#define DVR_CAPABLE (1<<0)
26#define PCIE_CAPABLE (1<<1)
27#define FFS_CAPABLE (1<<2)
28#define DISPLAY_CAPABLE (1<<3)
29
30/* Platform Family types
31 * For compitability, the new value must be added in the end */
32enum family_type {
33 FAMILY_8500,
34 FAMILY_8500RNG,
35 FAMILY_4500,
36 FAMILY_1500,
37 FAMILY_8600,
38 FAMILY_4600,
39 FAMILY_4600VZA,
40 FAMILY_8600VZB,
41 FAMILY_1500VZE,
42 FAMILY_1500VZF,
43 FAMILIES
44};
45
46/* Register maps for each ASIC */
47extern const struct register_map calliope_register_map;
48extern const struct register_map cronus_register_map;
49extern const struct register_map zeus_register_map;
50
51extern struct resource dvr_cronus_resources[];
52extern struct resource dvr_zeus_resources[];
53extern struct resource non_dvr_calliope_resources[];
54extern struct resource non_dvr_cronus_resources[];
55extern struct resource non_dvr_cronuslite_resources[];
56extern struct resource non_dvr_vz_calliope_resources[];
57extern struct resource non_dvr_vze_calliope_resources[];
58extern struct resource non_dvr_vzf_calliope_resources[];
59extern struct resource non_dvr_zeus_resources[];
60
61extern void powertv_platform_init(void);
62extern void platform_alloc_bootmem(void);
63extern enum asic_type platform_get_asic(void);
64extern enum family_type platform_get_family(void);
65extern int platform_supports_dvr(void);
66extern int platform_supports_ffs(void);
67extern int platform_supports_pcie(void);
68extern int platform_supports_display(void);
69extern void configure_platform(void);
70extern void platform_configure_usb_ehci(void);
71extern void platform_unconfigure_usb_ehci(void);
72extern void platform_configure_usb_ohci(void);
73extern void platform_unconfigure_usb_ohci(void);
74
75/* Platform Resources */
76#define ASIC_RESOURCE_GET_EXISTS 1
77extern struct resource *asic_resource_get(const char *name);
78extern void platform_release_memory(void *baddr, int size);
79
80/* Reboot Cause */
81extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
82extern void set_locked_reboot_cause(char code, unsigned int data,
83 unsigned int data2);
84
85enum sys_reboot_type {
86 sys_unknown_reboot = 0x00, /* Unknown reboot cause */
87 sys_davic_change = 0x01, /* Reboot due to change in DAVIC
88 * mode */
89 sys_user_reboot = 0x02, /* Reboot initiated by user */
90 sys_system_reboot = 0x03, /* Reboot initiated by OS */
91 sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
92 sys_silent_reboot = 0x05, /* Silent reboot */
93 sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
94 sys_power_up_reboot = 0x07, /* Power on bootup. Older
95 * drivers may report as
96 * userReboot. */
97 sys_code_change = 0x08, /* Reboot to take code change.
98 * Older drivers may report as
99 * userReboot. */
100 sys_hardware_reset = 0x09, /* HW watchdog or front-panel
101 * reset button reset. Older
102 * drivers may report as
103 * userReboot. */
104 sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
105};
106
107#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
new file mode 100644
index 000000000000..9a65c93782f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -0,0 +1,155 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_MACH_POWERTV_ASIC_H_
20#define __ASM_MACH_POWERTV_ASIC_H_
21#include <linux/io.h>
22
23/* ASIC types */
24enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASICS
31};
32
33/* hardcoded values read from Chip Version registers */
34#define CRONUS_10 0x0B4C1C20
35#define CRONUS_11 0x0B4C1C21
36#define CRONUSLITE_10 0x0B4C1C40
37
38#define NAND_FLASH_BASE 0x03000000
39#define ZEUS_IO_BASE 0x09000000
40#define CALLIOPE_IO_BASE 0x08000000
41#define CRONUS_IO_BASE 0x09000000
42#define ASIC_IO_SIZE 0x01000000
43
44/* Definitions for backward compatibility */
45#define UART1_INTSTAT uart1_intstat
46#define UART1_INTEN uart1_inten
47#define UART1_CONFIG1 uart1_config1
48#define UART1_CONFIG2 uart1_config2
49#define UART1_DIVISORHI uart1_divisorhi
50#define UART1_DIVISORLO uart1_divisorlo
51#define UART1_DATA uart1_data
52#define UART1_STATUS uart1_status
53
54/* ASIC register enumeration */
55struct register_map {
56 u32 eic_slow0_strt_add;
57 u32 eic_cfg_bits;
58 u32 eic_ready_status;
59
60 u32 chipver3;
61 u32 chipver2;
62 u32 chipver1;
63 u32 chipver0;
64
65 u32 uart1_intstat;
66 u32 uart1_inten;
67 u32 uart1_config1;
68 u32 uart1_config2;
69 u32 uart1_divisorhi;
70 u32 uart1_divisorlo;
71 u32 uart1_data;
72 u32 uart1_status;
73
74 u32 int_stat_3;
75 u32 int_stat_2;
76 u32 int_stat_1;
77 u32 int_stat_0;
78 u32 int_config;
79 u32 int_int_scan;
80 u32 ien_int_3;
81 u32 ien_int_2;
82 u32 ien_int_1;
83 u32 ien_int_0;
84 u32 int_level_3_3;
85 u32 int_level_3_2;
86 u32 int_level_3_1;
87 u32 int_level_3_0;
88 u32 int_level_2_3;
89 u32 int_level_2_2;
90 u32 int_level_2_1;
91 u32 int_level_2_0;
92 u32 int_level_1_3;
93 u32 int_level_1_2;
94 u32 int_level_1_1;
95 u32 int_level_1_0;
96 u32 int_level_0_3;
97 u32 int_level_0_2;
98 u32 int_level_0_1;
99 u32 int_level_0_0;
100 u32 int_docsis_en;
101
102 u32 mips_pll_setup;
103 u32 usb_fs;
104 u32 test_bus;
105 u32 crt_spare;
106 u32 usb2_ohci_int_mask;
107 u32 usb2_strap;
108 u32 ehci_hcapbase;
109 u32 ohci_hc_revision;
110 u32 bcm1_bs_lmi_steer;
111 u32 usb2_control;
112 u32 usb2_stbus_obc;
113 u32 usb2_stbus_mess_size;
114 u32 usb2_stbus_chunk_size;
115
116 u32 pcie_regs;
117 u32 tim_ch;
118 u32 tim_cl;
119 u32 gpio_dout;
120 u32 gpio_din;
121 u32 gpio_dir;
122 u32 watchdog;
123 u32 front_panel;
124
125 u32 register_maps;
126};
127
128extern enum asic_type asic;
129extern const struct register_map *register_map;
130extern unsigned long asic_phy_base; /* Physical address of ASIC */
131extern unsigned long asic_base; /* Virtual address of ASIC */
132
133/*
134 * Macros to interface to registers through their ioremapped address
135 * asic_reg_offset Returns the offset of a given register from the start
136 * of the ASIC address space
137 * asic_reg_phys_addr Returns the physical address of the given register
138 * asic_reg_addr Returns the iomapped virtual address of the given
139 * register.
140 */
141#define asic_reg_offset(x) (register_map->x)
142#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x))
143#define asic_reg_addr(x) \
144 ((unsigned int *) (asic_base + asic_reg_offset(x)))
145
146/*
147 * The asic_reg macro is gone. It should be replaced by either asic_read or
148 * asic_write, as appropriate.
149 */
150
151#define asic_read(x) readl(asic_reg_addr(x))
152#define asic_write(v, x) writel(v, asic_reg_addr(x))
153
154extern void asic_irq_init(void);
155#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
new file mode 100644
index 000000000000..5b8d5ebeb838
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -0,0 +1,119 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Version from mach-generic modified to support PowerTV port
7 * Portions Copyright (C) 2009 Cisco Systems, Inc.
8 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 *
10 */
11
12#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14
15#include <linux/sched.h>
16#include <linux/version.h>
17#include <linux/device.h>
18#include <asm/mach-powertv/asic.h>
19
20static inline bool is_kseg2(void *addr)
21{
22 return (unsigned long)addr >= KSEG2;
23}
24
25static inline unsigned long virt_to_phys_from_pte(void *addr)
26{
27 pgd_t *pgd;
28 pud_t *pud;
29 pmd_t *pmd;
30 pte_t *ptep, pte;
31
32 unsigned long virt_addr = (unsigned long)addr;
33 unsigned long phys_addr = 0UL;
34
35 /* get the page global directory. */
36 pgd = pgd_offset_k(virt_addr);
37
38 if (!pgd_none(*pgd)) {
39 /* get the page upper directory */
40 pud = pud_offset(pgd, virt_addr);
41 if (!pud_none(*pud)) {
42 /* get the page middle directory */
43 pmd = pmd_offset(pud, virt_addr);
44 if (!pmd_none(*pmd)) {
45 /* get a pointer to the page table entry */
46 ptep = pte_offset(pmd, virt_addr);
47 pte = *ptep;
48 /* check for a valid page */
49 if (pte_present(pte)) {
50 /* get the physical address the page is
51 * refering to */
52 phys_addr = (unsigned long)
53 page_to_phys(pte_page(pte));
54 /* add the offset within the page */
55 phys_addr |= (virt_addr & ~PAGE_MASK);
56 }
57 }
58 }
59 }
60
61 return phys_addr;
62}
63
64static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
65 size_t size)
66{
67 if (is_kseg2(addr))
68 return phys_to_bus(virt_to_phys_from_pte(addr));
69 else
70 return phys_to_bus(virt_to_phys(addr));
71}
72
73static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
74 struct page *page)
75{
76 return phys_to_bus(page_to_phys(page));
77}
78
79static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
80 dma_addr_t dma_addr)
81{
82 return bus_to_phys(dma_addr);
83}
84
85static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
86 size_t size, enum dma_data_direction direction)
87{
88}
89
90static inline int plat_dma_supported(struct device *dev, u64 mask)
91{
92 /*
93 * we fall back to GFP_DMA when the mask isn't all 1s,
94 * so we can't guarantee allocations that must be
95 * within a tighter range than GFP_DMA..
96 */
97 if (mask < DMA_BIT_MASK(24))
98 return 0;
99
100 return 1;
101}
102
103static inline void plat_extra_sync_for_device(struct device *dev)
104{
105 return;
106}
107
108static inline int plat_dma_mapping_error(struct device *dev,
109 dma_addr_t dma_addr)
110{
111 return 0;
112}
113
114static inline int plat_device_is_coherent(struct device *dev)
115{
116 return 0;
117}
118
119#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
new file mode 100644
index 000000000000..629a57413657
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -0,0 +1,254 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21
22/*
23 * Defines for all of the interrupt lines
24 */
25
26/* Definitions for backward compatibility */
27#define kIrq_Uart1 irq_uart1
28
29#define ibase 0
30
31/*------------- Register: int_stat_3 */
32/* 126 unused (bit 31) */
33#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39 * Interrupt */
40#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42 * -- Ored by glue logic inside
43 * SPARC ILC (see
44 * INT_MEM_PROT_STAT, below,
45 * for individual interrupts)
46 */
47/* 118 unused (bit 22) */
48#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside
57 * SPARC ILC (see
58 * INT_MAILBOX_STAT, below, for
59 * individual interrupts) */
60#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63 * Status 3 */
64#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65 * Status 3 */
66#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67 * Interrupt */
68#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69 * Interrupt */
70#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71 * Interrupt */
72#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73 * Interrupt */
74#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75 * Interrupt */
76#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77 * Interrupt */
78#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80 * Interrupt */
81#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87/*------------- Register: int_stat_2 */
88#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90#define irq_timer2 (ibase+93) /* Programmable Timer
91 * Interrupt 2 */
92#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108 * Host module) */
109#define irq_pod (ibase+78) /* POD Interrupt */
110#define irq_slave_usb (ibase+77) /* Slave USB */
111#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */
139#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */
147#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148 * Interrupt */
149#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150 * Interrupt */
151#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152 * (Chans 63-32) */
153#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154 * (Chans 31-0) */
155#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156 * (Chans 63-32) */
157#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158 * (Chans 31-0) */
159#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160 * Interrupt */
161#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163 * Interrupt */
164#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */
173#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174 * (PEI) */
175#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176 * detect */
177#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178/*------------- Register: int_stat_0 */
179#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180 * Module */
181#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182 * Module */
183#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184 * (chan 3) Transmission
185 * Completed OK */
186#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187 * Transmission Completed OK */
188#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189 * (chan 1) Transmission
190 * Completed OK */
191#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192 * (chan 3)Transmission
193 * completed with Errors. */
194#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195 * Transmission completed with
196 * Errors. */
197#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198 * (chan 1) Transmission
199 * completed with Errors */
200#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201 * for N times. Aloha retry
202 * timeout for channel 3. */
203#define irq_timer1 (ibase+22) /* Programmable Timer
204 * Interrupt */
205#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207#define irq_spi (ibase+19) /* SPI Module Interrupt */
208#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210 * Splice Detect Interrupt */
211#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212 * Interrupt */
213#define irq_uart1 (ibase+15) /* UART Interrupt */
214#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */
220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference -
228 * every 3ms when forward Mbits
229 * and forward slot control
230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference -
233 * delayed from forward mark by
234 * the ranging delay plus a
235 * fixed amount. When reverse
236 * Mbits and reverse slot
237 * control bytes are updated.
238 * Occurs every 3ms for 3.0M and
239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream
241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed
246 * or Slotted aloha verify for
247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation
250 * increment completed for
251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
254
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
new file mode 100644
index 000000000000..e6276d5146e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -0,0 +1,90 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * Portions Copyright (C) Cisco Systems, Inc.
8 */
9#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10#define __ASM_MACH_POWERTV_IOREMAP_H
11
12#include <linux/types.h>
13
14#define LOW_MEM_BOUNDARY_PHYS 0x20000000
15#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1))
16
17/*
18 * The bus addresses are different than the physical addresses that
19 * the processor sees by an offset. This offset varies by ASIC
20 * version. Define a variable to hold the offset and some macros to
21 * make the conversion simpler. */
22extern unsigned long phys_to_bus_offset;
23
24#ifdef CONFIG_HIGHMEM
25#define MEM_GAP_PHYS 0x60000000
26/*
27 * TODO: We will use the hard code for conversion between physical and
28 * bus until the bootloader releases their device tree to us.
29 */
30#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
31 ((x) + phys_to_bus_offset) : (x))
32#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
33 ((x) - phys_to_bus_offset) : (x))
34#else
35#define phys_to_bus(x) ((x) + phys_to_bus_offset)
36#define bus_to_phys(x) ((x) - phys_to_bus_offset)
37#endif
38
39/*
40 * Determine whether the address we are given is for an ASIC device
41 * Params: addr Address to check
42 * Returns: Zero if the address is not for ASIC devices, non-zero
43 * if it is.
44 */
45static inline int asic_is_device_addr(phys_t addr)
46{
47 return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
48}
49
50/*
51 * Determine whether the address we are given is external RAM mappable
52 * into KSEG1.
53 * Params: addr Address to check
54 * Returns: Zero if the address is not for external RAM and
55 */
56static inline int asic_is_lowmem_ram_addr(phys_t addr)
57{
58 /*
59 * The RAM always starts at the following address in the processor's
60 * physical address space
61 */
62 static const phys_t phys_ram_base = 0x10000000;
63 phys_t bus_ram_base;
64
65 bus_ram_base = phys_to_bus_offset + phys_ram_base;
66
67 return addr >= bus_ram_base &&
68 addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
69}
70
71/*
72 * Allow physical addresses to be fixed up to help peripherals located
73 * outside the low 32-bit range -- generic pass-through version.
74 */
75static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
76{
77 return phys_addr;
78}
79
80static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
81 unsigned long flags)
82{
83 return NULL;
84}
85
86static inline int plat_iounmap(const volatile void __iomem *addr)
87{
88 return 0;
89}
90#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
new file mode 100644
index 000000000000..4bd5d0c61a91
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/irq.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_IRQ_H
20#define _ASM_MACH_POWERTV_IRQ_H
21#include <asm/mach-powertv/interrupts.h>
22
23#define MIPS_CPU_IRQ_BASE ibase
24#define NR_IRQS 127
25#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
new file mode 100644
index 000000000000..6f3e9a0fcf8c
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18/*
19 * Local definitions for the powertv PCI code
20 */
21
22#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23#define _POWERTV_PCI_POWERTV_PCI_H_
24extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25extern int asic_pcie_init(void);
26extern int asic_pcie_init(void);
27
28extern int log_level;
29#endif
diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 1f82180c1598..7ac05ecc512b 100644
--- a/arch/mips/include/asm/mach-excite/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -3,10 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * This version for the PowerTV platform copied from the Malta version.
7 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
7 */ 10 */
8#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H 11#ifndef __ASM_MACH_POWERTV_WAR_H
9#define __ASM_MIPS_MACH_EXCITE_WAR_H 12#define __ASM_MACH_POWERTV_WAR_H
10 13
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 14#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 15#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -14,12 +17,12 @@
14#define R5432_CP0_INTERRUPT_WAR 0 17#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0 18#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0 19#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0 20#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0 21#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 22#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1 23#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 24#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 25#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 26#define MIPS34K_MISSED_ITLB_WAR 0
24 27
25#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ 28#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a576ce044c3c..d14e2adc4be5 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -26,11 +26,6 @@
26/* offsets from base register */ 26/* offsets from base register */
27#define BONITO(x) (x) 27#define BONITO(x) (x)
28 28
29#elif defined(CONFIG_LEMOTE_FULOONG2E)
30
31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32#define BONITO_IRQ_BASE 32
33
34#else 29#else
35 30
36/* 31/*
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 6083db586500..145bb81ccaa5 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -24,6 +24,33 @@
24#endif /* SMTC */ 24#endif /* SMTC */
25#include <asm-generic/mm_hooks.h> 25#include <asm-generic/mm_hooks.h>
26 26
27#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30 tlbmiss_handler_setup_pgd((unsigned long)(pgd))
31
32static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
33{
34 /* Check for swapper_pg_dir and convert to physical address. */
35 if ((pgd & CKSEG3) == CKSEG0)
36 pgd = CPHYSADDR(pgd);
37 write_c0_context(pgd << 11);
38}
39
40#define TLBMISS_HANDLER_SETUP() \
41 do { \
42 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
43 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
44 } while (0)
45
46
47static inline unsigned long get_current_pgd(void)
48{
49 return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
50}
51
52#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
53
27/* 54/*
28 * For the fast tlb miss handlers, we keep a per cpu array of pointers 55 * For the fast tlb miss handlers, we keep a per cpu array of pointers
29 * to the current pgd for each processor. Also, the proc. id is stuffed 56 * to the current pgd for each processor. Also, the proc. id is stuffed
@@ -46,7 +73,7 @@ extern unsigned long pgd_current[];
46 back_to_back_c0_hazard(); \ 73 back_to_back_c0_hazard(); \
47 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 74 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
48#endif 75#endif
49 76#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
50#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 77#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
51 78
52#define ASID_INC 0x40 79#define ASID_INC 0x40
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
new file mode 100644
index 000000000000..ec94b9ab7be1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -0,0 +1,1194 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_AGL_DEFS_H__
29#define __CVMX_AGL_DEFS_H__
30
31#define CVMX_AGL_GMX_BAD_REG \
32 CVMX_ADD_IO_SEG(0x00011800E0000518ull)
33#define CVMX_AGL_GMX_BIST \
34 CVMX_ADD_IO_SEG(0x00011800E0000400ull)
35#define CVMX_AGL_GMX_DRV_CTL \
36 CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
37#define CVMX_AGL_GMX_INF_MODE \
38 CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
39#define CVMX_AGL_GMX_PRTX_CFG(offset) \
40 CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
41#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
42 CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
43#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
44 CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
45#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
46 CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
47#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
48 CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
49#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
50 CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
51#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
52 CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
53#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
54 CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
55#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
56 CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
57#define CVMX_AGL_GMX_RXX_DECISION(offset) \
58 CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
59#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
60 CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
61#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
62 CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
63#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
64 CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
65#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
66 CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
67#define CVMX_AGL_GMX_RXX_IFG(offset) \
68 CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
69#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
70 CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
71#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
72 CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
73#define CVMX_AGL_GMX_RXX_JABBER(offset) \
74 CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
75#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
76 CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
77#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
78 CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
79#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
80 CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
81#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
82 CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
83#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
84 CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
85#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
86 CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
87#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
88 CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
89#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
90 CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
91#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
92 CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
93#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
94 CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
95#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
96 CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
97#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
98 CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
99#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
100 CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
101#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
102 CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
103#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
104 CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
105#define CVMX_AGL_GMX_RX_PRT_INFO \
106 CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
107#define CVMX_AGL_GMX_RX_TX_STATUS \
108 CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
109#define CVMX_AGL_GMX_SMACX(offset) \
110 CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
111#define CVMX_AGL_GMX_STAT_BP \
112 CVMX_ADD_IO_SEG(0x00011800E0000520ull)
113#define CVMX_AGL_GMX_TXX_APPEND(offset) \
114 CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
115#define CVMX_AGL_GMX_TXX_CTL(offset) \
116 CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
117#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
118 CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
119#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
120 CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
121#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
122 CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
123#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
124 CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
125#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
126 CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
127#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
128 CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
129#define CVMX_AGL_GMX_TXX_STAT0(offset) \
130 CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
131#define CVMX_AGL_GMX_TXX_STAT1(offset) \
132 CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
133#define CVMX_AGL_GMX_TXX_STAT2(offset) \
134 CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
135#define CVMX_AGL_GMX_TXX_STAT3(offset) \
136 CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
137#define CVMX_AGL_GMX_TXX_STAT4(offset) \
138 CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
139#define CVMX_AGL_GMX_TXX_STAT5(offset) \
140 CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
141#define CVMX_AGL_GMX_TXX_STAT6(offset) \
142 CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
143#define CVMX_AGL_GMX_TXX_STAT7(offset) \
144 CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
145#define CVMX_AGL_GMX_TXX_STAT8(offset) \
146 CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
147#define CVMX_AGL_GMX_TXX_STAT9(offset) \
148 CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
149#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
150 CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
151#define CVMX_AGL_GMX_TXX_THRESH(offset) \
152 CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
153#define CVMX_AGL_GMX_TX_BP \
154 CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
155#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
156 CVMX_ADD_IO_SEG(0x00011800E0000498ull)
157#define CVMX_AGL_GMX_TX_IFG \
158 CVMX_ADD_IO_SEG(0x00011800E0000488ull)
159#define CVMX_AGL_GMX_TX_INT_EN \
160 CVMX_ADD_IO_SEG(0x00011800E0000508ull)
161#define CVMX_AGL_GMX_TX_INT_REG \
162 CVMX_ADD_IO_SEG(0x00011800E0000500ull)
163#define CVMX_AGL_GMX_TX_JAM \
164 CVMX_ADD_IO_SEG(0x00011800E0000490ull)
165#define CVMX_AGL_GMX_TX_LFSR \
166 CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
167#define CVMX_AGL_GMX_TX_OVR_BP \
168 CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
169#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
170 CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
171#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
172 CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
173
174union cvmx_agl_gmx_bad_reg {
175 uint64_t u64;
176 struct cvmx_agl_gmx_bad_reg_s {
177 uint64_t reserved_38_63:26;
178 uint64_t txpsh1:1;
179 uint64_t txpop1:1;
180 uint64_t ovrflw1:1;
181 uint64_t txpsh:1;
182 uint64_t txpop:1;
183 uint64_t ovrflw:1;
184 uint64_t reserved_27_31:5;
185 uint64_t statovr:1;
186 uint64_t reserved_23_25:3;
187 uint64_t loststat:1;
188 uint64_t reserved_4_21:18;
189 uint64_t out_ovr:2;
190 uint64_t reserved_0_1:2;
191 } s;
192 struct cvmx_agl_gmx_bad_reg_s cn52xx;
193 struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
194 struct cvmx_agl_gmx_bad_reg_cn56xx {
195 uint64_t reserved_35_63:29;
196 uint64_t txpsh:1;
197 uint64_t txpop:1;
198 uint64_t ovrflw:1;
199 uint64_t reserved_27_31:5;
200 uint64_t statovr:1;
201 uint64_t reserved_23_25:3;
202 uint64_t loststat:1;
203 uint64_t reserved_3_21:19;
204 uint64_t out_ovr:1;
205 uint64_t reserved_0_1:2;
206 } cn56xx;
207 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
208};
209
210union cvmx_agl_gmx_bist {
211 uint64_t u64;
212 struct cvmx_agl_gmx_bist_s {
213 uint64_t reserved_10_63:54;
214 uint64_t status:10;
215 } s;
216 struct cvmx_agl_gmx_bist_s cn52xx;
217 struct cvmx_agl_gmx_bist_s cn52xxp1;
218 struct cvmx_agl_gmx_bist_s cn56xx;
219 struct cvmx_agl_gmx_bist_s cn56xxp1;
220};
221
222union cvmx_agl_gmx_drv_ctl {
223 uint64_t u64;
224 struct cvmx_agl_gmx_drv_ctl_s {
225 uint64_t reserved_49_63:15;
226 uint64_t byp_en1:1;
227 uint64_t reserved_45_47:3;
228 uint64_t pctl1:5;
229 uint64_t reserved_37_39:3;
230 uint64_t nctl1:5;
231 uint64_t reserved_17_31:15;
232 uint64_t byp_en:1;
233 uint64_t reserved_13_15:3;
234 uint64_t pctl:5;
235 uint64_t reserved_5_7:3;
236 uint64_t nctl:5;
237 } s;
238 struct cvmx_agl_gmx_drv_ctl_s cn52xx;
239 struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
240 struct cvmx_agl_gmx_drv_ctl_cn56xx {
241 uint64_t reserved_17_63:47;
242 uint64_t byp_en:1;
243 uint64_t reserved_13_15:3;
244 uint64_t pctl:5;
245 uint64_t reserved_5_7:3;
246 uint64_t nctl:5;
247 } cn56xx;
248 struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
249};
250
251union cvmx_agl_gmx_inf_mode {
252 uint64_t u64;
253 struct cvmx_agl_gmx_inf_mode_s {
254 uint64_t reserved_2_63:62;
255 uint64_t en:1;
256 uint64_t reserved_0_0:1;
257 } s;
258 struct cvmx_agl_gmx_inf_mode_s cn52xx;
259 struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
260 struct cvmx_agl_gmx_inf_mode_s cn56xx;
261 struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
262};
263
264union cvmx_agl_gmx_prtx_cfg {
265 uint64_t u64;
266 struct cvmx_agl_gmx_prtx_cfg_s {
267 uint64_t reserved_6_63:58;
268 uint64_t tx_en:1;
269 uint64_t rx_en:1;
270 uint64_t slottime:1;
271 uint64_t duplex:1;
272 uint64_t speed:1;
273 uint64_t en:1;
274 } s;
275 struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
276 struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
277 struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
278 struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
279};
280
281union cvmx_agl_gmx_rxx_adr_cam0 {
282 uint64_t u64;
283 struct cvmx_agl_gmx_rxx_adr_cam0_s {
284 uint64_t adr:64;
285 } s;
286 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
287 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
288 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
289 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
290};
291
292union cvmx_agl_gmx_rxx_adr_cam1 {
293 uint64_t u64;
294 struct cvmx_agl_gmx_rxx_adr_cam1_s {
295 uint64_t adr:64;
296 } s;
297 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
298 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
299 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
300 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
301};
302
303union cvmx_agl_gmx_rxx_adr_cam2 {
304 uint64_t u64;
305 struct cvmx_agl_gmx_rxx_adr_cam2_s {
306 uint64_t adr:64;
307 } s;
308 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
309 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
310 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
311 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
312};
313
314union cvmx_agl_gmx_rxx_adr_cam3 {
315 uint64_t u64;
316 struct cvmx_agl_gmx_rxx_adr_cam3_s {
317 uint64_t adr:64;
318 } s;
319 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
320 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
321 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
322 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
323};
324
325union cvmx_agl_gmx_rxx_adr_cam4 {
326 uint64_t u64;
327 struct cvmx_agl_gmx_rxx_adr_cam4_s {
328 uint64_t adr:64;
329 } s;
330 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
331 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
332 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
333 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
334};
335
336union cvmx_agl_gmx_rxx_adr_cam5 {
337 uint64_t u64;
338 struct cvmx_agl_gmx_rxx_adr_cam5_s {
339 uint64_t adr:64;
340 } s;
341 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
342 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
343 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
344 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
345};
346
347union cvmx_agl_gmx_rxx_adr_cam_en {
348 uint64_t u64;
349 struct cvmx_agl_gmx_rxx_adr_cam_en_s {
350 uint64_t reserved_8_63:56;
351 uint64_t en:8;
352 } s;
353 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
354 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
355 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
356 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
357};
358
359union cvmx_agl_gmx_rxx_adr_ctl {
360 uint64_t u64;
361 struct cvmx_agl_gmx_rxx_adr_ctl_s {
362 uint64_t reserved_4_63:60;
363 uint64_t cam_mode:1;
364 uint64_t mcst:2;
365 uint64_t bcst:1;
366 } s;
367 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
368 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
369 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
370 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
371};
372
373union cvmx_agl_gmx_rxx_decision {
374 uint64_t u64;
375 struct cvmx_agl_gmx_rxx_decision_s {
376 uint64_t reserved_5_63:59;
377 uint64_t cnt:5;
378 } s;
379 struct cvmx_agl_gmx_rxx_decision_s cn52xx;
380 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
381 struct cvmx_agl_gmx_rxx_decision_s cn56xx;
382 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
383};
384
385union cvmx_agl_gmx_rxx_frm_chk {
386 uint64_t u64;
387 struct cvmx_agl_gmx_rxx_frm_chk_s {
388 uint64_t reserved_9_63:55;
389 uint64_t skperr:1;
390 uint64_t rcverr:1;
391 uint64_t lenerr:1;
392 uint64_t alnerr:1;
393 uint64_t fcserr:1;
394 uint64_t jabber:1;
395 uint64_t maxerr:1;
396 uint64_t reserved_1_1:1;
397 uint64_t minerr:1;
398 } s;
399 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
400 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
401 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
402 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
403};
404
405union cvmx_agl_gmx_rxx_frm_ctl {
406 uint64_t u64;
407 struct cvmx_agl_gmx_rxx_frm_ctl_s {
408 uint64_t reserved_10_63:54;
409 uint64_t pre_align:1;
410 uint64_t pad_len:1;
411 uint64_t vlan_len:1;
412 uint64_t pre_free:1;
413 uint64_t ctl_smac:1;
414 uint64_t ctl_mcst:1;
415 uint64_t ctl_bck:1;
416 uint64_t ctl_drp:1;
417 uint64_t pre_strp:1;
418 uint64_t pre_chk:1;
419 } s;
420 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
421 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
422 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
423 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
424};
425
426union cvmx_agl_gmx_rxx_frm_max {
427 uint64_t u64;
428 struct cvmx_agl_gmx_rxx_frm_max_s {
429 uint64_t reserved_16_63:48;
430 uint64_t len:16;
431 } s;
432 struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
433 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
434 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
435 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
436};
437
438union cvmx_agl_gmx_rxx_frm_min {
439 uint64_t u64;
440 struct cvmx_agl_gmx_rxx_frm_min_s {
441 uint64_t reserved_16_63:48;
442 uint64_t len:16;
443 } s;
444 struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
445 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
446 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
447 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
448};
449
450union cvmx_agl_gmx_rxx_ifg {
451 uint64_t u64;
452 struct cvmx_agl_gmx_rxx_ifg_s {
453 uint64_t reserved_4_63:60;
454 uint64_t ifg:4;
455 } s;
456 struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
457 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
458 struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
459 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
460};
461
462union cvmx_agl_gmx_rxx_int_en {
463 uint64_t u64;
464 struct cvmx_agl_gmx_rxx_int_en_s {
465 uint64_t reserved_20_63:44;
466 uint64_t pause_drp:1;
467 uint64_t reserved_16_18:3;
468 uint64_t ifgerr:1;
469 uint64_t coldet:1;
470 uint64_t falerr:1;
471 uint64_t rsverr:1;
472 uint64_t pcterr:1;
473 uint64_t ovrerr:1;
474 uint64_t reserved_9_9:1;
475 uint64_t skperr:1;
476 uint64_t rcverr:1;
477 uint64_t lenerr:1;
478 uint64_t alnerr:1;
479 uint64_t fcserr:1;
480 uint64_t jabber:1;
481 uint64_t maxerr:1;
482 uint64_t reserved_1_1:1;
483 uint64_t minerr:1;
484 } s;
485 struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
486 struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
487 struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
488 struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
489};
490
491union cvmx_agl_gmx_rxx_int_reg {
492 uint64_t u64;
493 struct cvmx_agl_gmx_rxx_int_reg_s {
494 uint64_t reserved_20_63:44;
495 uint64_t pause_drp:1;
496 uint64_t reserved_16_18:3;
497 uint64_t ifgerr:1;
498 uint64_t coldet:1;
499 uint64_t falerr:1;
500 uint64_t rsverr:1;
501 uint64_t pcterr:1;
502 uint64_t ovrerr:1;
503 uint64_t reserved_9_9:1;
504 uint64_t skperr:1;
505 uint64_t rcverr:1;
506 uint64_t lenerr:1;
507 uint64_t alnerr:1;
508 uint64_t fcserr:1;
509 uint64_t jabber:1;
510 uint64_t maxerr:1;
511 uint64_t reserved_1_1:1;
512 uint64_t minerr:1;
513 } s;
514 struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
515 struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
516 struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
517 struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
518};
519
520union cvmx_agl_gmx_rxx_jabber {
521 uint64_t u64;
522 struct cvmx_agl_gmx_rxx_jabber_s {
523 uint64_t reserved_16_63:48;
524 uint64_t cnt:16;
525 } s;
526 struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
527 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
528 struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
529 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
530};
531
532union cvmx_agl_gmx_rxx_pause_drop_time {
533 uint64_t u64;
534 struct cvmx_agl_gmx_rxx_pause_drop_time_s {
535 uint64_t reserved_16_63:48;
536 uint64_t status:16;
537 } s;
538 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
539 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
540 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
541 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
542};
543
544union cvmx_agl_gmx_rxx_stats_ctl {
545 uint64_t u64;
546 struct cvmx_agl_gmx_rxx_stats_ctl_s {
547 uint64_t reserved_1_63:63;
548 uint64_t rd_clr:1;
549 } s;
550 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
551 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
552 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
553 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
554};
555
556union cvmx_agl_gmx_rxx_stats_octs {
557 uint64_t u64;
558 struct cvmx_agl_gmx_rxx_stats_octs_s {
559 uint64_t reserved_48_63:16;
560 uint64_t cnt:48;
561 } s;
562 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
563 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
564 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
565 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
566};
567
568union cvmx_agl_gmx_rxx_stats_octs_ctl {
569 uint64_t u64;
570 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
571 uint64_t reserved_48_63:16;
572 uint64_t cnt:48;
573 } s;
574 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
575 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
576 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
577 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
578};
579
580union cvmx_agl_gmx_rxx_stats_octs_dmac {
581 uint64_t u64;
582 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
583 uint64_t reserved_48_63:16;
584 uint64_t cnt:48;
585 } s;
586 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
587 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
588 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
589 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
590};
591
592union cvmx_agl_gmx_rxx_stats_octs_drp {
593 uint64_t u64;
594 struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
595 uint64_t reserved_48_63:16;
596 uint64_t cnt:48;
597 } s;
598 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
599 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
600 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
601 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
602};
603
604union cvmx_agl_gmx_rxx_stats_pkts {
605 uint64_t u64;
606 struct cvmx_agl_gmx_rxx_stats_pkts_s {
607 uint64_t reserved_32_63:32;
608 uint64_t cnt:32;
609 } s;
610 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
611 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
612 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
613 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
614};
615
616union cvmx_agl_gmx_rxx_stats_pkts_bad {
617 uint64_t u64;
618 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
619 uint64_t reserved_32_63:32;
620 uint64_t cnt:32;
621 } s;
622 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
623 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
624 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
625 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
626};
627
628union cvmx_agl_gmx_rxx_stats_pkts_ctl {
629 uint64_t u64;
630 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
631 uint64_t reserved_32_63:32;
632 uint64_t cnt:32;
633 } s;
634 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
635 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
636 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
637 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
638};
639
640union cvmx_agl_gmx_rxx_stats_pkts_dmac {
641 uint64_t u64;
642 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
643 uint64_t reserved_32_63:32;
644 uint64_t cnt:32;
645 } s;
646 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
647 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
648 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
649 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
650};
651
652union cvmx_agl_gmx_rxx_stats_pkts_drp {
653 uint64_t u64;
654 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
655 uint64_t reserved_32_63:32;
656 uint64_t cnt:32;
657 } s;
658 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
659 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
660 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
661 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
662};
663
664union cvmx_agl_gmx_rxx_udd_skp {
665 uint64_t u64;
666 struct cvmx_agl_gmx_rxx_udd_skp_s {
667 uint64_t reserved_9_63:55;
668 uint64_t fcssel:1;
669 uint64_t reserved_7_7:1;
670 uint64_t len:7;
671 } s;
672 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
673 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
674 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
675 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
676};
677
678union cvmx_agl_gmx_rx_bp_dropx {
679 uint64_t u64;
680 struct cvmx_agl_gmx_rx_bp_dropx_s {
681 uint64_t reserved_6_63:58;
682 uint64_t mark:6;
683 } s;
684 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
685 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
686 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
687 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
688};
689
690union cvmx_agl_gmx_rx_bp_offx {
691 uint64_t u64;
692 struct cvmx_agl_gmx_rx_bp_offx_s {
693 uint64_t reserved_6_63:58;
694 uint64_t mark:6;
695 } s;
696 struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
697 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
698 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
699 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
700};
701
702union cvmx_agl_gmx_rx_bp_onx {
703 uint64_t u64;
704 struct cvmx_agl_gmx_rx_bp_onx_s {
705 uint64_t reserved_9_63:55;
706 uint64_t mark:9;
707 } s;
708 struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
709 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
710 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
711 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
712};
713
714union cvmx_agl_gmx_rx_prt_info {
715 uint64_t u64;
716 struct cvmx_agl_gmx_rx_prt_info_s {
717 uint64_t reserved_18_63:46;
718 uint64_t drop:2;
719 uint64_t reserved_2_15:14;
720 uint64_t commit:2;
721 } s;
722 struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
723 struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
724 struct cvmx_agl_gmx_rx_prt_info_cn56xx {
725 uint64_t reserved_17_63:47;
726 uint64_t drop:1;
727 uint64_t reserved_1_15:15;
728 uint64_t commit:1;
729 } cn56xx;
730 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
731};
732
733union cvmx_agl_gmx_rx_tx_status {
734 uint64_t u64;
735 struct cvmx_agl_gmx_rx_tx_status_s {
736 uint64_t reserved_6_63:58;
737 uint64_t tx:2;
738 uint64_t reserved_2_3:2;
739 uint64_t rx:2;
740 } s;
741 struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
742 struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
743 struct cvmx_agl_gmx_rx_tx_status_cn56xx {
744 uint64_t reserved_5_63:59;
745 uint64_t tx:1;
746 uint64_t reserved_1_3:3;
747 uint64_t rx:1;
748 } cn56xx;
749 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
750};
751
752union cvmx_agl_gmx_smacx {
753 uint64_t u64;
754 struct cvmx_agl_gmx_smacx_s {
755 uint64_t reserved_48_63:16;
756 uint64_t smac:48;
757 } s;
758 struct cvmx_agl_gmx_smacx_s cn52xx;
759 struct cvmx_agl_gmx_smacx_s cn52xxp1;
760 struct cvmx_agl_gmx_smacx_s cn56xx;
761 struct cvmx_agl_gmx_smacx_s cn56xxp1;
762};
763
764union cvmx_agl_gmx_stat_bp {
765 uint64_t u64;
766 struct cvmx_agl_gmx_stat_bp_s {
767 uint64_t reserved_17_63:47;
768 uint64_t bp:1;
769 uint64_t cnt:16;
770 } s;
771 struct cvmx_agl_gmx_stat_bp_s cn52xx;
772 struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
773 struct cvmx_agl_gmx_stat_bp_s cn56xx;
774 struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
775};
776
777union cvmx_agl_gmx_txx_append {
778 uint64_t u64;
779 struct cvmx_agl_gmx_txx_append_s {
780 uint64_t reserved_4_63:60;
781 uint64_t force_fcs:1;
782 uint64_t fcs:1;
783 uint64_t pad:1;
784 uint64_t preamble:1;
785 } s;
786 struct cvmx_agl_gmx_txx_append_s cn52xx;
787 struct cvmx_agl_gmx_txx_append_s cn52xxp1;
788 struct cvmx_agl_gmx_txx_append_s cn56xx;
789 struct cvmx_agl_gmx_txx_append_s cn56xxp1;
790};
791
792union cvmx_agl_gmx_txx_ctl {
793 uint64_t u64;
794 struct cvmx_agl_gmx_txx_ctl_s {
795 uint64_t reserved_2_63:62;
796 uint64_t xsdef_en:1;
797 uint64_t xscol_en:1;
798 } s;
799 struct cvmx_agl_gmx_txx_ctl_s cn52xx;
800 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
801 struct cvmx_agl_gmx_txx_ctl_s cn56xx;
802 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
803};
804
805union cvmx_agl_gmx_txx_min_pkt {
806 uint64_t u64;
807 struct cvmx_agl_gmx_txx_min_pkt_s {
808 uint64_t reserved_8_63:56;
809 uint64_t min_size:8;
810 } s;
811 struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
812 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
813 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
814 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
815};
816
817union cvmx_agl_gmx_txx_pause_pkt_interval {
818 uint64_t u64;
819 struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
820 uint64_t reserved_16_63:48;
821 uint64_t interval:16;
822 } s;
823 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
824 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
825 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
826 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
827};
828
829union cvmx_agl_gmx_txx_pause_pkt_time {
830 uint64_t u64;
831 struct cvmx_agl_gmx_txx_pause_pkt_time_s {
832 uint64_t reserved_16_63:48;
833 uint64_t time:16;
834 } s;
835 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
836 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
837 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
838 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
839};
840
841union cvmx_agl_gmx_txx_pause_togo {
842 uint64_t u64;
843 struct cvmx_agl_gmx_txx_pause_togo_s {
844 uint64_t reserved_16_63:48;
845 uint64_t time:16;
846 } s;
847 struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
848 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
849 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
850 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
851};
852
853union cvmx_agl_gmx_txx_pause_zero {
854 uint64_t u64;
855 struct cvmx_agl_gmx_txx_pause_zero_s {
856 uint64_t reserved_1_63:63;
857 uint64_t send:1;
858 } s;
859 struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
860 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
861 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
862 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
863};
864
865union cvmx_agl_gmx_txx_soft_pause {
866 uint64_t u64;
867 struct cvmx_agl_gmx_txx_soft_pause_s {
868 uint64_t reserved_16_63:48;
869 uint64_t time:16;
870 } s;
871 struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
872 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
873 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
874 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
875};
876
877union cvmx_agl_gmx_txx_stat0 {
878 uint64_t u64;
879 struct cvmx_agl_gmx_txx_stat0_s {
880 uint64_t xsdef:32;
881 uint64_t xscol:32;
882 } s;
883 struct cvmx_agl_gmx_txx_stat0_s cn52xx;
884 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
885 struct cvmx_agl_gmx_txx_stat0_s cn56xx;
886 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
887};
888
889union cvmx_agl_gmx_txx_stat1 {
890 uint64_t u64;
891 struct cvmx_agl_gmx_txx_stat1_s {
892 uint64_t scol:32;
893 uint64_t mcol:32;
894 } s;
895 struct cvmx_agl_gmx_txx_stat1_s cn52xx;
896 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
897 struct cvmx_agl_gmx_txx_stat1_s cn56xx;
898 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
899};
900
901union cvmx_agl_gmx_txx_stat2 {
902 uint64_t u64;
903 struct cvmx_agl_gmx_txx_stat2_s {
904 uint64_t reserved_48_63:16;
905 uint64_t octs:48;
906 } s;
907 struct cvmx_agl_gmx_txx_stat2_s cn52xx;
908 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
909 struct cvmx_agl_gmx_txx_stat2_s cn56xx;
910 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
911};
912
913union cvmx_agl_gmx_txx_stat3 {
914 uint64_t u64;
915 struct cvmx_agl_gmx_txx_stat3_s {
916 uint64_t reserved_32_63:32;
917 uint64_t pkts:32;
918 } s;
919 struct cvmx_agl_gmx_txx_stat3_s cn52xx;
920 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
921 struct cvmx_agl_gmx_txx_stat3_s cn56xx;
922 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
923};
924
925union cvmx_agl_gmx_txx_stat4 {
926 uint64_t u64;
927 struct cvmx_agl_gmx_txx_stat4_s {
928 uint64_t hist1:32;
929 uint64_t hist0:32;
930 } s;
931 struct cvmx_agl_gmx_txx_stat4_s cn52xx;
932 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
933 struct cvmx_agl_gmx_txx_stat4_s cn56xx;
934 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
935};
936
937union cvmx_agl_gmx_txx_stat5 {
938 uint64_t u64;
939 struct cvmx_agl_gmx_txx_stat5_s {
940 uint64_t hist3:32;
941 uint64_t hist2:32;
942 } s;
943 struct cvmx_agl_gmx_txx_stat5_s cn52xx;
944 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
945 struct cvmx_agl_gmx_txx_stat5_s cn56xx;
946 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
947};
948
949union cvmx_agl_gmx_txx_stat6 {
950 uint64_t u64;
951 struct cvmx_agl_gmx_txx_stat6_s {
952 uint64_t hist5:32;
953 uint64_t hist4:32;
954 } s;
955 struct cvmx_agl_gmx_txx_stat6_s cn52xx;
956 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
957 struct cvmx_agl_gmx_txx_stat6_s cn56xx;
958 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
959};
960
961union cvmx_agl_gmx_txx_stat7 {
962 uint64_t u64;
963 struct cvmx_agl_gmx_txx_stat7_s {
964 uint64_t hist7:32;
965 uint64_t hist6:32;
966 } s;
967 struct cvmx_agl_gmx_txx_stat7_s cn52xx;
968 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
969 struct cvmx_agl_gmx_txx_stat7_s cn56xx;
970 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
971};
972
973union cvmx_agl_gmx_txx_stat8 {
974 uint64_t u64;
975 struct cvmx_agl_gmx_txx_stat8_s {
976 uint64_t mcst:32;
977 uint64_t bcst:32;
978 } s;
979 struct cvmx_agl_gmx_txx_stat8_s cn52xx;
980 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
981 struct cvmx_agl_gmx_txx_stat8_s cn56xx;
982 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
983};
984
985union cvmx_agl_gmx_txx_stat9 {
986 uint64_t u64;
987 struct cvmx_agl_gmx_txx_stat9_s {
988 uint64_t undflw:32;
989 uint64_t ctl:32;
990 } s;
991 struct cvmx_agl_gmx_txx_stat9_s cn52xx;
992 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
993 struct cvmx_agl_gmx_txx_stat9_s cn56xx;
994 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
995};
996
997union cvmx_agl_gmx_txx_stats_ctl {
998 uint64_t u64;
999 struct cvmx_agl_gmx_txx_stats_ctl_s {
1000 uint64_t reserved_1_63:63;
1001 uint64_t rd_clr:1;
1002 } s;
1003 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
1004 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1005 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1006 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1007};
1008
1009union cvmx_agl_gmx_txx_thresh {
1010 uint64_t u64;
1011 struct cvmx_agl_gmx_txx_thresh_s {
1012 uint64_t reserved_6_63:58;
1013 uint64_t cnt:6;
1014 } s;
1015 struct cvmx_agl_gmx_txx_thresh_s cn52xx;
1016 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1017 struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1018 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1019};
1020
1021union cvmx_agl_gmx_tx_bp {
1022 uint64_t u64;
1023 struct cvmx_agl_gmx_tx_bp_s {
1024 uint64_t reserved_2_63:62;
1025 uint64_t bp:2;
1026 } s;
1027 struct cvmx_agl_gmx_tx_bp_s cn52xx;
1028 struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
1029 struct cvmx_agl_gmx_tx_bp_cn56xx {
1030 uint64_t reserved_1_63:63;
1031 uint64_t bp:1;
1032 } cn56xx;
1033 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
1034};
1035
1036union cvmx_agl_gmx_tx_col_attempt {
1037 uint64_t u64;
1038 struct cvmx_agl_gmx_tx_col_attempt_s {
1039 uint64_t reserved_5_63:59;
1040 uint64_t limit:5;
1041 } s;
1042 struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
1043 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
1044 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
1045 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
1046};
1047
1048union cvmx_agl_gmx_tx_ifg {
1049 uint64_t u64;
1050 struct cvmx_agl_gmx_tx_ifg_s {
1051 uint64_t reserved_8_63:56;
1052 uint64_t ifg2:4;
1053 uint64_t ifg1:4;
1054 } s;
1055 struct cvmx_agl_gmx_tx_ifg_s cn52xx;
1056 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
1057 struct cvmx_agl_gmx_tx_ifg_s cn56xx;
1058 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
1059};
1060
1061union cvmx_agl_gmx_tx_int_en {
1062 uint64_t u64;
1063 struct cvmx_agl_gmx_tx_int_en_s {
1064 uint64_t reserved_18_63:46;
1065 uint64_t late_col:2;
1066 uint64_t reserved_14_15:2;
1067 uint64_t xsdef:2;
1068 uint64_t reserved_10_11:2;
1069 uint64_t xscol:2;
1070 uint64_t reserved_4_7:4;
1071 uint64_t undflw:2;
1072 uint64_t reserved_1_1:1;
1073 uint64_t pko_nxa:1;
1074 } s;
1075 struct cvmx_agl_gmx_tx_int_en_s cn52xx;
1076 struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
1077 struct cvmx_agl_gmx_tx_int_en_cn56xx {
1078 uint64_t reserved_17_63:47;
1079 uint64_t late_col:1;
1080 uint64_t reserved_13_15:3;
1081 uint64_t xsdef:1;
1082 uint64_t reserved_9_11:3;
1083 uint64_t xscol:1;
1084 uint64_t reserved_3_7:5;
1085 uint64_t undflw:1;
1086 uint64_t reserved_1_1:1;
1087 uint64_t pko_nxa:1;
1088 } cn56xx;
1089 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
1090};
1091
1092union cvmx_agl_gmx_tx_int_reg {
1093 uint64_t u64;
1094 struct cvmx_agl_gmx_tx_int_reg_s {
1095 uint64_t reserved_18_63:46;
1096 uint64_t late_col:2;
1097 uint64_t reserved_14_15:2;
1098 uint64_t xsdef:2;
1099 uint64_t reserved_10_11:2;
1100 uint64_t xscol:2;
1101 uint64_t reserved_4_7:4;
1102 uint64_t undflw:2;
1103 uint64_t reserved_1_1:1;
1104 uint64_t pko_nxa:1;
1105 } s;
1106 struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
1107 struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
1108 struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1109 uint64_t reserved_17_63:47;
1110 uint64_t late_col:1;
1111 uint64_t reserved_13_15:3;
1112 uint64_t xsdef:1;
1113 uint64_t reserved_9_11:3;
1114 uint64_t xscol:1;
1115 uint64_t reserved_3_7:5;
1116 uint64_t undflw:1;
1117 uint64_t reserved_1_1:1;
1118 uint64_t pko_nxa:1;
1119 } cn56xx;
1120 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
1121};
1122
1123union cvmx_agl_gmx_tx_jam {
1124 uint64_t u64;
1125 struct cvmx_agl_gmx_tx_jam_s {
1126 uint64_t reserved_8_63:56;
1127 uint64_t jam:8;
1128 } s;
1129 struct cvmx_agl_gmx_tx_jam_s cn52xx;
1130 struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
1131 struct cvmx_agl_gmx_tx_jam_s cn56xx;
1132 struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
1133};
1134
1135union cvmx_agl_gmx_tx_lfsr {
1136 uint64_t u64;
1137 struct cvmx_agl_gmx_tx_lfsr_s {
1138 uint64_t reserved_16_63:48;
1139 uint64_t lfsr:16;
1140 } s;
1141 struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
1142 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
1143 struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
1144 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
1145};
1146
1147union cvmx_agl_gmx_tx_ovr_bp {
1148 uint64_t u64;
1149 struct cvmx_agl_gmx_tx_ovr_bp_s {
1150 uint64_t reserved_10_63:54;
1151 uint64_t en:2;
1152 uint64_t reserved_6_7:2;
1153 uint64_t bp:2;
1154 uint64_t reserved_2_3:2;
1155 uint64_t ign_full:2;
1156 } s;
1157 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
1158 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
1159 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1160 uint64_t reserved_9_63:55;
1161 uint64_t en:1;
1162 uint64_t reserved_5_7:3;
1163 uint64_t bp:1;
1164 uint64_t reserved_1_3:3;
1165 uint64_t ign_full:1;
1166 } cn56xx;
1167 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
1168};
1169
1170union cvmx_agl_gmx_tx_pause_pkt_dmac {
1171 uint64_t u64;
1172 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1173 uint64_t reserved_48_63:16;
1174 uint64_t dmac:48;
1175 } s;
1176 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
1177 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
1178 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
1179 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
1180};
1181
1182union cvmx_agl_gmx_tx_pause_pkt_type {
1183 uint64_t u64;
1184 struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1185 uint64_t reserved_16_63:48;
1186 uint64_t type:16;
1187 } s;
1188 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
1189 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
1190 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
1191 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
1192};
1193
1194#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
new file mode 100644
index 000000000000..dab6dca492f9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -0,0 +1,248 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIXX_DEFS_H__
29#define __CVMX_MIXX_DEFS_H__
30
31#define CVMX_MIXX_BIST(offset) \
32 CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
33#define CVMX_MIXX_CTL(offset) \
34 CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
35#define CVMX_MIXX_INTENA(offset) \
36 CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
37#define CVMX_MIXX_IRCNT(offset) \
38 CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
39#define CVMX_MIXX_IRHWM(offset) \
40 CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
41#define CVMX_MIXX_IRING1(offset) \
42 CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
43#define CVMX_MIXX_IRING2(offset) \
44 CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
45#define CVMX_MIXX_ISR(offset) \
46 CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
47#define CVMX_MIXX_ORCNT(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
49#define CVMX_MIXX_ORHWM(offset) \
50 CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
51#define CVMX_MIXX_ORING1(offset) \
52 CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
53#define CVMX_MIXX_ORING2(offset) \
54 CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
55#define CVMX_MIXX_REMCNT(offset) \
56 CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
57
58union cvmx_mixx_bist {
59 uint64_t u64;
60 struct cvmx_mixx_bist_s {
61 uint64_t reserved_4_63:60;
62 uint64_t mrqdat:1;
63 uint64_t ipfdat:1;
64 uint64_t irfdat:1;
65 uint64_t orfdat:1;
66 } s;
67 struct cvmx_mixx_bist_s cn52xx;
68 struct cvmx_mixx_bist_s cn52xxp1;
69 struct cvmx_mixx_bist_s cn56xx;
70 struct cvmx_mixx_bist_s cn56xxp1;
71};
72
73union cvmx_mixx_ctl {
74 uint64_t u64;
75 struct cvmx_mixx_ctl_s {
76 uint64_t reserved_8_63:56;
77 uint64_t crc_strip:1;
78 uint64_t busy:1;
79 uint64_t en:1;
80 uint64_t reset:1;
81 uint64_t lendian:1;
82 uint64_t nbtarb:1;
83 uint64_t mrq_hwm:2;
84 } s;
85 struct cvmx_mixx_ctl_s cn52xx;
86 struct cvmx_mixx_ctl_s cn52xxp1;
87 struct cvmx_mixx_ctl_s cn56xx;
88 struct cvmx_mixx_ctl_s cn56xxp1;
89};
90
91union cvmx_mixx_intena {
92 uint64_t u64;
93 struct cvmx_mixx_intena_s {
94 uint64_t reserved_7_63:57;
95 uint64_t orunena:1;
96 uint64_t irunena:1;
97 uint64_t data_drpena:1;
98 uint64_t ithena:1;
99 uint64_t othena:1;
100 uint64_t ivfena:1;
101 uint64_t ovfena:1;
102 } s;
103 struct cvmx_mixx_intena_s cn52xx;
104 struct cvmx_mixx_intena_s cn52xxp1;
105 struct cvmx_mixx_intena_s cn56xx;
106 struct cvmx_mixx_intena_s cn56xxp1;
107};
108
109union cvmx_mixx_ircnt {
110 uint64_t u64;
111 struct cvmx_mixx_ircnt_s {
112 uint64_t reserved_20_63:44;
113 uint64_t ircnt:20;
114 } s;
115 struct cvmx_mixx_ircnt_s cn52xx;
116 struct cvmx_mixx_ircnt_s cn52xxp1;
117 struct cvmx_mixx_ircnt_s cn56xx;
118 struct cvmx_mixx_ircnt_s cn56xxp1;
119};
120
121union cvmx_mixx_irhwm {
122 uint64_t u64;
123 struct cvmx_mixx_irhwm_s {
124 uint64_t reserved_40_63:24;
125 uint64_t ibplwm:20;
126 uint64_t irhwm:20;
127 } s;
128 struct cvmx_mixx_irhwm_s cn52xx;
129 struct cvmx_mixx_irhwm_s cn52xxp1;
130 struct cvmx_mixx_irhwm_s cn56xx;
131 struct cvmx_mixx_irhwm_s cn56xxp1;
132};
133
134union cvmx_mixx_iring1 {
135 uint64_t u64;
136 struct cvmx_mixx_iring1_s {
137 uint64_t reserved_60_63:4;
138 uint64_t isize:20;
139 uint64_t reserved_36_39:4;
140 uint64_t ibase:33;
141 uint64_t reserved_0_2:3;
142 } s;
143 struct cvmx_mixx_iring1_s cn52xx;
144 struct cvmx_mixx_iring1_s cn52xxp1;
145 struct cvmx_mixx_iring1_s cn56xx;
146 struct cvmx_mixx_iring1_s cn56xxp1;
147};
148
149union cvmx_mixx_iring2 {
150 uint64_t u64;
151 struct cvmx_mixx_iring2_s {
152 uint64_t reserved_52_63:12;
153 uint64_t itlptr:20;
154 uint64_t reserved_20_31:12;
155 uint64_t idbell:20;
156 } s;
157 struct cvmx_mixx_iring2_s cn52xx;
158 struct cvmx_mixx_iring2_s cn52xxp1;
159 struct cvmx_mixx_iring2_s cn56xx;
160 struct cvmx_mixx_iring2_s cn56xxp1;
161};
162
163union cvmx_mixx_isr {
164 uint64_t u64;
165 struct cvmx_mixx_isr_s {
166 uint64_t reserved_7_63:57;
167 uint64_t orun:1;
168 uint64_t irun:1;
169 uint64_t data_drp:1;
170 uint64_t irthresh:1;
171 uint64_t orthresh:1;
172 uint64_t idblovf:1;
173 uint64_t odblovf:1;
174 } s;
175 struct cvmx_mixx_isr_s cn52xx;
176 struct cvmx_mixx_isr_s cn52xxp1;
177 struct cvmx_mixx_isr_s cn56xx;
178 struct cvmx_mixx_isr_s cn56xxp1;
179};
180
181union cvmx_mixx_orcnt {
182 uint64_t u64;
183 struct cvmx_mixx_orcnt_s {
184 uint64_t reserved_20_63:44;
185 uint64_t orcnt:20;
186 } s;
187 struct cvmx_mixx_orcnt_s cn52xx;
188 struct cvmx_mixx_orcnt_s cn52xxp1;
189 struct cvmx_mixx_orcnt_s cn56xx;
190 struct cvmx_mixx_orcnt_s cn56xxp1;
191};
192
193union cvmx_mixx_orhwm {
194 uint64_t u64;
195 struct cvmx_mixx_orhwm_s {
196 uint64_t reserved_20_63:44;
197 uint64_t orhwm:20;
198 } s;
199 struct cvmx_mixx_orhwm_s cn52xx;
200 struct cvmx_mixx_orhwm_s cn52xxp1;
201 struct cvmx_mixx_orhwm_s cn56xx;
202 struct cvmx_mixx_orhwm_s cn56xxp1;
203};
204
205union cvmx_mixx_oring1 {
206 uint64_t u64;
207 struct cvmx_mixx_oring1_s {
208 uint64_t reserved_60_63:4;
209 uint64_t osize:20;
210 uint64_t reserved_36_39:4;
211 uint64_t obase:33;
212 uint64_t reserved_0_2:3;
213 } s;
214 struct cvmx_mixx_oring1_s cn52xx;
215 struct cvmx_mixx_oring1_s cn52xxp1;
216 struct cvmx_mixx_oring1_s cn56xx;
217 struct cvmx_mixx_oring1_s cn56xxp1;
218};
219
220union cvmx_mixx_oring2 {
221 uint64_t u64;
222 struct cvmx_mixx_oring2_s {
223 uint64_t reserved_52_63:12;
224 uint64_t otlptr:20;
225 uint64_t reserved_20_31:12;
226 uint64_t odbell:20;
227 } s;
228 struct cvmx_mixx_oring2_s cn52xx;
229 struct cvmx_mixx_oring2_s cn52xxp1;
230 struct cvmx_mixx_oring2_s cn56xx;
231 struct cvmx_mixx_oring2_s cn56xxp1;
232};
233
234union cvmx_mixx_remcnt {
235 uint64_t u64;
236 struct cvmx_mixx_remcnt_s {
237 uint64_t reserved_52_63:12;
238 uint64_t iremcnt:20;
239 uint64_t reserved_20_31:12;
240 uint64_t oremcnt:20;
241 } s;
242 struct cvmx_mixx_remcnt_s cn52xx;
243 struct cvmx_mixx_remcnt_s cn52xxp1;
244 struct cvmx_mixx_remcnt_s cn56xx;
245 struct cvmx_mixx_remcnt_s cn56xxp1;
246};
247
248#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
new file mode 100644
index 000000000000..9ae45fcbe3e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -0,0 +1,178 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SMIX_DEFS_H__
29#define __CVMX_SMIX_DEFS_H__
30
31#define CVMX_SMIX_CLK(offset) \
32 CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
33#define CVMX_SMIX_CMD(offset) \
34 CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
35#define CVMX_SMIX_EN(offset) \
36 CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
37#define CVMX_SMIX_RD_DAT(offset) \
38 CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
39#define CVMX_SMIX_WR_DAT(offset) \
40 CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
41
42union cvmx_smix_clk {
43 uint64_t u64;
44 struct cvmx_smix_clk_s {
45 uint64_t reserved_25_63:39;
46 uint64_t mode:1;
47 uint64_t reserved_21_23:3;
48 uint64_t sample_hi:5;
49 uint64_t sample_mode:1;
50 uint64_t reserved_14_14:1;
51 uint64_t clk_idle:1;
52 uint64_t preamble:1;
53 uint64_t sample:4;
54 uint64_t phase:8;
55 } s;
56 struct cvmx_smix_clk_cn30xx {
57 uint64_t reserved_21_63:43;
58 uint64_t sample_hi:5;
59 uint64_t reserved_14_15:2;
60 uint64_t clk_idle:1;
61 uint64_t preamble:1;
62 uint64_t sample:4;
63 uint64_t phase:8;
64 } cn30xx;
65 struct cvmx_smix_clk_cn30xx cn31xx;
66 struct cvmx_smix_clk_cn30xx cn38xx;
67 struct cvmx_smix_clk_cn30xx cn38xxp2;
68 struct cvmx_smix_clk_cn50xx {
69 uint64_t reserved_25_63:39;
70 uint64_t mode:1;
71 uint64_t reserved_21_23:3;
72 uint64_t sample_hi:5;
73 uint64_t reserved_14_15:2;
74 uint64_t clk_idle:1;
75 uint64_t preamble:1;
76 uint64_t sample:4;
77 uint64_t phase:8;
78 } cn50xx;
79 struct cvmx_smix_clk_s cn52xx;
80 struct cvmx_smix_clk_cn50xx cn52xxp1;
81 struct cvmx_smix_clk_s cn56xx;
82 struct cvmx_smix_clk_cn50xx cn56xxp1;
83 struct cvmx_smix_clk_cn30xx cn58xx;
84 struct cvmx_smix_clk_cn30xx cn58xxp1;
85};
86
87union cvmx_smix_cmd {
88 uint64_t u64;
89 struct cvmx_smix_cmd_s {
90 uint64_t reserved_18_63:46;
91 uint64_t phy_op:2;
92 uint64_t reserved_13_15:3;
93 uint64_t phy_adr:5;
94 uint64_t reserved_5_7:3;
95 uint64_t reg_adr:5;
96 } s;
97 struct cvmx_smix_cmd_cn30xx {
98 uint64_t reserved_17_63:47;
99 uint64_t phy_op:1;
100 uint64_t reserved_13_15:3;
101 uint64_t phy_adr:5;
102 uint64_t reserved_5_7:3;
103 uint64_t reg_adr:5;
104 } cn30xx;
105 struct cvmx_smix_cmd_cn30xx cn31xx;
106 struct cvmx_smix_cmd_cn30xx cn38xx;
107 struct cvmx_smix_cmd_cn30xx cn38xxp2;
108 struct cvmx_smix_cmd_s cn50xx;
109 struct cvmx_smix_cmd_s cn52xx;
110 struct cvmx_smix_cmd_s cn52xxp1;
111 struct cvmx_smix_cmd_s cn56xx;
112 struct cvmx_smix_cmd_s cn56xxp1;
113 struct cvmx_smix_cmd_cn30xx cn58xx;
114 struct cvmx_smix_cmd_cn30xx cn58xxp1;
115};
116
117union cvmx_smix_en {
118 uint64_t u64;
119 struct cvmx_smix_en_s {
120 uint64_t reserved_1_63:63;
121 uint64_t en:1;
122 } s;
123 struct cvmx_smix_en_s cn30xx;
124 struct cvmx_smix_en_s cn31xx;
125 struct cvmx_smix_en_s cn38xx;
126 struct cvmx_smix_en_s cn38xxp2;
127 struct cvmx_smix_en_s cn50xx;
128 struct cvmx_smix_en_s cn52xx;
129 struct cvmx_smix_en_s cn52xxp1;
130 struct cvmx_smix_en_s cn56xx;
131 struct cvmx_smix_en_s cn56xxp1;
132 struct cvmx_smix_en_s cn58xx;
133 struct cvmx_smix_en_s cn58xxp1;
134};
135
136union cvmx_smix_rd_dat {
137 uint64_t u64;
138 struct cvmx_smix_rd_dat_s {
139 uint64_t reserved_18_63:46;
140 uint64_t pending:1;
141 uint64_t val:1;
142 uint64_t dat:16;
143 } s;
144 struct cvmx_smix_rd_dat_s cn30xx;
145 struct cvmx_smix_rd_dat_s cn31xx;
146 struct cvmx_smix_rd_dat_s cn38xx;
147 struct cvmx_smix_rd_dat_s cn38xxp2;
148 struct cvmx_smix_rd_dat_s cn50xx;
149 struct cvmx_smix_rd_dat_s cn52xx;
150 struct cvmx_smix_rd_dat_s cn52xxp1;
151 struct cvmx_smix_rd_dat_s cn56xx;
152 struct cvmx_smix_rd_dat_s cn56xxp1;
153 struct cvmx_smix_rd_dat_s cn58xx;
154 struct cvmx_smix_rd_dat_s cn58xxp1;
155};
156
157union cvmx_smix_wr_dat {
158 uint64_t u64;
159 struct cvmx_smix_wr_dat_s {
160 uint64_t reserved_18_63:46;
161 uint64_t pending:1;
162 uint64_t val:1;
163 uint64_t dat:16;
164 } s;
165 struct cvmx_smix_wr_dat_s cn30xx;
166 struct cvmx_smix_wr_dat_s cn31xx;
167 struct cvmx_smix_wr_dat_s cn38xx;
168 struct cvmx_smix_wr_dat_s cn38xxp2;
169 struct cvmx_smix_wr_dat_s cn50xx;
170 struct cvmx_smix_wr_dat_s cn52xx;
171 struct cvmx_smix_wr_dat_s cn52xxp1;
172 struct cvmx_smix_wr_dat_s cn56xx;
173 struct cvmx_smix_wr_dat_s cn56xxp1;
174 struct cvmx_smix_wr_dat_s cn58xx;
175 struct cvmx_smix_wr_dat_s cn58xxp1;
176};
177
178#endif
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index cac9b1a206fc..4d0a8c61fc3e 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -47,6 +47,7 @@ struct octeon_cop2_state;
47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); 47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
48extern void octeon_crypto_disable(struct octeon_cop2_state *state, 48extern void octeon_crypto_disable(struct octeon_cop2_state *state,
49 unsigned long flags); 49 unsigned long flags);
50extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
50 51
51extern void octeon_init_cvmcount(void); 52extern void octeon_init_cvmcount(void);
52 53
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d6eb6134abec..1854336e56a2 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -390,6 +390,19 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
390#include <asm-generic/pgtable.h> 390#include <asm-generic/pgtable.h>
391 391
392/* 392/*
393 * uncached accelerated TLB map for video memory access
394 */
395#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
396#define __HAVE_PHYS_MEM_ACCESS_PROT
397
398struct file;
399pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
400 unsigned long size, pgprot_t vma_prot);
401int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
402 unsigned long size, pgprot_t *vma_prot);
403#endif
404
405/*
393 * We provide our own get_unmapped area to cope with the virtual aliasing 406 * We provide our own get_unmapped area to cope with the virtual aliasing
394 * constraints placed on us by the cache architecture. 407 * constraints placed on us by the cache architecture.
395 */ 408 */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index bfce5c786f1c..63741ca1e422 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -85,8 +85,7 @@ extern void prom_identify_arch(void);
85extern PCHAR ArcGetEnvironmentVariable(PCHAR name); 85extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
86extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); 86extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
87 87
88/* ARCS command line acquisition and parsing. */ 88/* ARCS command line parsing. */
89extern char *prom_getcmdline(void);
90extern void prom_init_cmdline(void); 89extern void prom_init_cmdline(void);
91 90
92/* Acquiring info about the current time, etc. */ 91/* Acquiring info about the current time, etc. */
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index db0fa7b5aeaf..3b6da3330e32 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -51,9 +51,6 @@
51 LONG_S v1, PT_ACX(sp) 51 LONG_S v1, PT_ACX(sp)
52#else 52#else
53 mfhi v1 53 mfhi v1
54 LONG_S v1, PT_HI(sp)
55 mflo v1
56 LONG_S v1, PT_LO(sp)
57#endif 54#endif
58#ifdef CONFIG_32BIT 55#ifdef CONFIG_32BIT
59 LONG_S $8, PT_R8(sp) 56 LONG_S $8, PT_R8(sp)
@@ -62,10 +59,17 @@
62 LONG_S $10, PT_R10(sp) 59 LONG_S $10, PT_R10(sp)
63 LONG_S $11, PT_R11(sp) 60 LONG_S $11, PT_R11(sp)
64 LONG_S $12, PT_R12(sp) 61 LONG_S $12, PT_R12(sp)
62#ifndef CONFIG_CPU_HAS_SMARTMIPS
63 LONG_S v1, PT_HI(sp)
64 mflo v1
65#endif
65 LONG_S $13, PT_R13(sp) 66 LONG_S $13, PT_R13(sp)
66 LONG_S $14, PT_R14(sp) 67 LONG_S $14, PT_R14(sp)
67 LONG_S $15, PT_R15(sp) 68 LONG_S $15, PT_R15(sp)
68 LONG_S $24, PT_R24(sp) 69 LONG_S $24, PT_R24(sp)
70#ifndef CONFIG_CPU_HAS_SMARTMIPS
71 LONG_S v1, PT_LO(sp)
72#endif
69 .endm 73 .endm
70 74
71 .macro SAVE_STATIC 75 .macro SAVE_STATIC
@@ -83,15 +87,19 @@
83#ifdef CONFIG_SMP 87#ifdef CONFIG_SMP
84#ifdef CONFIG_MIPS_MT_SMTC 88#ifdef CONFIG_MIPS_MT_SMTC
85#define PTEBASE_SHIFT 19 /* TCBIND */ 89#define PTEBASE_SHIFT 19 /* TCBIND */
90#define CPU_ID_REG CP0_TCBIND
91#define CPU_ID_MFC0 mfc0
92#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
93#define PTEBASE_SHIFT 48 /* XCONTEXT */
94#define CPU_ID_REG CP0_XCONTEXT
95#define CPU_ID_MFC0 MFC0
86#else 96#else
87#define PTEBASE_SHIFT 23 /* CONTEXT */ 97#define PTEBASE_SHIFT 23 /* CONTEXT */
98#define CPU_ID_REG CP0_CONTEXT
99#define CPU_ID_MFC0 MFC0
88#endif 100#endif
89 .macro get_saved_sp /* SMP variation */ 101 .macro get_saved_sp /* SMP variation */
90#ifdef CONFIG_MIPS_MT_SMTC 102 CPU_ID_MFC0 k0, CPU_ID_REG
91 mfc0 k0, CP0_TCBIND
92#else
93 MFC0 k0, CP0_CONTEXT
94#endif
95#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 103#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
96 lui k1, %hi(kernelsp) 104 lui k1, %hi(kernelsp)
97#else 105#else
@@ -107,11 +115,7 @@
107 .endm 115 .endm
108 116
109 .macro set_saved_sp stackp temp temp2 117 .macro set_saved_sp stackp temp temp2
110#ifdef CONFIG_MIPS_MT_SMTC 118 CPU_ID_MFC0 \temp, CPU_ID_REG
111 mfc0 \temp, CP0_TCBIND
112#else
113 MFC0 \temp, CP0_CONTEXT
114#endif
115 LONG_SRL \temp, PTEBASE_SHIFT 119 LONG_SRL \temp, PTEBASE_SHIFT
116 LONG_S \stackp, kernelsp(\temp) 120 LONG_S \stackp, kernelsp(\temp)
117 .endm 121 .endm
@@ -166,7 +170,6 @@
166 LONG_S $0, PT_R0(sp) 170 LONG_S $0, PT_R0(sp)
167 mfc0 v1, CP0_STATUS 171 mfc0 v1, CP0_STATUS
168 LONG_S $2, PT_R2(sp) 172 LONG_S $2, PT_R2(sp)
169 LONG_S v1, PT_STATUS(sp)
170#ifdef CONFIG_MIPS_MT_SMTC 173#ifdef CONFIG_MIPS_MT_SMTC
171 /* 174 /*
172 * Ideally, these instructions would be shuffled in 175 * Ideally, these instructions would be shuffled in
@@ -178,20 +181,21 @@
178 LONG_S v1, PT_TCSTATUS(sp) 181 LONG_S v1, PT_TCSTATUS(sp)
179#endif /* CONFIG_MIPS_MT_SMTC */ 182#endif /* CONFIG_MIPS_MT_SMTC */
180 LONG_S $4, PT_R4(sp) 183 LONG_S $4, PT_R4(sp)
181 mfc0 v1, CP0_CAUSE
182 LONG_S $5, PT_R5(sp) 184 LONG_S $5, PT_R5(sp)
183 LONG_S v1, PT_CAUSE(sp) 185 LONG_S v1, PT_STATUS(sp)
186 mfc0 v1, CP0_CAUSE
184 LONG_S $6, PT_R6(sp) 187 LONG_S $6, PT_R6(sp)
185 MFC0 v1, CP0_EPC
186 LONG_S $7, PT_R7(sp) 188 LONG_S $7, PT_R7(sp)
189 LONG_S v1, PT_CAUSE(sp)
190 MFC0 v1, CP0_EPC
187#ifdef CONFIG_64BIT 191#ifdef CONFIG_64BIT
188 LONG_S $8, PT_R8(sp) 192 LONG_S $8, PT_R8(sp)
189 LONG_S $9, PT_R9(sp) 193 LONG_S $9, PT_R9(sp)
190#endif 194#endif
191 LONG_S v1, PT_EPC(sp)
192 LONG_S $25, PT_R25(sp) 195 LONG_S $25, PT_R25(sp)
193 LONG_S $28, PT_R28(sp) 196 LONG_S $28, PT_R28(sp)
194 LONG_S $31, PT_R31(sp) 197 LONG_S $31, PT_R31(sp)
198 LONG_S v1, PT_EPC(sp)
195 ori $28, sp, _THREAD_MASK 199 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK 200 xori $28, _THREAD_MASK
197#ifdef CONFIG_CPU_CAVIUM_OCTEON 201#ifdef CONFIG_CPU_CAVIUM_OCTEON
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-11 00:26:20 -0400