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-rw-r--r--arch/mips/include/asm/abi.h6
-rw-r--r--arch/mips/include/asm/asm-offsets.h1
-rw-r--r--arch/mips/include/asm/atomic.h16
-rw-r--r--arch/mips/include/asm/barrier.h60
-rw-r--r--arch/mips/include/asm/bitops.h8
-rw-r--r--arch/mips/include/asm/bootinfo.h8
-rw-r--r--arch/mips/include/asm/bug.h4
-rw-r--r--arch/mips/include/asm/cacheflush.h1
-rw-r--r--arch/mips/include/asm/clock.h64
-rw-r--r--arch/mips/include/asm/cmpxchg.h12
-rw-r--r--arch/mips/include/asm/compat.h3
-rw-r--r--arch/mips/include/asm/cop2.h23
-rw-r--r--arch/mips/include/asm/cpu-features.h10
-rw-r--r--arch/mips/include/asm/cpu-info.h3
-rw-r--r--arch/mips/include/asm/cpu.h4
-rw-r--r--arch/mips/include/asm/current.h24
-rw-r--r--arch/mips/include/asm/dec/kn01.h1
-rw-r--r--arch/mips/include/asm/device.h1
-rw-r--r--arch/mips/include/asm/elf.h20
-rw-r--r--arch/mips/include/asm/fcntl.h17
-rw-r--r--arch/mips/include/asm/fpu.h8
-rw-r--r--arch/mips/include/asm/fpu_emulator.h28
-rw-r--r--arch/mips/include/asm/ftrace.h91
-rw-r--r--arch/mips/include/asm/i8259.h6
-rw-r--r--arch/mips/include/asm/io.h18
-rw-r--r--arch/mips/include/asm/irq.h30
-rw-r--r--arch/mips/include/asm/local.h25
-rw-r--r--arch/mips/include/asm/mach-ar7/ar7.h23
-rw-r--r--arch/mips/include/asm/mach-ar7/gpio.h86
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h876
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1100_mmc.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h24
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_eth.h17
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h164
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/ioremap.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/prom.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h15
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h6
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h4
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h238
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h156
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h100
-rw-r--r--arch/mips/include/asm/mach-excite/cpu-feature-overrides.h48
-rw-r--r--arch/mips/include/asm/mach-excite/excite.h154
-rw-r--r--arch/mips/include/asm/mach-excite/excite_fpga.h80
-rw-r--r--arch/mips/include/asm/mach-excite/excite_nandflash.h7
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_eth.h23
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_wdt.h12
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_xicap.h16
-rw-r--r--arch/mips/include/asm/mach-ip27/topology.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536.h305
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h35
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h153
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h31
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h295
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h13
-rw-r--r--arch/mips/include/asm/mach-loongson/mem.h29
-rw-r--r--arch/mips/include/asm/mach-loongson/pci.h45
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1100.h85
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h122
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1500.h49
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h96
-rw-r--r--arch/mips/include/asm/mach-pnx833x/gpio.h2
-rw-r--r--arch/mips/include/asm/mach-pnx833x/irq-mapping.h1
-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h107
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_reg_map.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h122
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h119
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h253
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/irq.h25
-rw-r--r--arch/mips/include/asm/mach-powertv/powertv-clock.h29
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h (renamed from arch/mips/include/asm/mach-excite/war.h)19
-rw-r--r--arch/mips/include/asm/mach-sibyte/war.h6
-rw-r--r--arch/mips/include/asm/mips-boards/bonito64.h5
-rw-r--r--arch/mips/include/asm/mipsregs.h36
-rw-r--r--arch/mips/include/asm/mmu.h5
-rw-r--r--arch/mips/include/asm/mmu_context.h31
-rw-r--r--arch/mips/include/asm/msc01_ic.h1
-rw-r--r--arch/mips/include/asm/nile4.h1
-rw-r--r--arch/mips/include/asm/octeon/cvmx-agl-defs.h1194
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mixx-defs.h248
-rw-r--r--arch/mips/include/asm/octeon/cvmx-smix-defs.h178
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h8
-rw-r--r--arch/mips/include/asm/octeon/octeon.h6
-rw-r--r--arch/mips/include/asm/page.h18
-rw-r--r--arch/mips/include/asm/param.h17
-rw-r--r--arch/mips/include/asm/parport.h16
-rw-r--r--arch/mips/include/asm/pci.h22
-rw-r--r--arch/mips/include/asm/pgalloc.h4
-rw-r--r--arch/mips/include/asm/pgtable-32.h4
-rw-r--r--arch/mips/include/asm/pgtable-64.h53
-rw-r--r--arch/mips/include/asm/pgtable-bits.h120
-rw-r--r--arch/mips/include/asm/pgtable.h44
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h1
-rw-r--r--arch/mips/include/asm/processor.h11
-rw-r--r--arch/mips/include/asm/ptrace.h4
-rw-r--r--arch/mips/include/asm/serial.h23
-rw-r--r--arch/mips/include/asm/sgi/ioc.h2
-rw-r--r--arch/mips/include/asm/sgialib.h48
-rw-r--r--arch/mips/include/asm/sibyte/bigsur.h1
-rw-r--r--arch/mips/include/asm/sibyte/sb1250_ldt.h1
-rw-r--r--arch/mips/include/asm/sibyte/sb1250_mac.h2
-rw-r--r--arch/mips/include/asm/sn/klkernvars.h1
-rw-r--r--arch/mips/include/asm/sn/sn0/hubio.h2
-rw-r--r--arch/mips/include/asm/socket.h2
-rw-r--r--arch/mips/include/asm/sparsemem.h1
-rw-r--r--arch/mips/include/asm/spinlock.h194
-rw-r--r--arch/mips/include/asm/spinlock_types.h30
-rw-r--r--arch/mips/include/asm/stackframe.h59
-rw-r--r--arch/mips/include/asm/system.h4
-rw-r--r--arch/mips/include/asm/time.h14
-rw-r--r--arch/mips/include/asm/txx9/generic.h1
-rw-r--r--arch/mips/include/asm/uasm.h215
-rw-r--r--arch/mips/include/asm/ucontext.h22
-rw-r--r--arch/mips/include/asm/unistd.h17
-rw-r--r--arch/mips/include/asm/vdso.h29
124 files changed, 5155 insertions, 2227 deletions
diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h
index 1dd74fbdc09b..9252d9b50e59 100644
--- a/arch/mips/include/asm/abi.h
+++ b/arch/mips/include/asm/abi.h
@@ -13,12 +13,14 @@
13#include <asm/siginfo.h> 13#include <asm/siginfo.h>
14 14
15struct mips_abi { 15struct mips_abi {
16 int (* const setup_frame)(struct k_sigaction * ka, 16 int (* const setup_frame)(void *sig_return, struct k_sigaction *ka,
17 struct pt_regs *regs, int signr, 17 struct pt_regs *regs, int signr,
18 sigset_t *set); 18 sigset_t *set);
19 int (* const setup_rt_frame)(struct k_sigaction * ka, 19 const unsigned long signal_return_offset;
20 int (* const setup_rt_frame)(void *sig_return, struct k_sigaction *ka,
20 struct pt_regs *regs, int signr, 21 struct pt_regs *regs, int signr,
21 sigset_t *set, siginfo_t *info); 22 sigset_t *set, siginfo_t *info);
23 const unsigned long rt_signal_return_offset;
22 const unsigned long restart; 24 const unsigned long restart;
23}; 25};
24 26
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/mips/include/asm/asm-offsets.h
@@ -0,0 +1 @@
#include <generated/asm-offsets.h>
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index dd75d673447e..519197ede089 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -137,7 +137,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
137{ 137{
138 int result; 138 int result;
139 139
140 smp_llsc_mb(); 140 smp_mb__before_llsc();
141 141
142 if (kernel_uses_llsc && R10000_LLSC_WAR) { 142 if (kernel_uses_llsc && R10000_LLSC_WAR) {
143 int temp; 143 int temp;
@@ -189,7 +189,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
189{ 189{
190 int result; 190 int result;
191 191
192 smp_llsc_mb(); 192 smp_mb__before_llsc();
193 193
194 if (kernel_uses_llsc && R10000_LLSC_WAR) { 194 if (kernel_uses_llsc && R10000_LLSC_WAR) {
195 int temp; 195 int temp;
@@ -249,7 +249,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
249{ 249{
250 int result; 250 int result;
251 251
252 smp_llsc_mb(); 252 smp_mb__before_llsc();
253 253
254 if (kernel_uses_llsc && R10000_LLSC_WAR) { 254 if (kernel_uses_llsc && R10000_LLSC_WAR) {
255 int temp; 255 int temp;
@@ -516,7 +516,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
516{ 516{
517 long result; 517 long result;
518 518
519 smp_llsc_mb(); 519 smp_mb__before_llsc();
520 520
521 if (kernel_uses_llsc && R10000_LLSC_WAR) { 521 if (kernel_uses_llsc && R10000_LLSC_WAR) {
522 long temp; 522 long temp;
@@ -568,7 +568,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
568{ 568{
569 long result; 569 long result;
570 570
571 smp_llsc_mb(); 571 smp_mb__before_llsc();
572 572
573 if (kernel_uses_llsc && R10000_LLSC_WAR) { 573 if (kernel_uses_llsc && R10000_LLSC_WAR) {
574 long temp; 574 long temp;
@@ -628,7 +628,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
628{ 628{
629 long result; 629 long result;
630 630
631 smp_llsc_mb(); 631 smp_mb__before_llsc();
632 632
633 if (kernel_uses_llsc && R10000_LLSC_WAR) { 633 if (kernel_uses_llsc && R10000_LLSC_WAR) {
634 long temp; 634 long temp;
@@ -788,9 +788,9 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
788 * atomic*_return operations are serializing but not the non-*_return 788 * atomic*_return operations are serializing but not the non-*_return
789 * versions. 789 * versions.
790 */ 790 */
791#define smp_mb__before_atomic_dec() smp_llsc_mb() 791#define smp_mb__before_atomic_dec() smp_mb__before_llsc()
792#define smp_mb__after_atomic_dec() smp_llsc_mb() 792#define smp_mb__after_atomic_dec() smp_llsc_mb()
793#define smp_mb__before_atomic_inc() smp_llsc_mb() 793#define smp_mb__before_atomic_inc() smp_mb__before_llsc()
794#define smp_mb__after_atomic_inc() smp_llsc_mb() 794#define smp_mb__after_atomic_inc() smp_llsc_mb()
795 795
796#include <asm-generic/atomic-long.h> 796#include <asm-generic/atomic-long.h>
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index 8e9ac313ca3b..c0884f02d3a6 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -88,12 +88,20 @@
88 : /* no output */ \ 88 : /* no output */ \
89 : "m" (*(int *)CKSEG1) \ 89 : "m" (*(int *)CKSEG1) \
90 : "memory") 90 : "memory")
91 91#ifdef CONFIG_CPU_CAVIUM_OCTEON
92#define fast_wmb() __sync() 92# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
93#define fast_rmb() __sync() 93# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
94#define fast_mb() __sync() 94
95#ifdef CONFIG_SGI_IP28 95# define fast_wmb() __syncw()
96#define fast_iob() \ 96# define fast_rmb() barrier()
97# define fast_mb() __sync()
98# define fast_iob() do { } while (0)
99#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
100# define fast_wmb() __sync()
101# define fast_rmb() __sync()
102# define fast_mb() __sync()
103# ifdef CONFIG_SGI_IP28
104# define fast_iob() \
97 __asm__ __volatile__( \ 105 __asm__ __volatile__( \
98 ".set push\n\t" \ 106 ".set push\n\t" \
99 ".set noreorder\n\t" \ 107 ".set noreorder\n\t" \
@@ -104,13 +112,14 @@
104 : /* no output */ \ 112 : /* no output */ \
105 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \ 113 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
106 : "memory") 114 : "memory")
107#else 115# else
108#define fast_iob() \ 116# define fast_iob() \
109 do { \ 117 do { \
110 __sync(); \ 118 __sync(); \
111 __fast_iob(); \ 119 __fast_iob(); \
112 } while (0) 120 } while (0)
113#endif 121# endif
122#endif /* CONFIG_CPU_CAVIUM_OCTEON */
114 123
115#ifdef CONFIG_CPU_HAS_WB 124#ifdef CONFIG_CPU_HAS_WB
116 125
@@ -131,25 +140,42 @@
131#endif /* !CONFIG_CPU_HAS_WB */ 140#endif /* !CONFIG_CPU_HAS_WB */
132 141
133#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP) 142#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
134#define __WEAK_ORDERING_MB " sync \n" 143# ifdef CONFIG_CPU_CAVIUM_OCTEON
144# define smp_mb() __sync()
145# define smp_rmb() barrier()
146# define smp_wmb() __syncw()
147# else
148# define smp_mb() __asm__ __volatile__("sync" : : :"memory")
149# define smp_rmb() __asm__ __volatile__("sync" : : :"memory")
150# define smp_wmb() __asm__ __volatile__("sync" : : :"memory")
151# endif
135#else 152#else
136#define __WEAK_ORDERING_MB " \n" 153#define smp_mb() barrier()
154#define smp_rmb() barrier()
155#define smp_wmb() barrier()
137#endif 156#endif
157
138#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) 158#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
139#define __WEAK_LLSC_MB " sync \n" 159#define __WEAK_LLSC_MB " sync \n"
140#else 160#else
141#define __WEAK_LLSC_MB " \n" 161#define __WEAK_LLSC_MB " \n"
142#endif 162#endif
143 163
144#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
145#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
146#define smp_wmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
147
148#define set_mb(var, value) \ 164#define set_mb(var, value) \
149 do { var = value; smp_mb(); } while (0) 165 do { var = value; smp_mb(); } while (0)
150 166
151#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") 167#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
152#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") 168
153#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") 169#ifdef CONFIG_CPU_CAVIUM_OCTEON
170#define smp_mb__before_llsc() smp_wmb()
171/* Cause previous writes to become visible on all CPUs as soon as possible */
172#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
173 ".set arch=octeon\n\t" \
174 "syncw\n\t" \
175 ".set pop" : : : "memory")
176#else
177#define smp_mb__before_llsc() smp_llsc_mb()
178#define nudge_writes() mb()
179#endif
154 180
155#endif /* __ASM_BARRIER_H */ 181#endif /* __ASM_BARRIER_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 84a383806b2c..9255cfbee459 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -42,7 +42,7 @@
42/* 42/*
43 * clear_bit() doesn't provide any barrier for the compiler. 43 * clear_bit() doesn't provide any barrier for the compiler.
44 */ 44 */
45#define smp_mb__before_clear_bit() smp_llsc_mb() 45#define smp_mb__before_clear_bit() smp_mb__before_llsc()
46#define smp_mb__after_clear_bit() smp_llsc_mb() 46#define smp_mb__after_clear_bit() smp_llsc_mb()
47 47
48/* 48/*
@@ -258,7 +258,7 @@ static inline int test_and_set_bit(unsigned long nr,
258 unsigned short bit = nr & SZLONG_MASK; 258 unsigned short bit = nr & SZLONG_MASK;
259 unsigned long res; 259 unsigned long res;
260 260
261 smp_llsc_mb(); 261 smp_mb__before_llsc();
262 262
263 if (kernel_uses_llsc && R10000_LLSC_WAR) { 263 if (kernel_uses_llsc && R10000_LLSC_WAR) {
264 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 264 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -395,7 +395,7 @@ static inline int test_and_clear_bit(unsigned long nr,
395 unsigned short bit = nr & SZLONG_MASK; 395 unsigned short bit = nr & SZLONG_MASK;
396 unsigned long res; 396 unsigned long res;
397 397
398 smp_llsc_mb(); 398 smp_mb__before_llsc();
399 399
400 if (kernel_uses_llsc && R10000_LLSC_WAR) { 400 if (kernel_uses_llsc && R10000_LLSC_WAR) {
401 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 401 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -485,7 +485,7 @@ static inline int test_and_change_bit(unsigned long nr,
485 unsigned short bit = nr & SZLONG_MASK; 485 unsigned short bit = nr & SZLONG_MASK;
486 unsigned long res; 486 unsigned long res;
487 487
488 smp_llsc_mb(); 488 smp_mb__before_llsc();
489 489
490 if (kernel_uses_llsc && R10000_LLSC_WAR) { 490 if (kernel_uses_llsc && R10000_LLSC_WAR) {
491 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 491 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index f5dfaf6a1606..09eee09780f2 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -67,9 +67,9 @@
67#define MACH_LEMOTE_ML2F7 3 67#define MACH_LEMOTE_ML2F7 3
68#define MACH_LEMOTE_YL2F89 4 68#define MACH_LEMOTE_YL2F89 4
69#define MACH_DEXXON_GDIUM2F10 5 69#define MACH_DEXXON_GDIUM2F10 5
70#define MACH_LOONGSON_END 6 70#define MACH_LEMOTE_NAS 6
71 71#define MACH_LEMOTE_LL2F 7
72#define CL_SIZE COMMAND_LINE_SIZE 72#define MACH_LOONGSON_END 8
73 73
74extern char *system_type; 74extern char *system_type;
75const char *get_system_type(void); 75const char *get_system_type(void);
@@ -107,7 +107,7 @@ extern void free_init_pages(const char *what,
107/* 107/*
108 * Initial kernel command line, usually setup by prom_init() 108 * Initial kernel command line, usually setup by prom_init()
109 */ 109 */
110extern char arcs_cmdline[CL_SIZE]; 110extern char arcs_cmdline[COMMAND_LINE_SIZE];
111 111
112/* 112/*
113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware 113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h
index 6cf29c26e873..540c98a810d1 100644
--- a/arch/mips/include/asm/bug.h
+++ b/arch/mips/include/asm/bug.h
@@ -11,9 +11,7 @@
11static inline void __noreturn BUG(void) 11static inline void __noreturn BUG(void)
12{ 12{
13 __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); 13 __asm__ __volatile__("break %0" : : "i" (BRK_BUG));
14 /* Fool GCC into thinking the function doesn't return. */ 14 unreachable();
15 while (1)
16 ;
17} 15}
18 16
19#define HAVE_ARCH_BUG 17#define HAVE_ARCH_BUG
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 03b1d69b142f..40bb9fde205f 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -38,6 +38,7 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma,
38extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); 38extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
39extern void __flush_dcache_page(struct page *page); 39extern void __flush_dcache_page(struct page *page);
40 40
41#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
41static inline void flush_dcache_page(struct page *page) 42static inline void flush_dcache_page(struct page *page)
42{ 43{
43 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) 44 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
new file mode 100644
index 000000000000..83894aa7932c
--- /dev/null
+++ b/arch/mips/include/asm/clock.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_MIPS_CLOCK_H
2#define __ASM_MIPS_CLOCK_H
3
4#include <linux/kref.h>
5#include <linux/list.h>
6#include <linux/seq_file.h>
7#include <linux/clk.h>
8
9extern void (*cpu_wait) (void);
10
11struct clk;
12
13struct clk_ops {
14 void (*init) (struct clk *clk);
15 void (*enable) (struct clk *clk);
16 void (*disable) (struct clk *clk);
17 void (*recalc) (struct clk *clk);
18 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
19 long (*round_rate) (struct clk *clk, unsigned long rate);
20};
21
22struct clk {
23 struct list_head node;
24 const char *name;
25 int id;
26 struct module *owner;
27
28 struct clk *parent;
29 struct clk_ops *ops;
30
31 struct kref kref;
32
33 unsigned long rate;
34 unsigned long flags;
35};
36
37#define CLK_ALWAYS_ENABLED (1 << 0)
38#define CLK_RATE_PROPAGATES (1 << 1)
39
40/* Should be defined by processor-specific code */
41void arch_init_clk_ops(struct clk_ops **, int type);
42
43int clk_init(void);
44
45int __clk_enable(struct clk *);
46void __clk_disable(struct clk *);
47
48void clk_recalc_rate(struct clk *);
49
50int clk_register(struct clk *);
51void clk_unregister(struct clk *);
52
53/* the exported API, in addition to clk_set_rate */
54/**
55 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
56 * @clk: clock source
57 * @rate: desired clock rate in Hz
58 * @algo_id: algorithm id to be passed down to ops->set_rate
59 *
60 * Returns success (0) or negative errno.
61 */
62int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
63
64#endif /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 815a438a268d..2d28017e95d0 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -16,7 +16,7 @@
16({ \ 16({ \
17 __typeof(*(m)) __ret; \ 17 __typeof(*(m)) __ret; \
18 \ 18 \
19 if (kernel_uses_llsc && R10000_LLSC_WAR) { \ 19 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
20 __asm__ __volatile__( \ 20 __asm__ __volatile__( \
21 " .set push \n" \ 21 " .set push \n" \
22 " .set noat \n" \ 22 " .set noat \n" \
@@ -72,14 +72,14 @@
72 */ 72 */
73extern void __cmpxchg_called_with_bad_pointer(void); 73extern void __cmpxchg_called_with_bad_pointer(void);
74 74
75#define __cmpxchg(ptr, old, new, barrier) \ 75#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \
76({ \ 76({ \
77 __typeof__(ptr) __ptr = (ptr); \ 77 __typeof__(ptr) __ptr = (ptr); \
78 __typeof__(*(ptr)) __old = (old); \ 78 __typeof__(*(ptr)) __old = (old); \
79 __typeof__(*(ptr)) __new = (new); \ 79 __typeof__(*(ptr)) __new = (new); \
80 __typeof__(*(ptr)) __res = 0; \ 80 __typeof__(*(ptr)) __res = 0; \
81 \ 81 \
82 barrier; \ 82 pre_barrier; \
83 \ 83 \
84 switch (sizeof(*(__ptr))) { \ 84 switch (sizeof(*(__ptr))) { \
85 case 4: \ 85 case 4: \
@@ -96,13 +96,13 @@ extern void __cmpxchg_called_with_bad_pointer(void);
96 break; \ 96 break; \
97 } \ 97 } \
98 \ 98 \
99 barrier; \ 99 post_barrier; \
100 \ 100 \
101 __res; \ 101 __res; \
102}) 102})
103 103
104#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) 104#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
105#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, ) 105#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
106 106
107#define cmpxchg64(ptr, o, n) \ 107#define cmpxchg64(ptr, o, n) \
108 ({ \ 108 ({ \
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index f58aed354bfd..613f6912dfc1 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -8,7 +8,8 @@
8#include <asm/page.h> 8#include <asm/page.h>
9#include <asm/ptrace.h> 9#include <asm/ptrace.h>
10 10
11#define COMPAT_USER_HZ 100 11#define COMPAT_USER_HZ 100
12#define COMPAT_UTS_MACHINE "mips\0\0\0"
12 13
13typedef u32 compat_size_t; 14typedef u32 compat_size_t;
14typedef s32 compat_ssize_t; 15typedef s32 compat_ssize_t;
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
new file mode 100644
index 000000000000..6b04c98b7fad
--- /dev/null
+++ b/arch/mips/include/asm/cop2.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Wind River Systems,
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_COP2_H
10#define __ASM_COP2_H
11
12enum cu2_ops {
13 CU2_EXCEPTION,
14 CU2_LWC2_OP,
15 CU2_LDC2_OP,
16 CU2_SWC2_OP,
17 CU2_SDC2_OP,
18};
19
20extern int register_cu2_notifier(struct notifier_block *nb);
21extern int cu2_notifier_call_chain(unsigned long val, void *v);
22
23#endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1f4df647c384..ac73cede3a0a 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -95,6 +95,9 @@
95#ifndef cpu_has_smartmips 95#ifndef cpu_has_smartmips
96#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 96#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
97#endif 97#endif
98#ifndef kernel_uses_smartmips_rixi
99#define kernel_uses_smartmips_rixi 0
100#endif
98#ifndef cpu_has_vtag_icache 101#ifndef cpu_has_vtag_icache
99#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 102#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
100#endif 103#endif
@@ -191,6 +194,9 @@
191# ifndef cpu_has_64bit_addresses 194# ifndef cpu_has_64bit_addresses
192# define cpu_has_64bit_addresses 0 195# define cpu_has_64bit_addresses 0
193# endif 196# endif
197# ifndef cpu_vmbits
198# define cpu_vmbits 31
199# endif
194#endif 200#endif
195 201
196#ifdef CONFIG_64BIT 202#ifdef CONFIG_64BIT
@@ -209,6 +215,10 @@
209# ifndef cpu_has_64bit_addresses 215# ifndef cpu_has_64bit_addresses
210# define cpu_has_64bit_addresses 1 216# define cpu_has_64bit_addresses 1
211# endif 217# endif
218# ifndef cpu_vmbits
219# define cpu_vmbits cpu_data[0].vmbits
220# define __NEED_VMBITS_PROBE
221# endif
212#endif 222#endif
213 223
214#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 224#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 126044308dec..b39def3f6e03 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -58,6 +58,9 @@ struct cpuinfo_mips {
58 struct cache_desc tcache; /* Tertiary/split secondary cache */ 58 struct cache_desc tcache; /* Tertiary/split secondary cache */
59 int srsets; /* Shadow register sets */ 59 int srsets; /* Shadow register sets */
60 int core; /* physical core number */ 60 int core; /* physical core number */
61#ifdef CONFIG_64BIT
62 int vmbits; /* Virtual memory size in bits */
63#endif
61#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 64#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
62 /* 65 /*
63 * In the MIPS MT "SMTC" model, each TC is considered 66 * In the MIPS MT "SMTC" model, each TC is considered
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4b96d1a36056..a5acda416946 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -154,6 +154,8 @@
154#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 154#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
155#define PRID_REV_VR4130 0x0080 155#define PRID_REV_VR4130 0x0080
156#define PRID_REV_34K_V1_0_2 0x0022 156#define PRID_REV_34K_V1_0_2 0x0022
157#define PRID_REV_LOONGSON2E 0x0002
158#define PRID_REV_LOONGSON2F 0x0003
157 159
158/* 160/*
159 * Older processors used to encode processor version and revision in two 161 * Older processors used to encode processor version and revision in two
@@ -222,7 +224,7 @@ enum cpu_type_enum {
222 * MIPS64 class processors 224 * MIPS64 class processors
223 */ 225 */
224 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 226 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
225 CPU_CAVIUM_OCTEON, 227 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
226 228
227 CPU_LAST 229 CPU_LAST
228}; 230};
diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h
index 559db66b9790..4c51401b5537 100644
--- a/arch/mips/include/asm/current.h
+++ b/arch/mips/include/asm/current.h
@@ -1,23 +1 @@
1/* #include <asm-generic/current.h>
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2002 Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_CURRENT_H
10#define _ASM_CURRENT_H
11
12#include <linux/thread_info.h>
13
14struct task_struct;
15
16static inline struct task_struct * get_current(void)
17{
18 return current_thread_info()->task;
19}
20
21#define current get_current()
22
23#endif /* _ASM_CURRENT_H */
diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
index 28fa717ac423..88d9ffd74258 100644
--- a/arch/mips/include/asm/dec/kn01.h
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -80,7 +80,6 @@
80struct pt_regs; 80struct pt_regs;
81 81
82extern u16 cached_kn01_csr; 82extern u16 cached_kn01_csr;
83extern spinlock_t kn01_lock;
84 83
85extern void dec_kn01_be_init(void); 84extern void dec_kn01_be_init(void);
86extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup); 85extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
index d8f9872b0e2d..06746c5e8099 100644
--- a/arch/mips/include/asm/device.h
+++ b/arch/mips/include/asm/device.h
@@ -4,4 +4,3 @@
4 * This file is released under the GPLv2 4 * This file is released under the GPLv2
5 */ 5 */
6#include <asm-generic/device.h> 6#include <asm-generic/device.h>
7
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 7990694cda22..ea77a42c5f8c 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -310,6 +310,7 @@ do { \
310 310
311#endif /* CONFIG_64BIT */ 311#endif /* CONFIG_64BIT */
312 312
313struct pt_regs;
313struct task_struct; 314struct task_struct;
314 315
315extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); 316extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
@@ -326,7 +327,6 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
326#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ 327#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
327 dump_task_fpu(tsk, elf_fpregs) 328 dump_task_fpu(tsk, elf_fpregs)
328 329
329#define USE_ELF_CORE_DUMP
330#define ELF_EXEC_PAGESIZE PAGE_SIZE 330#define ELF_EXEC_PAGESIZE PAGE_SIZE
331 331
332/* This yields a mask that user programs can use to figure out what 332/* This yields a mask that user programs can use to figure out what
@@ -335,14 +335,14 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
335 335
336#define ELF_HWCAP (0) 336#define ELF_HWCAP (0)
337 337
338/* This yields a string that ld.so will use to load implementation 338/*
339 specific libraries for optimization. This is more specific in 339 * This yields a string that ld.so will use to load implementation
340 intent than poking at uname or /proc/cpuinfo. 340 * specific libraries for optimization. This is more specific in
341 341 * intent than poking at uname or /proc/cpuinfo.
342 For the moment, we have only optimizations for the Intel generations, 342 */
343 but that could change... */
344 343
345#define ELF_PLATFORM (NULL) 344#define ELF_PLATFORM __elf_platform
345extern const char *__elf_platform;
346 346
347/* 347/*
348 * See comments in asm-alpha/elf.h, this is the same thing 348 * See comments in asm-alpha/elf.h, this is the same thing
@@ -368,4 +368,8 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
368#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) 368#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
369#endif 369#endif
370 370
371#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
372struct linux_binprm;
373extern int arch_setup_additional_pages(struct linux_binprm *bprm,
374 int uses_interp);
371#endif /* _ASM_ELF_H */ 375#endif /* _ASM_ELF_H */
diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h
index 2a52333a062d..e482fe90fe88 100644
--- a/arch/mips/include/asm/fcntl.h
+++ b/arch/mips/include/asm/fcntl.h
@@ -10,7 +10,7 @@
10 10
11 11
12#define O_APPEND 0x0008 12#define O_APPEND 0x0008
13#define O_SYNC 0x0010 13#define O_DSYNC 0x0010 /* used to be O_SYNC, see below */
14#define O_NONBLOCK 0x0080 14#define O_NONBLOCK 0x0080
15#define O_CREAT 0x0100 /* not fcntl */ 15#define O_CREAT 0x0100 /* not fcntl */
16#define O_TRUNC 0x0200 /* not fcntl */ 16#define O_TRUNC 0x0200 /* not fcntl */
@@ -18,6 +18,21 @@
18#define O_NOCTTY 0x0800 /* not fcntl */ 18#define O_NOCTTY 0x0800 /* not fcntl */
19#define FASYNC 0x1000 /* fcntl, for BSD compatibility */ 19#define FASYNC 0x1000 /* fcntl, for BSD compatibility */
20#define O_LARGEFILE 0x2000 /* allow large file opens */ 20#define O_LARGEFILE 0x2000 /* allow large file opens */
21/*
22 * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
23 * the O_SYNC flag. We continue to use the existing numerical value
24 * for O_DSYNC semantics now, but using the correct symbolic name for it.
25 * This new value is used to request true Posix O_SYNC semantics. It is
26 * defined in this strange way to make sure applications compiled against
27 * new headers get at least O_DSYNC semantics on older kernels.
28 *
29 * This has the nice side-effect that we can simply test for O_DSYNC
30 * wherever we do not care if O_DSYNC or O_SYNC is used.
31 *
32 * Note: __O_SYNC must never be used directly.
33 */
34#define __O_SYNC 0x4000
35#define O_SYNC (__O_SYNC|O_DSYNC)
21#define O_DIRECT 0x8000 /* direct disk access hint */ 36#define O_DIRECT 0x8000 /* direct disk access hint */
22 37
23#define F_GETLK 14 38#define F_GETLK 14
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 8a3ef247659a..7fcef8ef3fab 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -28,15 +28,7 @@
28struct sigcontext; 28struct sigcontext;
29struct sigcontext32; 29struct sigcontext32;
30 30
31extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
32extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
33
34extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
35extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
36
37extern void fpu_emulator_init_fpu(void); 31extern void fpu_emulator_init_fpu(void);
38extern int fpu_emulator_save_context(struct sigcontext __user *sc);
39extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
40extern void _init_fpu(void); 32extern void _init_fpu(void);
41extern void _save_fp(struct task_struct *); 33extern void _save_fp(struct task_struct *);
42extern void _restore_fp(struct task_struct *); 34extern void _restore_fp(struct task_struct *);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index e5189572956c..3b4092705567 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -25,17 +25,31 @@
25 25
26#include <asm/break.h> 26#include <asm/break.h>
27#include <asm/inst.h> 27#include <asm/inst.h>
28#include <asm/local.h>
29
30#ifdef CONFIG_DEBUG_FS
28 31
29struct mips_fpu_emulator_stats { 32struct mips_fpu_emulator_stats {
30 unsigned int emulated; 33 local_t emulated;
31 unsigned int loads; 34 local_t loads;
32 unsigned int stores; 35 local_t stores;
33 unsigned int cp1ops; 36 local_t cp1ops;
34 unsigned int cp1xops; 37 local_t cp1xops;
35 unsigned int errors; 38 local_t errors;
36}; 39};
37 40
38extern struct mips_fpu_emulator_stats fpuemustats; 41DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
42
43#define MIPS_FPU_EMU_INC_STATS(M) \
44do { \
45 preempt_disable(); \
46 __local_inc(&__get_cpu_var(fpuemustats).M); \
47 preempt_enable(); \
48} while (0)
49
50#else
51#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
52#endif /* CONFIG_DEBUG_FS */
39 53
40extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, 54extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
41 unsigned long cpc); 55 unsigned long cpc);
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 40a8c178f10d..ce35c9af0c28 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -1 +1,90 @@
1/* empty */ 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive for
4 * more details.
5 *
6 * Copyright (C) 2009 DSLab, Lanzhou University, China
7 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
8 */
9
10#ifndef _ASM_MIPS_FTRACE_H
11#define _ASM_MIPS_FTRACE_H
12
13#ifdef CONFIG_FUNCTION_TRACER
14
15#define MCOUNT_ADDR ((unsigned long)(_mcount))
16#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
17
18#ifndef __ASSEMBLY__
19extern void _mcount(void);
20#define mcount _mcount
21
22#define safe_load(load, src, dst, error) \
23do { \
24 asm volatile ( \
25 "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
26 " li %[" STR(error) "], 0\n" \
27 "2:\n" \
28 \
29 ".section .fixup, \"ax\"\n" \
30 "3: li %[" STR(error) "], 1\n" \
31 " j 2b\n" \
32 ".previous\n" \
33 \
34 ".section\t__ex_table,\"a\"\n\t" \
35 STR(PTR) "\t1b, 3b\n\t" \
36 ".previous\n" \
37 \
38 : [dst] "=&r" (dst), [error] "=r" (error)\
39 : [src] "r" (src) \
40 : "memory" \
41 ); \
42} while (0)
43
44#define safe_store(store, src, dst, error) \
45do { \
46 asm volatile ( \
47 "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
48 " li %[" STR(error) "], 0\n" \
49 "2:\n" \
50 \
51 ".section .fixup, \"ax\"\n" \
52 "3: li %[" STR(error) "], 1\n" \
53 " j 2b\n" \
54 ".previous\n" \
55 \
56 ".section\t__ex_table,\"a\"\n\t"\
57 STR(PTR) "\t1b, 3b\n\t" \
58 ".previous\n" \
59 \
60 : [error] "=r" (error) \
61 : [dst] "r" (dst), [src] "r" (src)\
62 : "memory" \
63 ); \
64} while (0)
65
66#define safe_load_code(dst, src, error) \
67 safe_load(STR(lw), src, dst, error)
68#define safe_store_code(src, dst, error) \
69 safe_store(STR(sw), src, dst, error)
70
71#define safe_load_stack(dst, src, error) \
72 safe_load(STR(PTR_L), src, dst, error)
73
74#define safe_store_stack(src, dst, error) \
75 safe_store(STR(PTR_S), src, dst, error)
76
77
78#ifdef CONFIG_DYNAMIC_FTRACE
79static inline unsigned long ftrace_call_adjust(unsigned long addr)
80{
81 return addr;
82}
83
84struct dyn_arch_ftrace {
85};
86
87#endif /* CONFIG_DYNAMIC_FTRACE */
88#endif /* __ASSEMBLY__ */
89#endif /* CONFIG_FUNCTION_TRACER */
90#endif /* _ASM_MIPS_FTRACE_H */
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index 8572a2d90484..c7e278447c0a 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -35,7 +35,7 @@
35#define SLAVE_ICW4_DEFAULT 0x01 35#define SLAVE_ICW4_DEFAULT 0x01
36#define PIC_ICW4_AEOI 2 36#define PIC_ICW4_AEOI 2
37 37
38extern spinlock_t i8259A_lock; 38extern raw_spinlock_t i8259A_lock;
39 39
40extern int i8259A_irq_pending(unsigned int irq); 40extern int i8259A_irq_pending(unsigned int irq);
41extern void make_8259A_irq(unsigned int irq); 41extern void make_8259A_irq(unsigned int irq);
@@ -51,7 +51,7 @@ static inline int i8259_irq(void)
51{ 51{
52 int irq; 52 int irq;
53 53
54 spin_lock(&i8259A_lock); 54 raw_spin_lock(&i8259A_lock);
55 55
56 /* Perform an interrupt acknowledge cycle on controller 1. */ 56 /* Perform an interrupt acknowledge cycle on controller 1. */
57 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ 57 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
@@ -78,7 +78,7 @@ static inline int i8259_irq(void)
78 irq = -1; 78 irq = -1;
79 } 79 }
80 80
81 spin_unlock(&i8259A_lock); 81 raw_spin_unlock(&i8259A_lock);
82 82
83 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; 83 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
84} 84}
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 436878e4e063..c98bf514ec7d 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -447,6 +447,24 @@ __BUILDIO(q, u64)
447#define readl_relaxed readl 447#define readl_relaxed readl
448#define readq_relaxed readq 448#define readq_relaxed readq
449 449
450#define readb_be(addr) \
451 __raw_readb((__force unsigned *)(addr))
452#define readw_be(addr) \
453 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
454#define readl_be(addr) \
455 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
456#define readq_be(addr) \
457 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
458
459#define writeb_be(val, addr) \
460 __raw_writeb((val), (__force unsigned *)(addr))
461#define writew_be(val, addr) \
462 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
463#define writel_be(val, addr) \
464 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
465#define writeq_be(val, addr) \
466 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
467
450/* 468/*
451 * Some code tests for these symbols 469 * Some code tests for these symbols
452 */ 470 */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 09b08d05ff72..dea4aed6478f 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -113,36 +113,11 @@ do { \
113 113
114#endif 114#endif
115 115
116/* 116extern void do_IRQ(unsigned int irq);
117 * do_IRQ handles all normal device IRQ's (the special
118 * SMP cross-CPU interrupts have their own specific
119 * handlers).
120 *
121 * Ideally there should be away to get this into kernel/irq/handle.c to
122 * avoid the overhead of a call for just a tiny function ...
123 */
124#define do_IRQ(irq) \
125do { \
126 irq_enter(); \
127 __DO_IRQ_SMTC_HOOK(irq); \
128 generic_handle_irq(irq); \
129 irq_exit(); \
130} while (0)
131 117
132#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 118#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
133/*
134 * To avoid inefficient and in some cases pathological re-checking of
135 * IRQ affinity, we have this variant that skips the affinity check.
136 */
137
138 119
139#define do_IRQ_no_affinity(irq) \ 120extern void do_IRQ_no_affinity(unsigned int irq);
140do { \
141 irq_enter(); \
142 __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
143 generic_handle_irq(irq); \
144 irq_exit(); \
145} while (0)
146 121
147#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 122#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
148 123
@@ -160,6 +135,7 @@ extern void free_irqno(unsigned int irq);
160#define CP0_LEGACY_COMPARE_IRQ 7 135#define CP0_LEGACY_COMPARE_IRQ 7
161 136
162extern int cp0_compare_irq; 137extern int cp0_compare_irq;
138extern int cp0_compare_irq_shift;
163extern int cp0_perfcount_irq; 139extern int cp0_perfcount_irq;
164 140
165#endif /* _ASM_IRQ_H */ 141#endif /* _ASM_IRQ_H */
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index 361f4f16c30c..bdcdef02d147 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -193,29 +193,4 @@ static __inline__ long local_sub_return(long i, local_t * l)
193#define __local_add(i, l) ((l)->a.counter+=(i)) 193#define __local_add(i, l) ((l)->a.counter+=(i))
194#define __local_sub(i, l) ((l)->a.counter-=(i)) 194#define __local_sub(i, l) ((l)->a.counter-=(i))
195 195
196/* Need to disable preemption for the cpu local counters otherwise we could
197 still access a variable of a previous CPU in a non atomic way. */
198#define cpu_local_wrap_v(l) \
199 ({ local_t res__; \
200 preempt_disable(); \
201 res__ = (l); \
202 preempt_enable(); \
203 res__; })
204#define cpu_local_wrap(l) \
205 ({ preempt_disable(); \
206 l; \
207 preempt_enable(); }) \
208
209#define cpu_local_read(l) cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
210#define cpu_local_set(l, i) cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
211#define cpu_local_inc(l) cpu_local_wrap(local_inc(&__get_cpu_var(l)))
212#define cpu_local_dec(l) cpu_local_wrap(local_dec(&__get_cpu_var(l)))
213#define cpu_local_add(i, l) cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
214#define cpu_local_sub(i, l) cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
215
216#define __cpu_local_inc(l) cpu_local_inc(l)
217#define __cpu_local_dec(l) cpu_local_dec(l)
218#define __cpu_local_add(i, l) cpu_local_add((i), (l))
219#define __cpu_local_sub(i, l) cpu_local_sub((i), (l))
220
221#endif /* _ARCH_MIPS_LOCAL_H */ 196#endif /* _ARCH_MIPS_LOCAL_H */
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 21cbbc706448..f1cf38943497 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -105,26 +105,9 @@ static inline u8 ar7_chip_rev(void)
105 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; 105 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
106} 106}
107 107
108static inline int ar7_cpu_freq(void) 108struct clk {
109{ 109 unsigned int rate;
110 return ar7_cpu_clock; 110};
111}
112
113static inline int ar7_bus_freq(void)
114{
115 return ar7_bus_clock;
116}
117
118static inline int ar7_vbus_freq(void)
119{
120 return ar7_bus_clock / 2;
121}
122#define ar7_cpmac_freq ar7_vbus_freq
123
124static inline int ar7_dsp_freq(void)
125{
126 return ar7_dsp_clock;
127}
128 111
129static inline int ar7_has_high_cpmac(void) 112static inline int ar7_has_high_cpmac(void)
130{ 113{
diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h
index cbe9c4f126df..73f9b162c970 100644
--- a/arch/mips/include/asm/mach-ar7/gpio.h
+++ b/arch/mips/include/asm/mach-ar7/gpio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org> 2 * Copyright (C) 2007-2009 Florian Fainelli <florian@openwrt.org>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 5 * it under the terms of the GNU General Public License as published by
@@ -22,88 +22,18 @@
22#include <asm/mach-ar7/ar7.h> 22#include <asm/mach-ar7/ar7.h>
23 23
24#define AR7_GPIO_MAX 32 24#define AR7_GPIO_MAX 32
25#define NR_BUILTIN_GPIO AR7_GPIO_MAX
25 26
26extern int gpio_request(unsigned gpio, const char *label); 27#define gpio_to_irq(gpio) NULL
27extern void gpio_free(unsigned gpio);
28 28
29/* Common GPIO layer */ 29#define gpio_get_value __gpio_get_value
30static inline int gpio_get_value(unsigned gpio) 30#define gpio_set_value __gpio_set_value
31{
32 void __iomem *gpio_in =
33 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
34 31
35 return readl(gpio_in) & (1 << gpio); 32#define gpio_cansleep __gpio_cansleep
36}
37
38static inline void gpio_set_value(unsigned gpio, int value)
39{
40 void __iomem *gpio_out =
41 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
42 unsigned tmp;
43
44 tmp = readl(gpio_out) & ~(1 << gpio);
45 if (value)
46 tmp |= 1 << gpio;
47 writel(tmp, gpio_out);
48}
49
50static inline int gpio_direction_input(unsigned gpio)
51{
52 void __iomem *gpio_dir =
53 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
54
55 if (gpio >= AR7_GPIO_MAX)
56 return -EINVAL;
57
58 writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
59
60 return 0;
61}
62
63static inline int gpio_direction_output(unsigned gpio, int value)
64{
65 void __iomem *gpio_dir =
66 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
67
68 if (gpio >= AR7_GPIO_MAX)
69 return -EINVAL;
70
71 gpio_set_value(gpio, value);
72 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
73
74 return 0;
75}
76
77static inline int gpio_to_irq(unsigned gpio)
78{
79 return -EINVAL;
80}
81
82static inline int irq_to_gpio(unsigned irq)
83{
84 return -EINVAL;
85}
86 33
87/* Board specific GPIO functions */ 34/* Board specific GPIO functions */
88static inline int ar7_gpio_enable(unsigned gpio) 35int ar7_gpio_enable(unsigned gpio);
89{ 36int ar7_gpio_disable(unsigned gpio);
90 void __iomem *gpio_en =
91 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
92
93 writel(readl(gpio_en) | (1 << gpio), gpio_en);
94
95 return 0;
96}
97
98static inline int ar7_gpio_disable(unsigned gpio)
99{
100 void __iomem *gpio_en =
101 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
102
103 writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
104
105 return 0;
106}
107 37
108#include <asm-generic/gpio.h> 38#include <asm-generic/gpio.h>
109 39
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 854e95f1b07c..ae07423e6e82 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -130,6 +130,56 @@ static inline int au1xxx_cpu_needs_config_od(void)
130 return 0; 130 return 0;
131} 131}
132 132
133#define ALCHEMY_CPU_UNKNOWN -1
134#define ALCHEMY_CPU_AU1000 0
135#define ALCHEMY_CPU_AU1500 1
136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4
139
140static inline int alchemy_get_cputype(void)
141{
142 switch (read_c0_prid() & 0xffff0000) {
143 case 0x00030000:
144 return ALCHEMY_CPU_AU1000;
145 break;
146 case 0x01030000:
147 return ALCHEMY_CPU_AU1500;
148 break;
149 case 0x02030000:
150 return ALCHEMY_CPU_AU1100;
151 break;
152 case 0x03030000:
153 return ALCHEMY_CPU_AU1550;
154 break;
155 case 0x04030000:
156 case 0x05030000:
157 return ALCHEMY_CPU_AU1200;
158 break;
159 }
160
161 return ALCHEMY_CPU_UNKNOWN;
162}
163
164static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
165{
166 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
167 int timeout, i;
168
169 /* check LSR TX_EMPTY bit */
170 timeout = 0xffffff;
171 do {
172 if (__raw_readl(base + 0x1c) & 0x20)
173 break;
174 /* slow down */
175 for (i = 10000; i; i--)
176 asm volatile ("nop");
177 } while (--timeout);
178
179 __raw_writel(c, base + 0x04); /* tx */
180 wmb();
181}
182
133/* arch/mips/au1000/common/clocks.c */ 183/* arch/mips/au1000/common/clocks.c */
134extern void set_au1x00_speed(unsigned int new_freq); 184extern void set_au1x00_speed(unsigned int new_freq);
135extern unsigned int get_au1x00_speed(void); 185extern unsigned int get_au1x00_speed(void);
@@ -143,20 +193,332 @@ void au_sleep(void);
143void save_au1xxx_intctl(void); 193void save_au1xxx_intctl(void);
144void restore_au1xxx_intctl(void); 194void restore_au1xxx_intctl(void);
145 195
146/* 196
147 * Every board describes its IRQ mapping with this table. 197/* SOC Interrupt numbers */
148 */ 198
149struct au1xxx_irqmap { 199#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
150 int im_irq; 200#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
151 int im_type; 201#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
152 int im_request; 202#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
203#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
204
205enum soc_au1000_ints {
206 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
207 AU1000_UART0_INT = AU1000_FIRST_INT,
208 AU1000_UART1_INT,
209 AU1000_UART2_INT,
210 AU1000_UART3_INT,
211 AU1000_SSI0_INT,
212 AU1000_SSI1_INT,
213 AU1000_DMA_INT_BASE,
214
215 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
216 AU1000_TOY_MATCH0_INT,
217 AU1000_TOY_MATCH1_INT,
218 AU1000_TOY_MATCH2_INT,
219 AU1000_RTC_INT,
220 AU1000_RTC_MATCH0_INT,
221 AU1000_RTC_MATCH1_INT,
222 AU1000_RTC_MATCH2_INT,
223 AU1000_IRDA_TX_INT,
224 AU1000_IRDA_RX_INT,
225 AU1000_USB_DEV_REQ_INT,
226 AU1000_USB_DEV_SUS_INT,
227 AU1000_USB_HOST_INT,
228 AU1000_ACSYNC_INT,
229 AU1000_MAC0_DMA_INT,
230 AU1000_MAC1_DMA_INT,
231 AU1000_I2S_UO_INT,
232 AU1000_AC97C_INT,
233 AU1000_GPIO0_INT,
234 AU1000_GPIO1_INT,
235 AU1000_GPIO2_INT,
236 AU1000_GPIO3_INT,
237 AU1000_GPIO4_INT,
238 AU1000_GPIO5_INT,
239 AU1000_GPIO6_INT,
240 AU1000_GPIO7_INT,
241 AU1000_GPIO8_INT,
242 AU1000_GPIO9_INT,
243 AU1000_GPIO10_INT,
244 AU1000_GPIO11_INT,
245 AU1000_GPIO12_INT,
246 AU1000_GPIO13_INT,
247 AU1000_GPIO14_INT,
248 AU1000_GPIO15_INT,
249 AU1000_GPIO16_INT,
250 AU1000_GPIO17_INT,
251 AU1000_GPIO18_INT,
252 AU1000_GPIO19_INT,
253 AU1000_GPIO20_INT,
254 AU1000_GPIO21_INT,
255 AU1000_GPIO22_INT,
256 AU1000_GPIO23_INT,
257 AU1000_GPIO24_INT,
258 AU1000_GPIO25_INT,
259 AU1000_GPIO26_INT,
260 AU1000_GPIO27_INT,
261 AU1000_GPIO28_INT,
262 AU1000_GPIO29_INT,
263 AU1000_GPIO30_INT,
264 AU1000_GPIO31_INT,
153}; 265};
154 266
155/* core calls this function to let boards initialize other IRQ sources */ 267enum soc_au1100_ints {
156void board_init_irq(void); 268 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
269 AU1100_UART0_INT = AU1100_FIRST_INT,
270 AU1100_UART1_INT,
271 AU1100_SD_INT,
272 AU1100_UART3_INT,
273 AU1100_SSI0_INT,
274 AU1100_SSI1_INT,
275 AU1100_DMA_INT_BASE,
276
277 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
278 AU1100_TOY_MATCH0_INT,
279 AU1100_TOY_MATCH1_INT,
280 AU1100_TOY_MATCH2_INT,
281 AU1100_RTC_INT,
282 AU1100_RTC_MATCH0_INT,
283 AU1100_RTC_MATCH1_INT,
284 AU1100_RTC_MATCH2_INT,
285 AU1100_IRDA_TX_INT,
286 AU1100_IRDA_RX_INT,
287 AU1100_USB_DEV_REQ_INT,
288 AU1100_USB_DEV_SUS_INT,
289 AU1100_USB_HOST_INT,
290 AU1100_ACSYNC_INT,
291 AU1100_MAC0_DMA_INT,
292 AU1100_GPIO208_215_INT,
293 AU1100_LCD_INT,
294 AU1100_AC97C_INT,
295 AU1100_GPIO0_INT,
296 AU1100_GPIO1_INT,
297 AU1100_GPIO2_INT,
298 AU1100_GPIO3_INT,
299 AU1100_GPIO4_INT,
300 AU1100_GPIO5_INT,
301 AU1100_GPIO6_INT,
302 AU1100_GPIO7_INT,
303 AU1100_GPIO8_INT,
304 AU1100_GPIO9_INT,
305 AU1100_GPIO10_INT,
306 AU1100_GPIO11_INT,
307 AU1100_GPIO12_INT,
308 AU1100_GPIO13_INT,
309 AU1100_GPIO14_INT,
310 AU1100_GPIO15_INT,
311 AU1100_GPIO16_INT,
312 AU1100_GPIO17_INT,
313 AU1100_GPIO18_INT,
314 AU1100_GPIO19_INT,
315 AU1100_GPIO20_INT,
316 AU1100_GPIO21_INT,
317 AU1100_GPIO22_INT,
318 AU1100_GPIO23_INT,
319 AU1100_GPIO24_INT,
320 AU1100_GPIO25_INT,
321 AU1100_GPIO26_INT,
322 AU1100_GPIO27_INT,
323 AU1100_GPIO28_INT,
324 AU1100_GPIO29_INT,
325 AU1100_GPIO30_INT,
326 AU1100_GPIO31_INT,
327};
157 328
158/* boards call this to register additional (GPIO) interrupts */ 329enum soc_au1500_ints {
159void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); 330 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
331 AU1500_UART0_INT = AU1500_FIRST_INT,
332 AU1500_PCI_INTA,
333 AU1500_PCI_INTB,
334 AU1500_UART3_INT,
335 AU1500_PCI_INTC,
336 AU1500_PCI_INTD,
337 AU1500_DMA_INT_BASE,
338
339 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
340 AU1500_TOY_MATCH0_INT,
341 AU1500_TOY_MATCH1_INT,
342 AU1500_TOY_MATCH2_INT,
343 AU1500_RTC_INT,
344 AU1500_RTC_MATCH0_INT,
345 AU1500_RTC_MATCH1_INT,
346 AU1500_RTC_MATCH2_INT,
347 AU1500_PCI_ERR_INT,
348 AU1500_RESERVED_INT,
349 AU1500_USB_DEV_REQ_INT,
350 AU1500_USB_DEV_SUS_INT,
351 AU1500_USB_HOST_INT,
352 AU1500_ACSYNC_INT,
353 AU1500_MAC0_DMA_INT,
354 AU1500_MAC1_DMA_INT,
355 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
356 AU1500_GPIO0_INT,
357 AU1500_GPIO1_INT,
358 AU1500_GPIO2_INT,
359 AU1500_GPIO3_INT,
360 AU1500_GPIO4_INT,
361 AU1500_GPIO5_INT,
362 AU1500_GPIO6_INT,
363 AU1500_GPIO7_INT,
364 AU1500_GPIO8_INT,
365 AU1500_GPIO9_INT,
366 AU1500_GPIO10_INT,
367 AU1500_GPIO11_INT,
368 AU1500_GPIO12_INT,
369 AU1500_GPIO13_INT,
370 AU1500_GPIO14_INT,
371 AU1500_GPIO15_INT,
372 AU1500_GPIO200_INT,
373 AU1500_GPIO201_INT,
374 AU1500_GPIO202_INT,
375 AU1500_GPIO203_INT,
376 AU1500_GPIO20_INT,
377 AU1500_GPIO204_INT,
378 AU1500_GPIO205_INT,
379 AU1500_GPIO23_INT,
380 AU1500_GPIO24_INT,
381 AU1500_GPIO25_INT,
382 AU1500_GPIO26_INT,
383 AU1500_GPIO27_INT,
384 AU1500_GPIO28_INT,
385 AU1500_GPIO206_INT,
386 AU1500_GPIO207_INT,
387 AU1500_GPIO208_215_INT,
388};
389
390enum soc_au1550_ints {
391 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
392 AU1550_UART0_INT = AU1550_FIRST_INT,
393 AU1550_PCI_INTA,
394 AU1550_PCI_INTB,
395 AU1550_DDMA_INT,
396 AU1550_CRYPTO_INT,
397 AU1550_PCI_INTC,
398 AU1550_PCI_INTD,
399 AU1550_PCI_RST_INT,
400 AU1550_UART1_INT,
401 AU1550_UART3_INT,
402 AU1550_PSC0_INT,
403 AU1550_PSC1_INT,
404 AU1550_PSC2_INT,
405 AU1550_PSC3_INT,
406 AU1550_TOY_INT,
407 AU1550_TOY_MATCH0_INT,
408 AU1550_TOY_MATCH1_INT,
409 AU1550_TOY_MATCH2_INT,
410 AU1550_RTC_INT,
411 AU1550_RTC_MATCH0_INT,
412 AU1550_RTC_MATCH1_INT,
413 AU1550_RTC_MATCH2_INT,
414
415 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
416 AU1550_USB_DEV_REQ_INT,
417 AU1550_USB_DEV_SUS_INT,
418 AU1550_USB_HOST_INT,
419 AU1550_MAC0_DMA_INT,
420 AU1550_MAC1_DMA_INT,
421 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
422 AU1550_GPIO1_INT,
423 AU1550_GPIO2_INT,
424 AU1550_GPIO3_INT,
425 AU1550_GPIO4_INT,
426 AU1550_GPIO5_INT,
427 AU1550_GPIO6_INT,
428 AU1550_GPIO7_INT,
429 AU1550_GPIO8_INT,
430 AU1550_GPIO9_INT,
431 AU1550_GPIO10_INT,
432 AU1550_GPIO11_INT,
433 AU1550_GPIO12_INT,
434 AU1550_GPIO13_INT,
435 AU1550_GPIO14_INT,
436 AU1550_GPIO15_INT,
437 AU1550_GPIO200_INT,
438 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
439 AU1550_GPIO16_INT,
440 AU1550_GPIO17_INT,
441 AU1550_GPIO20_INT,
442 AU1550_GPIO21_INT,
443 AU1550_GPIO22_INT,
444 AU1550_GPIO23_INT,
445 AU1550_GPIO24_INT,
446 AU1550_GPIO25_INT,
447 AU1550_GPIO26_INT,
448 AU1550_GPIO27_INT,
449 AU1550_GPIO28_INT,
450 AU1550_GPIO206_INT,
451 AU1550_GPIO207_INT,
452 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
453};
454
455enum soc_au1200_ints {
456 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
457 AU1200_UART0_INT = AU1200_FIRST_INT,
458 AU1200_SWT_INT,
459 AU1200_SD_INT,
460 AU1200_DDMA_INT,
461 AU1200_MAE_BE_INT,
462 AU1200_GPIO200_INT,
463 AU1200_GPIO201_INT,
464 AU1200_GPIO202_INT,
465 AU1200_UART1_INT,
466 AU1200_MAE_FE_INT,
467 AU1200_PSC0_INT,
468 AU1200_PSC1_INT,
469 AU1200_AES_INT,
470 AU1200_CAMERA_INT,
471 AU1200_TOY_INT,
472 AU1200_TOY_MATCH0_INT,
473 AU1200_TOY_MATCH1_INT,
474 AU1200_TOY_MATCH2_INT,
475 AU1200_RTC_INT,
476 AU1200_RTC_MATCH0_INT,
477 AU1200_RTC_MATCH1_INT,
478 AU1200_RTC_MATCH2_INT,
479 AU1200_GPIO203_INT,
480 AU1200_NAND_INT,
481 AU1200_GPIO204_INT,
482 AU1200_GPIO205_INT,
483 AU1200_GPIO206_INT,
484 AU1200_GPIO207_INT,
485 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
486 AU1200_USB_INT,
487 AU1200_LCD_INT,
488 AU1200_MAE_BOTH_INT,
489 AU1200_GPIO0_INT,
490 AU1200_GPIO1_INT,
491 AU1200_GPIO2_INT,
492 AU1200_GPIO3_INT,
493 AU1200_GPIO4_INT,
494 AU1200_GPIO5_INT,
495 AU1200_GPIO6_INT,
496 AU1200_GPIO7_INT,
497 AU1200_GPIO8_INT,
498 AU1200_GPIO9_INT,
499 AU1200_GPIO10_INT,
500 AU1200_GPIO11_INT,
501 AU1200_GPIO12_INT,
502 AU1200_GPIO13_INT,
503 AU1200_GPIO14_INT,
504 AU1200_GPIO15_INT,
505 AU1200_GPIO16_INT,
506 AU1200_GPIO17_INT,
507 AU1200_GPIO18_INT,
508 AU1200_GPIO19_INT,
509 AU1200_GPIO20_INT,
510 AU1200_GPIO21_INT,
511 AU1200_GPIO22_INT,
512 AU1200_GPIO23_INT,
513 AU1200_GPIO24_INT,
514 AU1200_GPIO25_INT,
515 AU1200_GPIO26_INT,
516 AU1200_GPIO27_INT,
517 AU1200_GPIO28_INT,
518 AU1200_GPIO29_INT,
519 AU1200_GPIO30_INT,
520 AU1200_GPIO31_INT,
521};
160 522
161#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 523#endif /* !defined (_LANGUAGE_ASSEMBLY) */
162 524
@@ -549,78 +911,16 @@ void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
549 911
550#define IC1_TESTBIT 0xB1800080 912#define IC1_TESTBIT 0xB1800080
551 913
552/* Interrupt Numbers */ 914
553/* Au1000 */ 915/* Au1000 */
554#ifdef CONFIG_SOC_AU1000 916#ifdef CONFIG_SOC_AU1000
555enum soc_au1000_ints {
556 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
557 AU1000_UART0_INT = AU1000_FIRST_INT,
558 AU1000_UART1_INT, /* au1000 */
559 AU1000_UART2_INT, /* au1000 */
560 AU1000_UART3_INT,
561 AU1000_SSI0_INT, /* au1000 */
562 AU1000_SSI1_INT, /* au1000 */
563 AU1000_DMA_INT_BASE,
564
565 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
566 AU1000_TOY_MATCH0_INT,
567 AU1000_TOY_MATCH1_INT,
568 AU1000_TOY_MATCH2_INT,
569 AU1000_RTC_INT,
570 AU1000_RTC_MATCH0_INT,
571 AU1000_RTC_MATCH1_INT,
572 AU1000_RTC_MATCH2_INT,
573 AU1000_IRDA_TX_INT, /* au1000 */
574 AU1000_IRDA_RX_INT, /* au1000 */
575 AU1000_USB_DEV_REQ_INT,
576 AU1000_USB_DEV_SUS_INT,
577 AU1000_USB_HOST_INT,
578 AU1000_ACSYNC_INT,
579 AU1000_MAC0_DMA_INT,
580 AU1000_MAC1_DMA_INT,
581 AU1000_I2S_UO_INT, /* au1000 */
582 AU1000_AC97C_INT,
583 AU1000_GPIO_0,
584 AU1000_GPIO_1,
585 AU1000_GPIO_2,
586 AU1000_GPIO_3,
587 AU1000_GPIO_4,
588 AU1000_GPIO_5,
589 AU1000_GPIO_6,
590 AU1000_GPIO_7,
591 AU1000_GPIO_8,
592 AU1000_GPIO_9,
593 AU1000_GPIO_10,
594 AU1000_GPIO_11,
595 AU1000_GPIO_12,
596 AU1000_GPIO_13,
597 AU1000_GPIO_14,
598 AU1000_GPIO_15,
599 AU1000_GPIO_16,
600 AU1000_GPIO_17,
601 AU1000_GPIO_18,
602 AU1000_GPIO_19,
603 AU1000_GPIO_20,
604 AU1000_GPIO_21,
605 AU1000_GPIO_22,
606 AU1000_GPIO_23,
607 AU1000_GPIO_24,
608 AU1000_GPIO_25,
609 AU1000_GPIO_26,
610 AU1000_GPIO_27,
611 AU1000_GPIO_28,
612 AU1000_GPIO_29,
613 AU1000_GPIO_30,
614 AU1000_GPIO_31,
615};
616 917
617#define UART0_ADDR 0xB1100000 918#define UART0_ADDR 0xB1100000
618#define UART1_ADDR 0xB1200000
619#define UART2_ADDR 0xB1300000
620#define UART3_ADDR 0xB1400000 919#define UART3_ADDR 0xB1400000
621 920
622#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 921#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
623#define USB_HOST_CONFIG 0xB017FFFC 922#define USB_HOST_CONFIG 0xB017FFFC
923#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
624 924
625#define AU1000_ETH0_BASE 0xB0500000 925#define AU1000_ETH0_BASE 0xB0500000
626#define AU1000_ETH1_BASE 0xB0510000 926#define AU1000_ETH1_BASE 0xB0510000
@@ -631,78 +931,13 @@ enum soc_au1000_ints {
631 931
632/* Au1500 */ 932/* Au1500 */
633#ifdef CONFIG_SOC_AU1500 933#ifdef CONFIG_SOC_AU1500
634enum soc_au1500_ints {
635 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
636 AU1500_UART0_INT = AU1500_FIRST_INT,
637 AU1000_PCI_INTA, /* au1500 */
638 AU1000_PCI_INTB, /* au1500 */
639 AU1500_UART3_INT,
640 AU1000_PCI_INTC, /* au1500 */
641 AU1000_PCI_INTD, /* au1500 */
642 AU1000_DMA_INT_BASE,
643
644 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
645 AU1000_TOY_MATCH0_INT,
646 AU1000_TOY_MATCH1_INT,
647 AU1000_TOY_MATCH2_INT,
648 AU1000_RTC_INT,
649 AU1000_RTC_MATCH0_INT,
650 AU1000_RTC_MATCH1_INT,
651 AU1000_RTC_MATCH2_INT,
652 AU1500_PCI_ERR_INT,
653 AU1500_RESERVED_INT,
654 AU1000_USB_DEV_REQ_INT,
655 AU1000_USB_DEV_SUS_INT,
656 AU1000_USB_HOST_INT,
657 AU1000_ACSYNC_INT,
658 AU1500_MAC0_DMA_INT,
659 AU1500_MAC1_DMA_INT,
660 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
661 AU1000_GPIO_0,
662 AU1000_GPIO_1,
663 AU1000_GPIO_2,
664 AU1000_GPIO_3,
665 AU1000_GPIO_4,
666 AU1000_GPIO_5,
667 AU1000_GPIO_6,
668 AU1000_GPIO_7,
669 AU1000_GPIO_8,
670 AU1000_GPIO_9,
671 AU1000_GPIO_10,
672 AU1000_GPIO_11,
673 AU1000_GPIO_12,
674 AU1000_GPIO_13,
675 AU1000_GPIO_14,
676 AU1000_GPIO_15,
677 AU1500_GPIO_200,
678 AU1500_GPIO_201,
679 AU1500_GPIO_202,
680 AU1500_GPIO_203,
681 AU1500_GPIO_20,
682 AU1500_GPIO_204,
683 AU1500_GPIO_205,
684 AU1500_GPIO_23,
685 AU1500_GPIO_24,
686 AU1500_GPIO_25,
687 AU1500_GPIO_26,
688 AU1500_GPIO_27,
689 AU1500_GPIO_28,
690 AU1500_GPIO_206,
691 AU1500_GPIO_207,
692 AU1500_GPIO_208_215,
693};
694
695/* shortcuts */
696#define INTA AU1000_PCI_INTA
697#define INTB AU1000_PCI_INTB
698#define INTC AU1000_PCI_INTC
699#define INTD AU1000_PCI_INTD
700 934
701#define UART0_ADDR 0xB1100000 935#define UART0_ADDR 0xB1100000
702#define UART3_ADDR 0xB1400000 936#define UART3_ADDR 0xB1400000
703 937
704#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 938#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
705#define USB_HOST_CONFIG 0xB017fffc 939#define USB_HOST_CONFIG 0xB017fffc
940#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
706 941
707#define AU1500_ETH0_BASE 0xB1500000 942#define AU1500_ETH0_BASE 0xB1500000
708#define AU1500_ETH1_BASE 0xB1510000 943#define AU1500_ETH1_BASE 0xB1510000
@@ -713,74 +948,13 @@ enum soc_au1500_ints {
713 948
714/* Au1100 */ 949/* Au1100 */
715#ifdef CONFIG_SOC_AU1100 950#ifdef CONFIG_SOC_AU1100
716enum soc_au1100_ints {
717 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
718 AU1100_UART0_INT = AU1100_FIRST_INT,
719 AU1100_UART1_INT,
720 AU1100_SD_INT,
721 AU1100_UART3_INT,
722 AU1000_SSI0_INT,
723 AU1000_SSI1_INT,
724 AU1000_DMA_INT_BASE,
725
726 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
727 AU1000_TOY_MATCH0_INT,
728 AU1000_TOY_MATCH1_INT,
729 AU1000_TOY_MATCH2_INT,
730 AU1000_RTC_INT,
731 AU1000_RTC_MATCH0_INT,
732 AU1000_RTC_MATCH1_INT,
733 AU1000_RTC_MATCH2_INT,
734 AU1000_IRDA_TX_INT,
735 AU1000_IRDA_RX_INT,
736 AU1000_USB_DEV_REQ_INT,
737 AU1000_USB_DEV_SUS_INT,
738 AU1000_USB_HOST_INT,
739 AU1000_ACSYNC_INT,
740 AU1100_MAC0_DMA_INT,
741 AU1100_GPIO_208_215,
742 AU1100_LCD_INT,
743 AU1000_AC97C_INT,
744 AU1000_GPIO_0,
745 AU1000_GPIO_1,
746 AU1000_GPIO_2,
747 AU1000_GPIO_3,
748 AU1000_GPIO_4,
749 AU1000_GPIO_5,
750 AU1000_GPIO_6,
751 AU1000_GPIO_7,
752 AU1000_GPIO_8,
753 AU1000_GPIO_9,
754 AU1000_GPIO_10,
755 AU1000_GPIO_11,
756 AU1000_GPIO_12,
757 AU1000_GPIO_13,
758 AU1000_GPIO_14,
759 AU1000_GPIO_15,
760 AU1000_GPIO_16,
761 AU1000_GPIO_17,
762 AU1000_GPIO_18,
763 AU1000_GPIO_19,
764 AU1000_GPIO_20,
765 AU1000_GPIO_21,
766 AU1000_GPIO_22,
767 AU1000_GPIO_23,
768 AU1000_GPIO_24,
769 AU1000_GPIO_25,
770 AU1000_GPIO_26,
771 AU1000_GPIO_27,
772 AU1000_GPIO_28,
773 AU1000_GPIO_29,
774 AU1000_GPIO_30,
775 AU1000_GPIO_31,
776};
777 951
778#define UART0_ADDR 0xB1100000 952#define UART0_ADDR 0xB1100000
779#define UART1_ADDR 0xB1200000
780#define UART3_ADDR 0xB1400000 953#define UART3_ADDR 0xB1400000
781 954
782#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 955#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
783#define USB_HOST_CONFIG 0xB017FFFC 956#define USB_HOST_CONFIG 0xB017FFFC
957#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
784 958
785#define AU1100_ETH0_BASE 0xB0500000 959#define AU1100_ETH0_BASE 0xB0500000
786#define AU1100_MAC0_ENABLE 0xB0520000 960#define AU1100_MAC0_ENABLE 0xB0520000
@@ -788,87 +962,12 @@ enum soc_au1100_ints {
788#endif /* CONFIG_SOC_AU1100 */ 962#endif /* CONFIG_SOC_AU1100 */
789 963
790#ifdef CONFIG_SOC_AU1550 964#ifdef CONFIG_SOC_AU1550
791enum soc_au1550_ints {
792 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
793 AU1550_UART0_INT = AU1550_FIRST_INT,
794 AU1550_PCI_INTA,
795 AU1550_PCI_INTB,
796 AU1550_DDMA_INT,
797 AU1550_CRYPTO_INT,
798 AU1550_PCI_INTC,
799 AU1550_PCI_INTD,
800 AU1550_PCI_RST_INT,
801 AU1550_UART1_INT,
802 AU1550_UART3_INT,
803 AU1550_PSC0_INT,
804 AU1550_PSC1_INT,
805 AU1550_PSC2_INT,
806 AU1550_PSC3_INT,
807 AU1000_TOY_INT,
808 AU1000_TOY_MATCH0_INT,
809 AU1000_TOY_MATCH1_INT,
810 AU1000_TOY_MATCH2_INT,
811 AU1000_RTC_INT,
812 AU1000_RTC_MATCH0_INT,
813 AU1000_RTC_MATCH1_INT,
814 AU1000_RTC_MATCH2_INT,
815
816 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
817 AU1550_USB_DEV_REQ_INT,
818 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
819 AU1550_USB_DEV_SUS_INT,
820 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
821 AU1550_USB_HOST_INT,
822 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
823 AU1550_MAC0_DMA_INT,
824 AU1550_MAC1_DMA_INT,
825 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
826 AU1000_GPIO_1,
827 AU1000_GPIO_2,
828 AU1000_GPIO_3,
829 AU1000_GPIO_4,
830 AU1000_GPIO_5,
831 AU1000_GPIO_6,
832 AU1000_GPIO_7,
833 AU1000_GPIO_8,
834 AU1000_GPIO_9,
835 AU1000_GPIO_10,
836 AU1000_GPIO_11,
837 AU1000_GPIO_12,
838 AU1000_GPIO_13,
839 AU1000_GPIO_14,
840 AU1000_GPIO_15,
841 AU1550_GPIO_200,
842 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
843 AU1500_GPIO_16,
844 AU1500_GPIO_17,
845 AU1500_GPIO_20,
846 AU1500_GPIO_21,
847 AU1500_GPIO_22,
848 AU1500_GPIO_23,
849 AU1500_GPIO_24,
850 AU1500_GPIO_25,
851 AU1500_GPIO_26,
852 AU1500_GPIO_27,
853 AU1500_GPIO_28,
854 AU1500_GPIO_206,
855 AU1500_GPIO_207,
856 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
857};
858
859/* shortcuts */
860#define INTA AU1550_PCI_INTA
861#define INTB AU1550_PCI_INTB
862#define INTC AU1550_PCI_INTC
863#define INTD AU1550_PCI_INTD
864
865#define UART0_ADDR 0xB1100000 965#define UART0_ADDR 0xB1100000
866#define UART1_ADDR 0xB1200000
867#define UART3_ADDR 0xB1400000
868 966
869#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ 967#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
870#define USB_OHCI_LEN 0x00060000 968#define USB_OHCI_LEN 0x00060000
871#define USB_HOST_CONFIG 0xB4027ffc 969#define USB_HOST_CONFIG 0xB4027ffc
970#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
872 971
873#define AU1550_ETH0_BASE 0xB0500000 972#define AU1550_ETH0_BASE 0xB0500000
874#define AU1550_ETH1_BASE 0xB0510000 973#define AU1550_ETH1_BASE 0xB0510000
@@ -877,78 +976,10 @@ enum soc_au1550_ints {
877#define NUM_ETH_INTERFACES 2 976#define NUM_ETH_INTERFACES 2
878#endif /* CONFIG_SOC_AU1550 */ 977#endif /* CONFIG_SOC_AU1550 */
879 978
979
880#ifdef CONFIG_SOC_AU1200 980#ifdef CONFIG_SOC_AU1200
881enum soc_au1200_ints {
882 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
883 AU1200_UART0_INT = AU1200_FIRST_INT,
884 AU1200_SWT_INT,
885 AU1200_SD_INT,
886 AU1200_DDMA_INT,
887 AU1200_MAE_BE_INT,
888 AU1200_GPIO_200,
889 AU1200_GPIO_201,
890 AU1200_GPIO_202,
891 AU1200_UART1_INT,
892 AU1200_MAE_FE_INT,
893 AU1200_PSC0_INT,
894 AU1200_PSC1_INT,
895 AU1200_AES_INT,
896 AU1200_CAMERA_INT,
897 AU1000_TOY_INT,
898 AU1000_TOY_MATCH0_INT,
899 AU1000_TOY_MATCH1_INT,
900 AU1000_TOY_MATCH2_INT,
901 AU1000_RTC_INT,
902 AU1000_RTC_MATCH0_INT,
903 AU1000_RTC_MATCH1_INT,
904 AU1000_RTC_MATCH2_INT,
905 AU1200_GPIO_203,
906 AU1200_NAND_INT,
907 AU1200_GPIO_204,
908 AU1200_GPIO_205,
909 AU1200_GPIO_206,
910 AU1200_GPIO_207,
911 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
912 AU1200_USB_INT,
913 AU1000_USB_HOST_INT = AU1200_USB_INT,
914 AU1200_LCD_INT,
915 AU1200_MAE_BOTH_INT,
916 AU1000_GPIO_0,
917 AU1000_GPIO_1,
918 AU1000_GPIO_2,
919 AU1000_GPIO_3,
920 AU1000_GPIO_4,
921 AU1000_GPIO_5,
922 AU1000_GPIO_6,
923 AU1000_GPIO_7,
924 AU1000_GPIO_8,
925 AU1000_GPIO_9,
926 AU1000_GPIO_10,
927 AU1000_GPIO_11,
928 AU1000_GPIO_12,
929 AU1000_GPIO_13,
930 AU1000_GPIO_14,
931 AU1000_GPIO_15,
932 AU1000_GPIO_16,
933 AU1000_GPIO_17,
934 AU1000_GPIO_18,
935 AU1000_GPIO_19,
936 AU1000_GPIO_20,
937 AU1000_GPIO_21,
938 AU1000_GPIO_22,
939 AU1000_GPIO_23,
940 AU1000_GPIO_24,
941 AU1000_GPIO_25,
942 AU1000_GPIO_26,
943 AU1000_GPIO_27,
944 AU1000_GPIO_28,
945 AU1000_GPIO_29,
946 AU1000_GPIO_30,
947 AU1000_GPIO_31,
948};
949 981
950#define UART0_ADDR 0xB1100000 982#define UART0_ADDR 0xB1100000
951#define UART1_ADDR 0xB1200000
952 983
953#define USB_UOC_BASE 0x14020020 984#define USB_UOC_BASE 0x14020020
954#define USB_UOC_LEN 0x20 985#define USB_UOC_LEN 0x20
@@ -974,15 +1005,9 @@ enum soc_au1200_ints {
974#define USBMSRMCFG_RDCOMB 30 1005#define USBMSRMCFG_RDCOMB 30
975#define USBMSRMCFG_PFEN 31 1006#define USBMSRMCFG_PFEN 31
976 1007
977#endif /* CONFIG_SOC_AU1200 */ 1008#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
978
979#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
980#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
981#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
982#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
983 1009
984#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 1010#endif /* CONFIG_SOC_AU1200 */
985#define INTX 0xFF /* not valid */
986 1011
987/* Programmable Counters 0 and 1 */ 1012/* Programmable Counters 0 and 1 */
988#define SYS_BASE 0xB1900000 1013#define SYS_BASE 0xB1900000
@@ -1231,14 +1256,6 @@ enum soc_au1200_ints {
1231#define MAC_RX_BUFF3_STATUS 0x30 1256#define MAC_RX_BUFF3_STATUS 0x30
1232#define MAC_RX_BUFF3_ADDR 0x34 1257#define MAC_RX_BUFF3_ADDR 0x34
1233 1258
1234/* UARTS 0-3 */
1235#define UART_BASE UART0_ADDR
1236#ifdef CONFIG_SOC_AU1200
1237#define UART_DEBUG_BASE UART1_ADDR
1238#else
1239#define UART_DEBUG_BASE UART3_ADDR
1240#endif
1241
1242#define UART_RX 0 /* Receive buffer */ 1259#define UART_RX 0 /* Receive buffer */
1243#define UART_TX 4 /* Transmit buffer */ 1260#define UART_TX 4 /* Transmit buffer */
1244#define UART_IER 8 /* Interrupt Enable Register */ 1261#define UART_IER 8 /* Interrupt Enable Register */
@@ -1251,84 +1268,6 @@ enum soc_au1200_ints {
1251#define UART_CLK 0x28 /* Baud Rate Clock Divider */ 1268#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1252#define UART_MOD_CNTRL 0x100 /* Module Control */ 1269#define UART_MOD_CNTRL 0x100 /* Module Control */
1253 1270
1254#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1255#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1256#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1257#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1258#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1259#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1260#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1261#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1262#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1263#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1264#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1265#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1266#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1267
1268/*
1269 * These are the definitions for the Line Control Register
1270 */
1271#define UART_LCR_SBC 0x40 /* Set break control */
1272#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1273#define UART_LCR_EPAR 0x10 /* Even parity select */
1274#define UART_LCR_PARITY 0x08 /* Parity Enable */
1275#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1276#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1277#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1278#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1279#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1280
1281/*
1282 * These are the definitions for the Line Status Register
1283 */
1284#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1285#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1286#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1287#define UART_LSR_FE 0x08 /* Frame error indicator */
1288#define UART_LSR_PE 0x04 /* Parity error indicator */
1289#define UART_LSR_OE 0x02 /* Overrun error indicator */
1290#define UART_LSR_DR 0x01 /* Receiver data ready */
1291
1292/*
1293 * These are the definitions for the Interrupt Identification Register
1294 */
1295#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1296#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1297#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1298#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1299#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1300#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1301
1302/*
1303 * These are the definitions for the Interrupt Enable Register
1304 */
1305#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1306#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1307#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1308#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1309
1310/*
1311 * These are the definitions for the Modem Control Register
1312 */
1313#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1314#define UART_MCR_OUT2 0x08 /* Out2 complement */
1315#define UART_MCR_OUT1 0x04 /* Out1 complement */
1316#define UART_MCR_RTS 0x02 /* RTS complement */
1317#define UART_MCR_DTR 0x01 /* DTR complement */
1318
1319/*
1320 * These are the definitions for the Modem Status Register
1321 */
1322#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1323#define UART_MSR_RI 0x40 /* Ring Indicator */
1324#define UART_MSR_DSR 0x20 /* Data Set Ready */
1325#define UART_MSR_CTS 0x10 /* Clear to Send */
1326#define UART_MSR_DDCD 0x08 /* Delta DCD */
1327#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1328#define UART_MSR_DDSR 0x02 /* Delta DSR */
1329#define UART_MSR_DCTS 0x01 /* Delta CTS */
1330#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1331
1332/* SSIO */ 1271/* SSIO */
1333#define SSI0_STATUS 0xB1600000 1272#define SSI0_STATUS 0xB1600000
1334# define SSI_STATUS_BF (1 << 4) 1273# define SSI_STATUS_BF (1 << 4)
@@ -1720,7 +1659,7 @@ enum soc_au1200_ints {
1720#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1659#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1721#define IOPORT_RESOURCE_END 0xffffffff 1660#define IOPORT_RESOURCE_END 0xffffffff
1722#define IOMEM_RESOURCE_START 0x10000000 1661#define IOMEM_RESOURCE_START 0x10000000
1723#define IOMEM_RESOURCE_END 0xffffffff 1662#define IOMEM_RESOURCE_END 0xfffffffffULL
1724 1663
1725#else /* Au1000 and Au1100 and Au1200 */ 1664#else /* Au1000 and Au1100 and Au1200 */
1726 1665
@@ -1728,7 +1667,7 @@ enum soc_au1200_ints {
1728#define IOPORT_RESOURCE_START 0x10000000 1667#define IOPORT_RESOURCE_START 0x10000000
1729#define IOPORT_RESOURCE_END 0xffffffff 1668#define IOPORT_RESOURCE_END 0xffffffff
1730#define IOMEM_RESOURCE_START 0x10000000 1669#define IOMEM_RESOURCE_START 0x10000000
1731#define IOMEM_RESOURCE_END 0xffffffff 1670#define IOMEM_RESOURCE_END 0xfffffffffULL
1732 1671
1733#define PCI_IO_START 0 1672#define PCI_IO_START 0
1734#define PCI_IO_END 0 1673#define PCI_IO_END 0
@@ -1739,53 +1678,4 @@ enum soc_au1200_ints {
1739 1678
1740#endif 1679#endif
1741 1680
1742#ifndef _LANGUAGE_ASSEMBLY
1743typedef volatile struct {
1744 /* 0x0000 */ u32 toytrim;
1745 /* 0x0004 */ u32 toywrite;
1746 /* 0x0008 */ u32 toymatch0;
1747 /* 0x000C */ u32 toymatch1;
1748 /* 0x0010 */ u32 toymatch2;
1749 /* 0x0014 */ u32 cntrctrl;
1750 /* 0x0018 */ u32 scratch0;
1751 /* 0x001C */ u32 scratch1;
1752 /* 0x0020 */ u32 freqctrl0;
1753 /* 0x0024 */ u32 freqctrl1;
1754 /* 0x0028 */ u32 clksrc;
1755 /* 0x002C */ u32 pinfunc;
1756 /* 0x0030 */ u32 reserved0;
1757 /* 0x0034 */ u32 wakemsk;
1758 /* 0x0038 */ u32 endian;
1759 /* 0x003C */ u32 powerctrl;
1760 /* 0x0040 */ u32 toyread;
1761 /* 0x0044 */ u32 rtctrim;
1762 /* 0x0048 */ u32 rtcwrite;
1763 /* 0x004C */ u32 rtcmatch0;
1764 /* 0x0050 */ u32 rtcmatch1;
1765 /* 0x0054 */ u32 rtcmatch2;
1766 /* 0x0058 */ u32 rtcread;
1767 /* 0x005C */ u32 wakesrc;
1768 /* 0x0060 */ u32 cpupll;
1769 /* 0x0064 */ u32 auxpll;
1770 /* 0x0068 */ u32 reserved1;
1771 /* 0x006C */ u32 reserved2;
1772 /* 0x0070 */ u32 reserved3;
1773 /* 0x0074 */ u32 reserved4;
1774 /* 0x0078 */ u32 slppwr;
1775 /* 0x007C */ u32 sleep;
1776 /* 0x0080 */ u32 reserved5[32];
1777 /* 0x0100 */ u32 trioutrd;
1778#define trioutclr trioutrd
1779 /* 0x0104 */ u32 reserved6;
1780 /* 0x0108 */ u32 outputrd;
1781#define outputset outputrd
1782 /* 0x010C */ u32 outputclr;
1783 /* 0x0110 */ u32 pinstaterd;
1784#define pininputen pinstaterd
1785} AU1X00_SYS;
1786
1787static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1788
1789#endif
1790
1791#endif 1681#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index c35e20918490..94000a3b6f0b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -46,6 +46,7 @@ struct au1xmmc_platform_data {
46 int(*card_readonly)(void *mmc_host); 46 int(*card_readonly)(void *mmc_host);
47 void(*set_power)(void *mmc_host, int state); 47 void(*set_power)(void *mmc_host, int state);
48 struct led_classdev *led; 48 struct led_classdev *led;
49 unsigned long mask_host_caps;
49}; 50};
50 51
51#define SD0_BASE 0xB0600000 52#define SD0_BASE 0xB0600000
@@ -205,4 +206,3 @@ struct au1xmmc_platform_data {
205 206
206 207
207#endif /* __ASM_AU1100_MMC_H */ 208#endif /* __ASM_AU1100_MMC_H */
208
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 06f68f43800a..8c6b1105ce0b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -305,6 +305,7 @@ typedef struct dbdma_chan_config {
305 dbdev_tab_t *chan_dest; 305 dbdev_tab_t *chan_dest;
306 au1x_dma_chan_t *chan_ptr; 306 au1x_dma_chan_t *chan_ptr;
307 au1x_ddma_desc_t *chan_desc_base; 307 au1x_ddma_desc_t *chan_desc_base;
308 u32 cdb_membase; /* kmalloc base of above */
308 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; 309 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
309 void *chan_callparam; 310 void *chan_callparam;
310 void (*chan_callback)(int, void *); 311 void (*chan_callback)(int, void *);
@@ -338,8 +339,8 @@ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
338u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); 339u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
339 340
340/* Put buffers on source/destination descriptors. */ 341/* Put buffers on source/destination descriptors. */
341u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); 342u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
342u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); 343u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
343 344
344/* Get a buffer from the destination descriptor. */ 345/* Get a buffer from the destination descriptor. */
345u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); 346u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
@@ -362,25 +363,6 @@ void au1xxx_dbdma_suspend(void);
362void au1xxx_dbdma_resume(void); 363void au1xxx_dbdma_resume(void);
363#endif 364#endif
364 365
365
366/*
367 * Some compatibilty macros -- needed to make changes to API
368 * without breaking existing drivers.
369 */
370#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
371 _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
372#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
373 _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
374#define put_source_flags(chanid, buf, nbytes, flags) \
375 au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
376
377#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
378 _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
379#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
380 _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
381#define put_dest_flags(chanid, buf, nbytes, flags) \
382 au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
383
384/* 366/*
385 * Flags for the put_source/put_dest functions. 367 * Flags for the put_source/put_dest functions.
386 */ 368 */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
new file mode 100644
index 000000000000..bae9b758fcde
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
@@ -0,0 +1,17 @@
1#ifndef __AU1X00_ETH_DATA_H
2#define __AU1X00_ETH_DATA_H
3
4/* Platform specific PHY configuration passed to the MAC driver */
5struct au1000_eth_platform_data {
6 int phy_static_config;
7 int phy_search_highest_addr;
8 int phy1_search_mac0;
9 int phy_addr;
10 int phy_busid;
11 int phy_irq;
12};
13
14void __init au1xxx_override_eth_cfg(unsigned port,
15 struct au1000_eth_platform_data *eth_data);
16
17#endif /* __AU1X00_ETH_DATA_H */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 91595fa89034..62d2f136d941 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -35,15 +35,13 @@ static inline int au1000_gpio2_to_irq(int gpio)
35 return -ENXIO; 35 return -ENXIO;
36} 36}
37 37
38#ifdef CONFIG_SOC_AU1000
39static inline int au1000_irq_to_gpio(int irq) 38static inline int au1000_irq_to_gpio(int irq)
40{ 39{
41 if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31)) 40 if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
42 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 41 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
43 42
44 return -ENXIO; 43 return -ENXIO;
45} 44}
46#endif
47 45
48static inline int au1500_gpio1_to_irq(int gpio) 46static inline int au1500_gpio1_to_irq(int gpio)
49{ 47{
@@ -71,27 +69,25 @@ static inline int au1500_gpio2_to_irq(int gpio)
71 return -ENXIO; 69 return -ENXIO;
72} 70}
73 71
74#ifdef CONFIG_SOC_AU1500
75static inline int au1500_irq_to_gpio(int irq) 72static inline int au1500_irq_to_gpio(int irq)
76{ 73{
77 switch (irq) { 74 switch (irq) {
78 case AU1000_GPIO_0 ... AU1000_GPIO_15: 75 case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
79 case AU1500_GPIO_20: 76 case AU1500_GPIO20_INT:
80 case AU1500_GPIO_23 ... AU1500_GPIO_28: 77 case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
81 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 78 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
82 case AU1500_GPIO_200 ... AU1500_GPIO_203: 79 case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
83 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0; 80 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
84 case AU1500_GPIO_204 ... AU1500_GPIO_205: 81 case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
85 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4; 82 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
86 case AU1500_GPIO_206 ... AU1500_GPIO_207: 83 case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
87 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; 84 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
88 case AU1500_GPIO_208_215: 85 case AU1500_GPIO208_215_INT:
89 return ALCHEMY_GPIO2_BASE + 8; 86 return ALCHEMY_GPIO2_BASE + 8;
90 } 87 }
91 88
92 return -ENXIO; 89 return -ENXIO;
93} 90}
94#endif
95 91
96static inline int au1100_gpio1_to_irq(int gpio) 92static inline int au1100_gpio1_to_irq(int gpio)
97{ 93{
@@ -108,19 +104,17 @@ static inline int au1100_gpio2_to_irq(int gpio)
108 return -ENXIO; 104 return -ENXIO;
109} 105}
110 106
111#ifdef CONFIG_SOC_AU1100
112static inline int au1100_irq_to_gpio(int irq) 107static inline int au1100_irq_to_gpio(int irq)
113{ 108{
114 switch (irq) { 109 switch (irq) {
115 case AU1000_GPIO_0 ... AU1000_GPIO_31: 110 case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
116 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 111 return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
117 case AU1100_GPIO_208_215: 112 case AU1100_GPIO208_215_INT:
118 return ALCHEMY_GPIO2_BASE + 8; 113 return ALCHEMY_GPIO2_BASE + 8;
119 } 114 }
120 115
121 return -ENXIO; 116 return -ENXIO;
122} 117}
123#endif
124 118
125static inline int au1550_gpio1_to_irq(int gpio) 119static inline int au1550_gpio1_to_irq(int gpio)
126{ 120{
@@ -149,24 +143,22 @@ static inline int au1550_gpio2_to_irq(int gpio)
149 return -ENXIO; 143 return -ENXIO;
150} 144}
151 145
152#ifdef CONFIG_SOC_AU1550
153static inline int au1550_irq_to_gpio(int irq) 146static inline int au1550_irq_to_gpio(int irq)
154{ 147{
155 switch (irq) { 148 switch (irq) {
156 case AU1000_GPIO_0 ... AU1000_GPIO_15: 149 case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
157 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 150 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
158 case AU1550_GPIO_200: 151 case AU1550_GPIO200_INT:
159 case AU1500_GPIO_201_205: 152 case AU1550_GPIO201_205_INT:
160 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0; 153 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
161 case AU1500_GPIO_16 ... AU1500_GPIO_28: 154 case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
162 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16; 155 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
163 case AU1500_GPIO_206 ... AU1500_GPIO_208_218: 156 case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
164 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; 157 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
165 } 158 }
166 159
167 return -ENXIO; 160 return -ENXIO;
168} 161}
169#endif
170 162
171static inline int au1200_gpio1_to_irq(int gpio) 163static inline int au1200_gpio1_to_irq(int gpio)
172{ 164{
@@ -187,23 +179,21 @@ static inline int au1200_gpio2_to_irq(int gpio)
187 return -ENXIO; 179 return -ENXIO;
188} 180}
189 181
190#ifdef CONFIG_SOC_AU1200
191static inline int au1200_irq_to_gpio(int irq) 182static inline int au1200_irq_to_gpio(int irq)
192{ 183{
193 switch (irq) { 184 switch (irq) {
194 case AU1000_GPIO_0 ... AU1000_GPIO_31: 185 case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
195 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 186 return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
196 case AU1200_GPIO_200 ... AU1200_GPIO_202: 187 case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
197 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0; 188 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
198 case AU1200_GPIO_203: 189 case AU1200_GPIO203_INT:
199 return ALCHEMY_GPIO2_BASE + 3; 190 return ALCHEMY_GPIO2_BASE + 3;
200 case AU1200_GPIO_204 ... AU1200_GPIO_208_215: 191 case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
201 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4; 192 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
202 } 193 }
203 194
204 return -ENXIO; 195 return -ENXIO;
205} 196}
206#endif
207 197
208/* 198/*
209 * GPIO1 block macros for common linux gpio functions. 199 * GPIO1 block macros for common linux gpio functions.
@@ -246,19 +236,19 @@ static inline int alchemy_gpio1_is_valid(int gpio)
246 236
247static inline int alchemy_gpio1_to_irq(int gpio) 237static inline int alchemy_gpio1_to_irq(int gpio)
248{ 238{
249#if defined(CONFIG_SOC_AU1000) 239 switch (alchemy_get_cputype()) {
250 return au1000_gpio1_to_irq(gpio); 240 case ALCHEMY_CPU_AU1000:
251#elif defined(CONFIG_SOC_AU1100) 241 return au1000_gpio1_to_irq(gpio);
252 return au1100_gpio1_to_irq(gpio); 242 case ALCHEMY_CPU_AU1100:
253#elif defined(CONFIG_SOC_AU1500) 243 return au1100_gpio1_to_irq(gpio);
254 return au1500_gpio1_to_irq(gpio); 244 case ALCHEMY_CPU_AU1500:
255#elif defined(CONFIG_SOC_AU1550) 245 return au1500_gpio1_to_irq(gpio);
256 return au1550_gpio1_to_irq(gpio); 246 case ALCHEMY_CPU_AU1550:
257#elif defined(CONFIG_SOC_AU1200) 247 return au1550_gpio1_to_irq(gpio);
258 return au1200_gpio1_to_irq(gpio); 248 case ALCHEMY_CPU_AU1200:
259#else 249 return au1200_gpio1_to_irq(gpio);
250 }
260 return -ENXIO; 251 return -ENXIO;
261#endif
262} 252}
263 253
264/* 254/*
@@ -316,19 +306,19 @@ static inline int alchemy_gpio2_is_valid(int gpio)
316 306
317static inline int alchemy_gpio2_to_irq(int gpio) 307static inline int alchemy_gpio2_to_irq(int gpio)
318{ 308{
319#if defined(CONFIG_SOC_AU1000) 309 switch (alchemy_get_cputype()) {
320 return au1000_gpio2_to_irq(gpio); 310 case ALCHEMY_CPU_AU1000:
321#elif defined(CONFIG_SOC_AU1100) 311 return au1000_gpio2_to_irq(gpio);
322 return au1100_gpio2_to_irq(gpio); 312 case ALCHEMY_CPU_AU1100:
323#elif defined(CONFIG_SOC_AU1500) 313 return au1100_gpio2_to_irq(gpio);
324 return au1500_gpio2_to_irq(gpio); 314 case ALCHEMY_CPU_AU1500:
325#elif defined(CONFIG_SOC_AU1550) 315 return au1500_gpio2_to_irq(gpio);
326 return au1550_gpio2_to_irq(gpio); 316 case ALCHEMY_CPU_AU1550:
327#elif defined(CONFIG_SOC_AU1200) 317 return au1550_gpio2_to_irq(gpio);
328 return au1200_gpio2_to_irq(gpio); 318 case ALCHEMY_CPU_AU1200:
329#else 319 return au1200_gpio2_to_irq(gpio);
320 }
330 return -ENXIO; 321 return -ENXIO;
331#endif
332} 322}
333 323
334/**********************************************************************/ 324/**********************************************************************/
@@ -384,10 +374,13 @@ static inline void alchemy_gpio2_enable_int(int gpio2)
384 374
385 gpio2 -= ALCHEMY_GPIO2_BASE; 375 gpio2 -= ALCHEMY_GPIO2_BASE;
386 376
387#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
388 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ 377 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
389 gpio2 -= 8; 378 switch (alchemy_get_cputype()) {
390#endif 379 case ALCHEMY_CPU_AU1100:
380 case ALCHEMY_CPU_AU1500:
381 gpio2 -= 8;
382 }
383
391 local_irq_save(flags); 384 local_irq_save(flags);
392 __alchemy_gpio2_mod_int(gpio2, 1); 385 __alchemy_gpio2_mod_int(gpio2, 1);
393 local_irq_restore(flags); 386 local_irq_restore(flags);
@@ -405,10 +398,13 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
405 398
406 gpio2 -= ALCHEMY_GPIO2_BASE; 399 gpio2 -= ALCHEMY_GPIO2_BASE;
407 400
408#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
409 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ 401 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
410 gpio2 -= 8; 402 switch (alchemy_get_cputype()) {
411#endif 403 case ALCHEMY_CPU_AU1100:
404 case ALCHEMY_CPU_AU1500:
405 gpio2 -= 8;
406 }
407
412 local_irq_save(flags); 408 local_irq_save(flags);
413 __alchemy_gpio2_mod_int(gpio2, 0); 409 __alchemy_gpio2_mod_int(gpio2, 0);
414 local_irq_restore(flags); 410 local_irq_restore(flags);
@@ -494,19 +490,19 @@ static inline int alchemy_gpio_to_irq(int gpio)
494 490
495static inline int alchemy_irq_to_gpio(int irq) 491static inline int alchemy_irq_to_gpio(int irq)
496{ 492{
497#if defined(CONFIG_SOC_AU1000) 493 switch (alchemy_get_cputype()) {
498 return au1000_irq_to_gpio(irq); 494 case ALCHEMY_CPU_AU1000:
499#elif defined(CONFIG_SOC_AU1100) 495 return au1000_irq_to_gpio(irq);
500 return au1100_irq_to_gpio(irq); 496 case ALCHEMY_CPU_AU1100:
501#elif defined(CONFIG_SOC_AU1500) 497 return au1100_irq_to_gpio(irq);
502 return au1500_irq_to_gpio(irq); 498 case ALCHEMY_CPU_AU1500:
503#elif defined(CONFIG_SOC_AU1550) 499 return au1500_irq_to_gpio(irq);
504 return au1550_irq_to_gpio(irq); 500 case ALCHEMY_CPU_AU1550:
505#elif defined(CONFIG_SOC_AU1200) 501 return au1550_irq_to_gpio(irq);
506 return au1200_irq_to_gpio(irq); 502 case ALCHEMY_CPU_AU1200:
507#else 503 return au1200_irq_to_gpio(irq);
504 }
508 return -ENXIO; 505 return -ENXIO;
509#endif
510} 506}
511 507
512/**********************************************************************/ 508/**********************************************************************/
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index f9b7d41c659a..c3f60cdc3203 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,7 +1,7 @@
1#ifndef _ALCHEMY_GPIO_H_ 1#ifndef _ALCHEMY_GPIO_H_
2#define _ALCHEMY_GPIO_H_ 2#define _ALCHEMY_GPIO_H_
3 3
4#if defined(CONFIG_ALCHEMY_GPIO_AU1000) 4#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000)
5 5
6#include <asm/mach-au1x00/gpio-au1000.h> 6#include <asm/mach-au1x00/gpio-au1000.h>
7 7
diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h
index 364cea2dc71f..75a94ad3ac91 100644
--- a/arch/mips/include/asm/mach-au1x00/ioremap.h
+++ b/arch/mips/include/asm/mach-au1x00/ioremap.h
@@ -11,7 +11,7 @@
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13 13
14#ifdef CONFIG_64BIT_PHYS_ADDR 14#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)
15extern phys_t __fixup_bigphys_addr(phys_t, phys_t); 15extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
16#else 16#else
17static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 17static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h
index e38715577c51..4c0e09cf1735 100644
--- a/arch/mips/include/asm/mach-au1x00/prom.h
+++ b/arch/mips/include/asm/mach-au1x00/prom.h
@@ -6,7 +6,6 @@ extern char **prom_argv;
6extern char **prom_envp; 6extern char **prom_envp;
7 7
8extern void prom_init_cmdline(void); 8extern void prom_init_cmdline(void);
9extern char *prom_getcmdline(void);
10extern char *prom_getenv(char *envname); 9extern char *prom_getenv(char *envname);
11extern int prom_get_ethernet_addr(char *ethernet_addr); 10extern int prom_get_ethernet_addr(char *ethernet_addr);
12 11
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index b12c4aca2cc9..96a2391ad85b 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -85,6 +85,7 @@ enum bcm63xx_regs_set {
85 RSET_TIMER, 85 RSET_TIMER,
86 RSET_WDT, 86 RSET_WDT,
87 RSET_UART0, 87 RSET_UART0,
88 RSET_UART1,
88 RSET_GPIO, 89 RSET_GPIO,
89 RSET_SPI, 90 RSET_SPI,
90 RSET_UDC0, 91 RSET_UDC0,
@@ -123,6 +124,7 @@ enum bcm63xx_regs_set {
123#define BCM_6338_TIMER_BASE (0xfffe0200) 124#define BCM_6338_TIMER_BASE (0xfffe0200)
124#define BCM_6338_WDT_BASE (0xfffe021c) 125#define BCM_6338_WDT_BASE (0xfffe021c)
125#define BCM_6338_UART0_BASE (0xfffe0300) 126#define BCM_6338_UART0_BASE (0xfffe0300)
127#define BCM_6338_UART1_BASE (0xdeadbeef)
126#define BCM_6338_GPIO_BASE (0xfffe0400) 128#define BCM_6338_GPIO_BASE (0xfffe0400)
127#define BCM_6338_SPI_BASE (0xfffe0c00) 129#define BCM_6338_SPI_BASE (0xfffe0c00)
128#define BCM_6338_UDC0_BASE (0xdeadbeef) 130#define BCM_6338_UDC0_BASE (0xdeadbeef)
@@ -153,6 +155,7 @@ enum bcm63xx_regs_set {
153#define BCM_6345_TIMER_BASE (0xfffe0200) 155#define BCM_6345_TIMER_BASE (0xfffe0200)
154#define BCM_6345_WDT_BASE (0xfffe021c) 156#define BCM_6345_WDT_BASE (0xfffe021c)
155#define BCM_6345_UART0_BASE (0xfffe0300) 157#define BCM_6345_UART0_BASE (0xfffe0300)
158#define BCM_6345_UART1_BASE (0xdeadbeef)
156#define BCM_6345_GPIO_BASE (0xfffe0400) 159#define BCM_6345_GPIO_BASE (0xfffe0400)
157#define BCM_6345_SPI_BASE (0xdeadbeef) 160#define BCM_6345_SPI_BASE (0xdeadbeef)
158#define BCM_6345_UDC0_BASE (0xdeadbeef) 161#define BCM_6345_UDC0_BASE (0xdeadbeef)
@@ -182,6 +185,7 @@ enum bcm63xx_regs_set {
182#define BCM_6348_TIMER_BASE (0xfffe0200) 185#define BCM_6348_TIMER_BASE (0xfffe0200)
183#define BCM_6348_WDT_BASE (0xfffe021c) 186#define BCM_6348_WDT_BASE (0xfffe021c)
184#define BCM_6348_UART0_BASE (0xfffe0300) 187#define BCM_6348_UART0_BASE (0xfffe0300)
188#define BCM_6348_UART1_BASE (0xdeadbeef)
185#define BCM_6348_GPIO_BASE (0xfffe0400) 189#define BCM_6348_GPIO_BASE (0xfffe0400)
186#define BCM_6348_SPI_BASE (0xfffe0c00) 190#define BCM_6348_SPI_BASE (0xfffe0c00)
187#define BCM_6348_UDC0_BASE (0xfffe1000) 191#define BCM_6348_UDC0_BASE (0xfffe1000)
@@ -208,6 +212,7 @@ enum bcm63xx_regs_set {
208#define BCM_6358_TIMER_BASE (0xfffe0040) 212#define BCM_6358_TIMER_BASE (0xfffe0040)
209#define BCM_6358_WDT_BASE (0xfffe005c) 213#define BCM_6358_WDT_BASE (0xfffe005c)
210#define BCM_6358_UART0_BASE (0xfffe0100) 214#define BCM_6358_UART0_BASE (0xfffe0100)
215#define BCM_6358_UART1_BASE (0xfffe0120)
211#define BCM_6358_GPIO_BASE (0xfffe0080) 216#define BCM_6358_GPIO_BASE (0xfffe0080)
212#define BCM_6358_SPI_BASE (0xdeadbeef) 217#define BCM_6358_SPI_BASE (0xdeadbeef)
213#define BCM_6358_UDC0_BASE (0xfffe0800) 218#define BCM_6358_UDC0_BASE (0xfffe0800)
@@ -246,6 +251,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
246 return BCM_6338_WDT_BASE; 251 return BCM_6338_WDT_BASE;
247 case RSET_UART0: 252 case RSET_UART0:
248 return BCM_6338_UART0_BASE; 253 return BCM_6338_UART0_BASE;
254 case RSET_UART1:
255 return BCM_6338_UART1_BASE;
249 case RSET_GPIO: 256 case RSET_GPIO:
250 return BCM_6338_GPIO_BASE; 257 return BCM_6338_GPIO_BASE;
251 case RSET_SPI: 258 case RSET_SPI:
@@ -292,6 +299,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
292 return BCM_6345_WDT_BASE; 299 return BCM_6345_WDT_BASE;
293 case RSET_UART0: 300 case RSET_UART0:
294 return BCM_6345_UART0_BASE; 301 return BCM_6345_UART0_BASE;
302 case RSET_UART1:
303 return BCM_6345_UART1_BASE;
295 case RSET_GPIO: 304 case RSET_GPIO:
296 return BCM_6345_GPIO_BASE; 305 return BCM_6345_GPIO_BASE;
297 case RSET_SPI: 306 case RSET_SPI:
@@ -338,6 +347,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
338 return BCM_6348_WDT_BASE; 347 return BCM_6348_WDT_BASE;
339 case RSET_UART0: 348 case RSET_UART0:
340 return BCM_6348_UART0_BASE; 349 return BCM_6348_UART0_BASE;
350 case RSET_UART1:
351 return BCM_6348_UART1_BASE;
341 case RSET_GPIO: 352 case RSET_GPIO:
342 return BCM_6348_GPIO_BASE; 353 return BCM_6348_GPIO_BASE;
343 case RSET_SPI: 354 case RSET_SPI:
@@ -384,6 +395,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
384 return BCM_6358_WDT_BASE; 395 return BCM_6358_WDT_BASE;
385 case RSET_UART0: 396 case RSET_UART0:
386 return BCM_6358_UART0_BASE; 397 return BCM_6358_UART0_BASE;
398 case RSET_UART1:
399 return BCM_6358_UART1_BASE;
387 case RSET_GPIO: 400 case RSET_GPIO:
388 return BCM_6358_GPIO_BASE; 401 return BCM_6358_GPIO_BASE;
389 case RSET_SPI: 402 case RSET_SPI:
@@ -429,6 +442,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
429enum bcm63xx_irq { 442enum bcm63xx_irq {
430 IRQ_TIMER = 0, 443 IRQ_TIMER = 0,
431 IRQ_UART0, 444 IRQ_UART0,
445 IRQ_UART1,
432 IRQ_DSL, 446 IRQ_DSL,
433 IRQ_ENET0, 447 IRQ_ENET0,
434 IRQ_ENET1, 448 IRQ_ENET1,
@@ -510,6 +524,7 @@ enum bcm63xx_irq {
510 */ 524 */
511#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
512#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
513#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
514#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
515#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
new file mode 100644
index 000000000000..23c705baf171
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
@@ -0,0 +1,6 @@
1#ifndef BCM63XX_DEV_UART_H_
2#define BCM63XX_DEV_UART_H_
3
4int bcm63xx_uart_register(unsigned int id);
5
6#endif /* BCM63XX_DEV_UART_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 76a0b7216af5..43d4da0b1e9f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -10,6 +10,10 @@ static inline unsigned long bcm63xx_gpio_count(void)
10 switch (bcm63xx_get_cpu_id()) { 10 switch (bcm63xx_get_cpu_id()) {
11 case BCM6358_CPU_ID: 11 case BCM6358_CPU_ID:
12 return 40; 12 return 40;
13 case BCM6338_CPU_ID:
14 return 8;
15 case BCM6345_CPU_ID:
16 return 16;
13 case BCM6348_CPU_ID: 17 case BCM6348_CPU_ID:
14 default: 18 default:
15 return 37; 19 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index ed4ccec87dd4..85fd27509aac 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -770,4 +770,3 @@
770#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 770#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
771 771
772#endif /* BCM63XX_REGS_H_ */ 772#endif /* BCM63XX_REGS_H_ */
773
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 6479090a4106..474daaa53497 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -45,6 +45,8 @@ struct board_info {
45 unsigned int has_ohci0:1; 45 unsigned int has_ohci0:1;
46 unsigned int has_ehci0:1; 46 unsigned int has_ehci0:1;
47 unsigned int has_dsp:1; 47 unsigned int has_dsp:1;
48 unsigned int has_uart0:1;
49 unsigned int has_uart1:1;
48 50
49 /* ethernet config */ 51 /* ethernet config */
50 struct bcm63xx_enet_platform_data enet0; 52 struct bcm63xx_enet_platform_data enet0;
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
index 71742bac940d..f453c01d0672 100644
--- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -24,7 +24,7 @@
24#define cpu_has_smartmips 0 24#define cpu_has_smartmips 0
25#define cpu_has_vtag_icache 0 25#define cpu_has_vtag_icache 0
26 26
27#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338) || defined(CONFIG_CPU_IS_BCM6345)) 27#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCM63XX_CPU_6348) || defined(CONFIG_BCM63XX_CPU_6345) || defined(CONFIG_BCM63XX_CPU_6338))
28#define cpu_has_dc_aliases 0 28#define cpu_has_dc_aliases 0
29#endif 29#endif
30 30
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 425e708d4fb9..bbf054042395 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -58,6 +58,9 @@
58#define cpu_has_vint 0 58#define cpu_has_vint 0
59#define cpu_has_veic 0 59#define cpu_has_veic 0
60#define cpu_hwrena_impl_bits 0xc0000000 60#define cpu_hwrena_impl_bits 0xc0000000
61
62#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
63
61#define ARCH_HAS_READ_CURRENT_TIMER 1 64#define ARCH_HAS_READ_CURRENT_TIMER 1
62#define ARCH_HAS_IRQ_PER_CPU 1 65#define ARCH_HAS_IRQ_PER_CPU 1
63#define ARCH_HAS_SPINLOCK_PREFETCH 1 66#define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
new file mode 100644
index 000000000000..618d2de02ed3
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -0,0 +1,238 @@
1/*
2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
3 *
4 * All Alchemy development boards (except, of course, the weird PB1000)
5 * have a few registers in a CPLD with standardised layout; they mostly
6 * only differ in base address and bit meanings in the RESETS and BOARD
7 * registers.
8 *
9 * All data taken from the official AMD board documentation sheets.
10 */
11
12#ifndef _DB1XXX_BCSR_H_
13#define _DB1XXX_BCSR_H_
14
15
16/* BCSR base addresses on various boards. BCSR base 2 refers to the
17 * physical address of the first HEXLEDS register, which is usually
18 * a variable offset from the WHOAMI register.
19 */
20
21/* DB1000, DB1100, DB1500, PB1100, PB1500 */
22#define DB1000_BCSR_PHYS_ADDR 0x0E000000
23#define DB1000_BCSR_HEXLED_OFS 0x01000000
24
25#define DB1550_BCSR_PHYS_ADDR 0x0F000000
26#define DB1550_BCSR_HEXLED_OFS 0x00400000
27
28#define PB1550_BCSR_PHYS_ADDR 0x0F000000
29#define PB1550_BCSR_HEXLED_OFS 0x00800000
30
31#define DB1200_BCSR_PHYS_ADDR 0x19800000
32#define DB1200_BCSR_HEXLED_OFS 0x00400000
33
34#define PB1200_BCSR_PHYS_ADDR 0x0D800000
35#define PB1200_BCSR_HEXLED_OFS 0x00400000
36
37
38enum bcsr_id {
39 /* BCSR base 1 */
40 BCSR_WHOAMI = 0,
41 BCSR_STATUS,
42 BCSR_SWITCHES,
43 BCSR_RESETS,
44 BCSR_PCMCIA,
45 BCSR_BOARD,
46 BCSR_LEDS,
47 BCSR_SYSTEM,
48 /* Au1200/1300 based boards */
49 BCSR_INTCLR,
50 BCSR_INTSET,
51 BCSR_MASKCLR,
52 BCSR_MASKSET,
53 BCSR_SIGSTAT,
54 BCSR_INTSTAT,
55
56 /* BCSR base 2 */
57 BCSR_HEXLEDS,
58 BCSR_RSVD1,
59 BCSR_HEXCLEAR,
60
61 BCSR_CNT,
62};
63
64/* register offsets, valid for all Db1xxx/Pb1xxx boards */
65#define BCSR_REG_WHOAMI 0x00
66#define BCSR_REG_STATUS 0x04
67#define BCSR_REG_SWITCHES 0x08
68#define BCSR_REG_RESETS 0x0c
69#define BCSR_REG_PCMCIA 0x10
70#define BCSR_REG_BOARD 0x14
71#define BCSR_REG_LEDS 0x18
72#define BCSR_REG_SYSTEM 0x1c
73/* Au1200/Au1300 based boards: CPLD IRQ muxer */
74#define BCSR_REG_INTCLR 0x20
75#define BCSR_REG_INTSET 0x24
76#define BCSR_REG_MASKCLR 0x28
77#define BCSR_REG_MASKSET 0x2c
78#define BCSR_REG_SIGSTAT 0x30
79#define BCSR_REG_INTSTAT 0x34
80
81/* hexled control, offset from BCSR base 2 */
82#define BCSR_REG_HEXLEDS 0x00
83#define BCSR_REG_HEXCLEAR 0x08
84
85/*
86 * Register Bits and Pieces.
87 */
88#define BCSR_WHOAMI_DCID(x) ((x) & 0xf)
89#define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf)
90#define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf)
91
92/* register "WHOAMI" bits 11:8 identify the board */
93enum bcsr_whoami_boards {
94 BCSR_WHOAMI_PB1500 = 1,
95 BCSR_WHOAMI_PB1500R2,
96 BCSR_WHOAMI_PB1100,
97 BCSR_WHOAMI_DB1000,
98 BCSR_WHOAMI_DB1100,
99 BCSR_WHOAMI_DB1500,
100 BCSR_WHOAMI_DB1550,
101 BCSR_WHOAMI_PB1550_DDR,
102 BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR,
103 BCSR_WHOAMI_PB1550_SDR,
104 BCSR_WHOAMI_PB1200_DDR1,
105 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
106 BCSR_WHOAMI_PB1200_DDR2,
107 BCSR_WHOAMI_DB1200,
108};
109
110/* STATUS reg. Unless otherwise noted, they're valid on all boards.
111 * PB1200 = DB1200.
112 */
113#define BCSR_STATUS_PC0VS 0x0003
114#define BCSR_STATUS_PC1VS 0x000C
115#define BCSR_STATUS_PC0FI 0x0010
116#define BCSR_STATUS_PC1FI 0x0020
117#define BCSR_STATUS_PB1550_SWAPBOOT 0x0040
118#define BCSR_STATUS_SRAMWIDTH 0x0080
119#define BCSR_STATUS_FLASHBUSY 0x0100
120#define BCSR_STATUS_ROMBUSY 0x0400
121#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */
122#define BCSR_STATUS_SD1WP 0x0800
123#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
124#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
125#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */
126#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */
127#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
128#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
129#define BCSR_STATUS_FLASHDEN 0xC000
130#define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */
131#define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */
132#define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */
133#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
134#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
135
136
137/* DB/PB1000,1100,1500,1550 */
138#define BCSR_RESETS_PHY0 0x0001
139#define BCSR_RESETS_PHY1 0x0002
140#define BCSR_RESETS_DC 0x0004
141#define BCSR_RESETS_FIR_SEL 0x2000
142#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
143#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
144#define BCSR_RESETS_PB1550_WSCFSM 0x2000
145#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
146#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
147#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
148#define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */
149
150#define BCSR_BOARD_PCIM66EN 0x0001
151#define BCSR_BOARD_SD0PWR 0x0040
152#define BCSR_BOARD_SD1PWR 0x0080
153#define BCSR_BOARD_PCIM33 0x0100
154#define BCSR_BOARD_PCIEXTARB 0x0200
155#define BCSR_BOARD_GPIO200RST 0x0400
156#define BCSR_BOARD_PCICLKOUT 0x0800
157#define BCSR_BOARD_PCICFG 0x1000
158#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */
159#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
160#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
161
162
163/* DB/PB1200 */
164#define BCSR_RESETS_ETH 0x0001
165#define BCSR_RESETS_CAMERA 0x0002
166#define BCSR_RESETS_DC 0x0004
167#define BCSR_RESETS_IDE 0x0008
168#define BCSR_RESETS_TV 0x0010 /* DB1200 */
169/* Not resets but in the same register */
170#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
171#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
172#define BCSR_RESETS_PSC0MUX 0x1000
173#define BCSR_RESETS_PSC1MUX 0x2000
174#define BCSR_RESETS_SPISEL 0x4000
175#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
176
177#define BCSR_BOARD_LCDVEE 0x0001
178#define BCSR_BOARD_LCDVDD 0x0002
179#define BCSR_BOARD_LCDBL 0x0004
180#define BCSR_BOARD_CAMSNAP 0x0010
181#define BCSR_BOARD_CAMPWR 0x0020
182#define BCSR_BOARD_SD0PWR 0x0040
183
184
185#define BCSR_SWITCHES_DIP 0x00FF
186#define BCSR_SWITCHES_DIP_1 0x0080
187#define BCSR_SWITCHES_DIP_2 0x0040
188#define BCSR_SWITCHES_DIP_3 0x0020
189#define BCSR_SWITCHES_DIP_4 0x0010
190#define BCSR_SWITCHES_DIP_5 0x0008
191#define BCSR_SWITCHES_DIP_6 0x0004
192#define BCSR_SWITCHES_DIP_7 0x0002
193#define BCSR_SWITCHES_DIP_8 0x0001
194#define BCSR_SWITCHES_ROTARY 0x0F00
195
196
197#define BCSR_PCMCIA_PC0VPP 0x0003
198#define BCSR_PCMCIA_PC0VCC 0x000C
199#define BCSR_PCMCIA_PC0DRVEN 0x0010
200#define BCSR_PCMCIA_PC0RST 0x0080
201#define BCSR_PCMCIA_PC1VPP 0x0300
202#define BCSR_PCMCIA_PC1VCC 0x0C00
203#define BCSR_PCMCIA_PC1DRVEN 0x1000
204#define BCSR_PCMCIA_PC1RST 0x8000
205
206
207#define BCSR_LEDS_DECIMALS 0x0003
208#define BCSR_LEDS_LED0 0x0100
209#define BCSR_LEDS_LED1 0x0200
210#define BCSR_LEDS_LED2 0x0400
211#define BCSR_LEDS_LED3 0x0800
212
213
214#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
215#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
216#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
217
218
219
220
221/* initialize BCSR for a board. Provide the PHYSICAL addresses of both
222 * BCSR spaces.
223 */
224void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys);
225
226/* read a board register */
227unsigned short bcsr_read(enum bcsr_id reg);
228
229/* write to a board register */
230void bcsr_write(enum bcsr_id reg, unsigned short val);
231
232/* modify a register. clear bits set in 'clr', set bits set in 'set' */
233void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set);
234
235/* install CPLD IRQ demuxer (DB1200/PB1200) */
236void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq);
237
238#endif
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 27f26102b1bb..3404248f5094 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -25,133 +25,9 @@
25#define __ASM_DB1200_H 25#define __ASM_DB1200_H
26 26
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 29#include <asm/mach-au1x00/au1xxx_psc.h>
29 30
30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
34
35/*
36 * SPI and SMB are muxed on the DBAu1200 board.
37 * Refer to board documentation.
38 */
39#define SPI_PSC_BASE PSC0_BASE_ADDR
40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
41/*
42 * AC'97 and I2S are muxed on the DBAu1200 board.
43 * Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xB9800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_U0RXD 0x1000
106#define BCSR_STATUS_U1RXD 0x2000
107
108#define BCSR_SWITCHES_OCTAL 0x00FF
109#define BCSR_SWITCHES_DIP_1 0x0080
110#define BCSR_SWITCHES_DIP_2 0x0040
111#define BCSR_SWITCHES_DIP_3 0x0020
112#define BCSR_SWITCHES_DIP_4 0x0010
113#define BCSR_SWITCHES_DIP_5 0x0008
114#define BCSR_SWITCHES_DIP_6 0x0004
115#define BCSR_SWITCHES_DIP_7 0x0002
116#define BCSR_SWITCHES_DIP_8 0x0001
117#define BCSR_SWITCHES_ROTARY 0x0F00
118
119#define BCSR_RESETS_ETH 0x0001
120#define BCSR_RESETS_CAMERA 0x0002
121#define BCSR_RESETS_DC 0x0004
122#define BCSR_RESETS_IDE 0x0008
123#define BCSR_RESETS_TV 0x0010
124/* Not resets but in the same register */
125#define BCSR_RESETS_PWMR1MUX 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129
130#define BCSR_PCMCIA_PC0VPP 0x0003
131#define BCSR_PCMCIA_PC0VCC 0x000C
132#define BCSR_PCMCIA_PC0DRVEN 0x0010
133#define BCSR_PCMCIA_PC0RST 0x0080
134#define BCSR_PCMCIA_PC1VPP 0x0300
135#define BCSR_PCMCIA_PC1VCC 0x0C00
136#define BCSR_PCMCIA_PC1DRVEN 0x1000
137#define BCSR_PCMCIA_PC1RST 0x8000
138
139#define BCSR_BOARD_LCDVEE 0x0001
140#define BCSR_BOARD_LCDVDD 0x0002
141#define BCSR_BOARD_LCDBL 0x0004
142#define BCSR_BOARD_CAMSNAP 0x0010
143#define BCSR_BOARD_CAMPWR 0x0020
144#define BCSR_BOARD_SD0PWR 0x0040
145
146#define BCSR_LEDS_DECIMALS 0x0003
147#define BCSR_LEDS_LED0 0x0100
148#define BCSR_LEDS_LED1 0x0200
149#define BCSR_LEDS_LED2 0x0400
150#define BCSR_LEDS_LED3 0x0800
151
152#define BCSR_SYSTEM_POWEROFF 0x4000
153#define BCSR_SYSTEM_RESET 0x8000
154
155/* Bit positions for the different interrupt sources */ 31/* Bit positions for the different interrupt sources */
156#define BCSR_INT_IDE 0x0001 32#define BCSR_INT_IDE 0x0001
157#define BCSR_INT_ETH 0x0002 33#define BCSR_INT_ETH 0x0002
@@ -168,17 +44,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
168#define BCSR_INT_SD0INSERT 0x1000 44#define BCSR_INT_SD0INSERT 0x1000
169#define BCSR_INT_SD0EJECT 0x2000 45#define BCSR_INT_SD0EJECT 0x2000
170 46
171#define SMC91C111_PHYS_ADDR 0x19000300
172#define SMC91C111_INT DB1200_ETH_INT
173
174#define IDE_PHYS_ADDR 0x18800000 47#define IDE_PHYS_ADDR 0x18800000
175#define IDE_REG_SHIFT 5 48#define IDE_REG_SHIFT 5
176#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
177#define IDE_INT DB1200_IDE_INT
178#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 49#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
179#define IDE_RQSIZE 128 50#define IDE_RQSIZE 128
180 51
181#define NAND_PHYS_ADDR 0x20000000 52#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
53#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
54#define DB1200_ETH_PHYS_ADDR 0x19000300
55#define DB1200_NAND_PHYS_ADDR 0x20000000
182 56
183/* 57/*
184 * External Interrupts for DBAu1200 as of 8/6/2004. 58 * External Interrupts for DBAu1200 as of 8/6/2004.
@@ -188,7 +62,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
188 * Example: IDE bis pos is = 64 - 64 62 * Example: IDE bis pos is = 64 - 64
189 * ETH bit pos is = 65 - 64 63 * ETH bit pos is = 65 - 64
190 */ 64 */
191enum external_pb1200_ints { 65enum external_db1200_ints {
192 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, 66 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
193 67
194 DB1200_IDE_INT = DB1200_INT_BEGIN, 68 DB1200_IDE_INT = DB1200_INT_BEGIN,
@@ -209,22 +83,4 @@ enum external_pb1200_ints {
209 DB1200_INT_END = DB1200_INT_BEGIN + 15, 83 DB1200_INT_END = DB1200_INT_BEGIN + 15,
210}; 84};
211 85
212
213/*
214 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
215 */
216#define PCMCIA_MAX_SOCK 1
217#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
218
219/* VPP/VCC */
220#define SET_VCC_VPP(VCC, VPP, SLOT) \
221 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
222
223#define BOARD_PC0_INT DB1200_PC0_INT
224#define BOARD_PC1_INT DB1200_PC1_INT
225#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
226
227/* NAND chip select */
228#define NAND_CS 1
229
230#endif /* __ASM_DB1200_H */ 86#endif /* __ASM_DB1200_H */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index 1a515b8c870f..a919dac525a1 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -41,111 +41,11 @@
41#define SMBUS_PSC_BASE PSC2_BASE_ADDR 41#define SMBUS_PSC_BASE PSC2_BASE_ADDR
42#define I2S_PSC_BASE PSC3_BASE_ADDR 42#define I2S_PSC_BASE PSC3_BASE_ADDR
43 43
44#define BCSR_KSEG1_ADDR 0xAF000000
45#define NAND_PHYS_ADDR 0x20000000 44#define NAND_PHYS_ADDR 0x20000000
46 45
47#else
48#define BCSR_KSEG1_ADDR 0xAE000000
49#endif 46#endif
50 47
51/* 48/*
52 * Overlay data structure of the DBAu1x00 board registers.
53 * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
54 */
55typedef volatile struct
56{
57 /*00*/ unsigned short whoami;
58 unsigned short reserved0;
59 /*04*/ unsigned short status;
60 unsigned short reserved1;
61 /*08*/ unsigned short switches;
62 unsigned short reserved2;
63 /*0C*/ unsigned short resets;
64 unsigned short reserved3;
65 /*10*/ unsigned short pcmcia;
66 unsigned short reserved4;
67 /*14*/ unsigned short specific;
68 unsigned short reserved5;
69 /*18*/ unsigned short leds;
70 unsigned short reserved6;
71 /*1C*/ unsigned short swreset;
72 unsigned short reserved7;
73
74} BCSR;
75
76
77/*
78 * Register/mask bit definitions for the BCSRs
79 */
80#define BCSR_WHOAMI_DCID 0x000F
81#define BCSR_WHOAMI_CPLD 0x00F0
82#define BCSR_WHOAMI_BOARD 0x0F00
83
84#define BCSR_STATUS_PC0VS 0x0003
85#define BCSR_STATUS_PC1VS 0x000C
86#define BCSR_STATUS_PC0FI 0x0010
87#define BCSR_STATUS_PC1FI 0x0020
88#define BCSR_STATUS_FLASHBUSY 0x0100
89#define BCSR_STATUS_ROMBUSY 0x0400
90#define BCSR_STATUS_SWAPBOOT 0x2000
91#define BCSR_STATUS_FLASHDEN 0xC000
92
93#define BCSR_SWITCHES_DIP 0x00FF
94#define BCSR_SWITCHES_DIP_1 0x0080
95#define BCSR_SWITCHES_DIP_2 0x0040
96#define BCSR_SWITCHES_DIP_3 0x0020
97#define BCSR_SWITCHES_DIP_4 0x0010
98#define BCSR_SWITCHES_DIP_5 0x0008
99#define BCSR_SWITCHES_DIP_6 0x0004
100#define BCSR_SWITCHES_DIP_7 0x0002
101#define BCSR_SWITCHES_DIP_8 0x0001
102#define BCSR_SWITCHES_ROTARY 0x0F00
103
104#define BCSR_RESETS_PHY0 0x0001
105#define BCSR_RESETS_PHY1 0x0002
106#define BCSR_RESETS_DC 0x0004
107#define BCSR_RESETS_FIR_SEL 0x2000
108#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
109#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
110#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
111#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
112#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
113
114#define BCSR_PCMCIA_PC0VPP 0x0003
115#define BCSR_PCMCIA_PC0VCC 0x000C
116#define BCSR_PCMCIA_PC0DRVEN 0x0010
117#define BCSR_PCMCIA_PC0RST 0x0080
118#define BCSR_PCMCIA_PC1VPP 0x0300
119#define BCSR_PCMCIA_PC1VCC 0x0C00
120#define BCSR_PCMCIA_PC1DRVEN 0x1000
121#define BCSR_PCMCIA_PC1RST 0x8000
122
123#define BCSR_BOARD_PCIM66EN 0x0001
124#define BCSR_BOARD_SD0_PWR 0x0040
125#define BCSR_BOARD_SD1_PWR 0x0080
126#define BCSR_BOARD_PCIM33 0x0100
127#define BCSR_BOARD_GPIO200RST 0x0400
128#define BCSR_BOARD_PCICFG 0x1000
129#define BCSR_BOARD_SD0_WP 0x4000
130#define BCSR_BOARD_SD1_WP 0x8000
131
132#define BCSR_LEDS_DECIMALS 0x0003
133#define BCSR_LEDS_LED0 0x0100
134#define BCSR_LEDS_LED1 0x0200
135#define BCSR_LEDS_LED2 0x0400
136#define BCSR_LEDS_LED3 0x0800
137
138#define BCSR_SWRESET_RESET 0x0080
139
140/* PCMCIA DBAu1x00 specific defines */
141#define PCMCIA_MAX_SOCK 1
142#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
143
144/* VPP/VCC */
145#define SET_VCC_VPP(VCC, VPP, SLOT)\
146 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
147
148/*
149 * NAND defines 49 * NAND defines
150 * 50 *
151 * Timing values as described in databook, * ns value stripped of the 51 * Timing values as described in databook, * ns value stripped of the
diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
deleted file mode 100644
index 107104c3cd12..000000000000
--- a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
7 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
11
12/*
13 * Basler eXcite has an RM9122 processor.
14 */
15#define cpu_has_watch 1
16#define cpu_has_mips16 0
17#define cpu_has_divec 0
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 0
23#define cpu_has_ejtag 0
24
25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0
30#define cpu_icache_snoops_remote_store 0
31#define cpu_has_mipsmt 0
32#define cpu_has_userlocal 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_mips32r1 0
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 0
40#define cpu_has_mips64r2 0
41
42#define cpu_has_inclusive_pcaches 0
43
44#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32
46#define cpu_scache_line_size() 32
47
48#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
deleted file mode 100644
index 4c29ba44992c..000000000000
--- a/arch/mips/include/asm/mach-excite/excite.h
+++ /dev/null
@@ -1,154 +0,0 @@
1#ifndef __EXCITE_H__
2#define __EXCITE_H__
3
4#include <linux/init.h>
5#include <asm/addrspace.h>
6#include <asm/types.h>
7
8#define EXCITE_CPU_EXT_CLOCK 100000000
9
10#if !defined(__ASSEMBLY__)
11void __init excite_kgdb_init(void);
12void excite_procfs_init(void);
13extern unsigned long memsize;
14extern char modetty[];
15extern u32 unit_id;
16#endif
17
18/* Base name for XICAP devices */
19#define XICAP_NAME "xicap_gpi"
20
21/* OCD register offsets */
22#define LKB0 0x0038
23#define LKB5 0x0128
24#define LKM5 0x012C
25#define LKB7 0x0138
26#define LKM7 0x013c
27#define LKB8 0x0140
28#define LKM8 0x0144
29#define LKB9 0x0148
30#define LKM9 0x014c
31#define LKB10 0x0150
32#define LKM10 0x0154
33#define LKB11 0x0158
34#define LKM11 0x015c
35#define LKB12 0x0160
36#define LKM12 0x0164
37#define LKB13 0x0168
38#define LKM13 0x016c
39#define LDP0 0x0200
40#define LDP1 0x0210
41#define LDP2 0x0220
42#define LDP3 0x0230
43#define INTPIN0 0x0A40
44#define INTPIN1 0x0A44
45#define INTPIN2 0x0A48
46#define INTPIN3 0x0A4C
47#define INTPIN4 0x0A50
48#define INTPIN5 0x0A54
49#define INTPIN6 0x0A58
50#define INTPIN7 0x0A5C
51
52
53
54
55/* TITAN register offsets */
56#define CPRR 0x0004
57#define CPDSR 0x0008
58#define CPTC0R 0x000c
59#define CPTC1R 0x0010
60#define CPCFG0 0x0020
61#define CPCFG1 0x0024
62#define CPDST0A 0x0028
63#define CPDST0B 0x002c
64#define CPDST1A 0x0030
65#define CPDST1B 0x0034
66#define CPXDSTA 0x0038
67#define CPXDSTB 0x003c
68#define CPXCISRA 0x0048
69#define CPXCISRB 0x004c
70#define CPGIG0ER 0x0050
71#define CPGIG1ER 0x0054
72#define CPGRWL 0x0068
73#define CPURSLMT 0x00f8
74#define UACFG 0x0200
75#define UAINTS 0x0204
76#define SDRXFCIE 0x4828
77#define SDTXFCIE 0x4928
78#define INTP0Status0 0x1B00
79#define INTP0Mask0 0x1B04
80#define INTP0Set0 0x1B08
81#define INTP0Clear0 0x1B0C
82#define GXCFG 0x5000
83#define GXDMADRPFX 0x5018
84#define GXDMA_DESCADR 0x501c
85#define GXCH0TDESSTRT 0x5054
86
87/* IRQ definitions */
88#define NMICONFIG 0xac0
89#define TITAN_MSGINT 0xc4
90#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
91#define FPGA0_MSGINT 0x5a
92#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
93#define FPGA1_MSGINT 0x7b
94#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
95#define PHY_MSGINT 0x9c
96#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
97
98#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
99/* Pre-release units used interrupt pin #9 */
100#define USB_IRQ 11
101#else
102/* Re-designed units use interrupt pin #1 */
103#define USB_MSGINT 0x39
104#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
105#endif
106#define TIMER_IRQ 12
107
108
109/* Device address ranges */
110#define EXCITE_OFFS_OCD 0x1fffc000
111#define EXCITE_SIZE_OCD (16 * 1024)
112#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
113#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
114
115#define EXCITE_OFFS_SCRAM 0x1fffa000
116#define EXCITE_SIZE_SCRAM (8 << 10)
117#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
118#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
119
120#define EXCITE_OFFS_PCI_IO 0x1fff8000
121#define EXCITE_SIZE_PCI_IO (8 << 10)
122#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
123#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
124
125#define EXCITE_OFFS_TITAN 0x1fff0000
126#define EXCITE_SIZE_TITAN (32 << 10)
127#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
128#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
129
130#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
131#define EXCITE_SIZE_PCI_MEM (64 << 10)
132#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
133#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
134
135#define EXCITE_OFFS_FPGA 0x1ffdc000
136#define EXCITE_SIZE_FPGA (16 << 10)
137#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
138#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
139
140#define EXCITE_OFFS_NAND 0x1ffd8000
141#define EXCITE_SIZE_NAND (16 << 10)
142#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
143#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
144
145#define EXCITE_OFFS_BOOTROM 0x1f000000
146#define EXCITE_SIZE_BOOTROM (8 << 20)
147#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
148#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
149
150/* FPGA address offsets */
151#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
152#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
153
154#endif /* __EXCITE_H__ */
diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
deleted file mode 100644
index 0a1ef69bece7..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
1#ifndef EXCITE_FPGA_H_INCLUDED
2#define EXCITE_FPGA_H_INCLUDED
3
4
5/**
6 * Address alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform.
9 */
10#ifdef EXCITE_CCI_FPGA_MK2
11typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12#else
13typedef unsigned char excite_cci_fpga_align_t;
14#endif
15
16
17/**
18 * Size of Dual Ported RAM.
19 */
20#define EXCITE_DPR_SIZE 263
21
22
23/**
24 * Size of Reserved Status Fields in Dual Ported RAM.
25 */
26#define EXCITE_DPR_STATUS_SIZE 7
27
28
29
30/**
31 * FPGA.
32 * Hardware register layout of the FPGA interface. The FPGA must accessed
33 * byte wise solely.
34 * @see EXCITE_CCI_DPR_MK2
35 */
36typedef struct excite_fpga {
37
38 /**
39 * Dual Ported RAM.
40 */
41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42
43 /**
44 * Status.
45 */
46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47
48#ifdef EXCITE_CCI_FPGA_MK2
49 /**
50 * RM9000 Interrupt.
51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52 */
53 excite_cci_fpga_align_t rm9k_int;
54#else
55 /**
56 * MK2 Interrupt.
57 * Write access initiates interrupt at the ARM processor of the MK2.
58 */
59 excite_cci_fpga_align_t mk2_int;
60
61 excite_cci_fpga_align_t gap[0x1000-0x10f];
62
63 /**
64 * IRQ Source/Acknowledge.
65 */
66 excite_cci_fpga_align_t rm9k_irq_src;
67
68 /**
69 * IRQ Mask.
70 * Set bits enable the related interrupt.
71 */
72 excite_cci_fpga_align_t rm9k_irq_mask;
73#endif
74
75
76} excite_fpga;
77
78
79
80#endif /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
deleted file mode 100644
index c4cf6140622e..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_nandflash.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __EXCITE_NANDFLASH_H__
2#define __EXCITE_NANDFLASH_H__
3
4/* Resource names */
5#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
6
7#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
deleted file mode 100644
index 94705a46f72e..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_eth.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#if !defined(__RM9K_ETH_H__)
2#define __RM9K_ETH_H__
3
4#define RM9K_GE_NAME "rm9k_ge"
5
6/* Resource names */
7#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
8#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
9#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
10#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
11#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
12#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
13#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
14#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
15#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
16#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
17#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
18#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
19#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
20#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
21#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
22
23#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
deleted file mode 100644
index 3fa3c08d2da7..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_wdt.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __RM9K_WDT_H__
2#define __RM9K_WDT_H__
3
4/* Device name */
5#define WDT_NAME "wdt_gpi"
6
7/* Resource names */
8#define WDT_RESOURCE_REGS "excite_watchdog_regs"
9#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
10#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
11
12#endif /* __RM9K_WDT_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
deleted file mode 100644
index 009577734a8d..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_xicap.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __EXCITE_XICAP_H__
2#define __EXCITE_XICAP_H__
3
4
5/* Resource names */
6#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
7#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
8#define XICAP_RESOURCE_XDMA "xicap_xdma"
9#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
10#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
11#define XICAP_RESOURCE_IRQ "xicap_irq"
12#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
13#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
14#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
15
16#endif /* __EXCITE_XICAP_H__ */
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index 09a59bcc1b07..1b1a7d1632b9 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -24,7 +24,9 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
24 24
25#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid) 25#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid)
26#define parent_node(node) (node) 26#define parent_node(node) (node)
27#define cpumask_of_node(node) (&hub_data(node)->h_cpus) 27#define cpumask_of_node(node) ((node) == -1 ? \
28 cpu_all_mask : \
29 &hub_data(node)->h_cpus)
28struct pci_bus; 30struct pci_bus;
29extern int pcibus_to_node(struct pci_bus *); 31extern int pcibus_to_node(struct pci_bus *);
30 32
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 9947e57c91de..16210cedd929 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com> 6 * Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
7 * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca> 7 * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
8 * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org> 8 * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
9 * 9 *
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
new file mode 100644
index 000000000000..021f77ca59ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -0,0 +1,305 @@
1/*
2 * The header file of cs5536 sourth bridge.
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu <liujl@lemote.com>
6 */
7
8#ifndef _CS5536_H
9#define _CS5536_H
10
11#include <linux/types.h>
12
13extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
14extern void _wrmsr(u32 msr, u32 hi, u32 lo);
15
16/*
17 * MSR module base
18 */
19#define CS5536_SB_MSR_BASE (0x00000000)
20#define CS5536_GLIU_MSR_BASE (0x10000000)
21#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
22#define CS5536_USB_MSR_BASE (0x40000000)
23#define CS5536_IDE_MSR_BASE (0x60000000)
24#define CS5536_DIVIL_MSR_BASE (0x80000000)
25#define CS5536_ACC_MSR_BASE (0xa0000000)
26#define CS5536_UNUSED_MSR_BASE (0xc0000000)
27#define CS5536_GLCP_MSR_BASE (0xe0000000)
28
29#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
30#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
31#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
32#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
33#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
34#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
35#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
36#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
37#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
38
39/*
40 * BAR SPACE OF VIRTUAL PCI :
41 * range for pci probe use, length is the actual size.
42 */
43/* IO space for all DIVIL modules */
44#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
45#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
46#define CS5536_SMB_RANGE 0xfffffff8
47#define CS5536_SMB_LENGTH 0x08
48#define CS5536_GPIO_RANGE 0xffffff00
49#define CS5536_GPIO_LENGTH 0x100
50#define CS5536_MFGPT_RANGE 0xffffffc0
51#define CS5536_MFGPT_LENGTH 0x40
52#define CS5536_ACPI_RANGE 0xffffffe0
53#define CS5536_ACPI_LENGTH 0x20
54#define CS5536_PMS_RANGE 0xffffff80
55#define CS5536_PMS_LENGTH 0x80
56/* IO space for IDE */
57#define CS5536_IDE_RANGE 0xfffffff0
58#define CS5536_IDE_LENGTH 0x10
59/* IO space for ACC */
60#define CS5536_ACC_RANGE 0xffffff80
61#define CS5536_ACC_LENGTH 0x80
62/* MEM space for ALL USB modules */
63#define CS5536_OHCI_RANGE 0xfffff000
64#define CS5536_OHCI_LENGTH 0x1000
65#define CS5536_EHCI_RANGE 0xfffff000
66#define CS5536_EHCI_LENGTH 0x1000
67
68/*
69 * PCI MSR ACCESS
70 */
71#define PCI_MSR_CTRL 0xF0
72#define PCI_MSR_ADDR 0xF4
73#define PCI_MSR_DATA_LO 0xF8
74#define PCI_MSR_DATA_HI 0xFC
75
76/**************** MSR *****************************/
77
78/*
79 * GLIU STANDARD MSR
80 */
81#define GLIU_CAP 0x00
82#define GLIU_CONFIG 0x01
83#define GLIU_SMI 0x02
84#define GLIU_ERROR 0x03
85#define GLIU_PM 0x04
86#define GLIU_DIAG 0x05
87
88/*
89 * GLIU SPEC. MSR
90 */
91#define GLIU_P2D_BM0 0x20
92#define GLIU_P2D_BM1 0x21
93#define GLIU_P2D_BM2 0x22
94#define GLIU_P2D_BMK0 0x23
95#define GLIU_P2D_BMK1 0x24
96#define GLIU_P2D_BM3 0x25
97#define GLIU_P2D_BM4 0x26
98#define GLIU_COH 0x80
99#define GLIU_PAE 0x81
100#define GLIU_ARB 0x82
101#define GLIU_ASMI 0x83
102#define GLIU_AERR 0x84
103#define GLIU_DEBUG 0x85
104#define GLIU_PHY_CAP 0x86
105#define GLIU_NOUT_RESP 0x87
106#define GLIU_NOUT_WDATA 0x88
107#define GLIU_WHOAMI 0x8B
108#define GLIU_SLV_DIS 0x8C
109#define GLIU_IOD_BM0 0xE0
110#define GLIU_IOD_BM1 0xE1
111#define GLIU_IOD_BM2 0xE2
112#define GLIU_IOD_BM3 0xE3
113#define GLIU_IOD_BM4 0xE4
114#define GLIU_IOD_BM5 0xE5
115#define GLIU_IOD_BM6 0xE6
116#define GLIU_IOD_BM7 0xE7
117#define GLIU_IOD_BM8 0xE8
118#define GLIU_IOD_BM9 0xE9
119#define GLIU_IOD_SC0 0xEA
120#define GLIU_IOD_SC1 0xEB
121#define GLIU_IOD_SC2 0xEC
122#define GLIU_IOD_SC3 0xED
123#define GLIU_IOD_SC4 0xEE
124#define GLIU_IOD_SC5 0xEF
125#define GLIU_IOD_SC6 0xF0
126#define GLIU_IOD_SC7 0xF1
127
128/*
129 * SB STANDARD
130 */
131#define SB_CAP 0x00
132#define SB_CONFIG 0x01
133#define SB_SMI 0x02
134#define SB_ERROR 0x03
135#define SB_MAR_ERR_EN 0x00000001
136#define SB_TAR_ERR_EN 0x00000002
137#define SB_RSVD_BIT1 0x00000004
138#define SB_EXCEP_ERR_EN 0x00000008
139#define SB_SYSE_ERR_EN 0x00000010
140#define SB_PARE_ERR_EN 0x00000020
141#define SB_TAS_ERR_EN 0x00000040
142#define SB_MAR_ERR_FLAG 0x00010000
143#define SB_TAR_ERR_FLAG 0x00020000
144#define SB_RSVD_BIT2 0x00040000
145#define SB_EXCEP_ERR_FLAG 0x00080000
146#define SB_SYSE_ERR_FLAG 0x00100000
147#define SB_PARE_ERR_FLAG 0x00200000
148#define SB_TAS_ERR_FLAG 0x00400000
149#define SB_PM 0x04
150#define SB_DIAG 0x05
151
152/*
153 * SB SPEC.
154 */
155#define SB_CTRL 0x10
156#define SB_R0 0x20
157#define SB_R1 0x21
158#define SB_R2 0x22
159#define SB_R3 0x23
160#define SB_R4 0x24
161#define SB_R5 0x25
162#define SB_R6 0x26
163#define SB_R7 0x27
164#define SB_R8 0x28
165#define SB_R9 0x29
166#define SB_R10 0x2A
167#define SB_R11 0x2B
168#define SB_R12 0x2C
169#define SB_R13 0x2D
170#define SB_R14 0x2E
171#define SB_R15 0x2F
172
173/*
174 * GLCP STANDARD
175 */
176#define GLCP_CAP 0x00
177#define GLCP_CONFIG 0x01
178#define GLCP_SMI 0x02
179#define GLCP_ERROR 0x03
180#define GLCP_PM 0x04
181#define GLCP_DIAG 0x05
182
183/*
184 * GLCP SPEC.
185 */
186#define GLCP_CLK_DIS_DELAY 0x08
187#define GLCP_PM_CLK_DISABLE 0x09
188#define GLCP_GLB_PM 0x0B
189#define GLCP_DBG_OUT 0x0C
190#define GLCP_RSVD1 0x0D
191#define GLCP_SOFT_COM 0x0E
192#define SOFT_BAR_SMB_FLAG 0x00000001
193#define SOFT_BAR_GPIO_FLAG 0x00000002
194#define SOFT_BAR_MFGPT_FLAG 0x00000004
195#define SOFT_BAR_IRQ_FLAG 0x00000008
196#define SOFT_BAR_PMS_FLAG 0x00000010
197#define SOFT_BAR_ACPI_FLAG 0x00000020
198#define SOFT_BAR_IDE_FLAG 0x00000400
199#define SOFT_BAR_ACC_FLAG 0x00000800
200#define SOFT_BAR_OHCI_FLAG 0x00001000
201#define SOFT_BAR_EHCI_FLAG 0x00002000
202#define GLCP_RSVD2 0x0F
203#define GLCP_CLK_OFF 0x10
204#define GLCP_CLK_ACTIVE 0x11
205#define GLCP_CLK_DISABLE 0x12
206#define GLCP_CLK4ACK 0x13
207#define GLCP_SYS_RST 0x14
208#define GLCP_RSVD3 0x15
209#define GLCP_DBG_CLK_CTRL 0x16
210#define GLCP_CHIP_REV_ID 0x17
211
212/* PIC */
213#define PIC_YSEL_LOW 0x20
214#define PIC_YSEL_LOW_USB_SHIFT 8
215#define PIC_YSEL_LOW_ACC_SHIFT 16
216#define PIC_YSEL_LOW_FLASH_SHIFT 24
217#define PIC_YSEL_HIGH 0x21
218#define PIC_ZSEL_LOW 0x22
219#define PIC_ZSEL_HIGH 0x23
220#define PIC_IRQM_PRIM 0x24
221#define PIC_IRQM_LPC 0x25
222#define PIC_XIRR_STS_LOW 0x26
223#define PIC_XIRR_STS_HIGH 0x27
224#define PCI_SHDW 0x34
225
226/*
227 * DIVIL STANDARD
228 */
229#define DIVIL_CAP 0x00
230#define DIVIL_CONFIG 0x01
231#define DIVIL_SMI 0x02
232#define DIVIL_ERROR 0x03
233#define DIVIL_PM 0x04
234#define DIVIL_DIAG 0x05
235
236/*
237 * DIVIL SPEC.
238 */
239#define DIVIL_LBAR_IRQ 0x08
240#define DIVIL_LBAR_KEL 0x09
241#define DIVIL_LBAR_SMB 0x0B
242#define DIVIL_LBAR_GPIO 0x0C
243#define DIVIL_LBAR_MFGPT 0x0D
244#define DIVIL_LBAR_ACPI 0x0E
245#define DIVIL_LBAR_PMS 0x0F
246#define DIVIL_LEG_IO 0x14
247#define DIVIL_BALL_OPTS 0x15
248#define DIVIL_SOFT_IRQ 0x16
249#define DIVIL_SOFT_RESET 0x17
250
251/* MFGPT */
252#define MFGPT_IRQ 0x28
253
254/*
255 * IDE STANDARD
256 */
257#define IDE_CAP 0x00
258#define IDE_CONFIG 0x01
259#define IDE_SMI 0x02
260#define IDE_ERROR 0x03
261#define IDE_PM 0x04
262#define IDE_DIAG 0x05
263
264/*
265 * IDE SPEC.
266 */
267#define IDE_IO_BAR 0x08
268#define IDE_CFG 0x10
269#define IDE_DTC 0x12
270#define IDE_CAST 0x13
271#define IDE_ETC 0x14
272#define IDE_INTERNAL_PM 0x15
273
274/*
275 * ACC STANDARD
276 */
277#define ACC_CAP 0x00
278#define ACC_CONFIG 0x01
279#define ACC_SMI 0x02
280#define ACC_ERROR 0x03
281#define ACC_PM 0x04
282#define ACC_DIAG 0x05
283
284/*
285 * USB STANDARD
286 */
287#define USB_CAP 0x00
288#define USB_CONFIG 0x01
289#define USB_SMI 0x02
290#define USB_ERROR 0x03
291#define USB_PM 0x04
292#define USB_DIAG 0x05
293
294/*
295 * USB SPEC.
296 */
297#define USB_OHCI 0x08
298#define USB_EHCI 0x09
299
300/****************** NATIVE ***************************/
301/* GPIO : I/O SPACE; REG : 32BITS */
302#define GPIOL_OUT_VAL 0x00
303#define GPIOL_OUT_EN 0x04
304
305#endif /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
new file mode 100644
index 000000000000..4b493d6772c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
@@ -0,0 +1,35 @@
1/*
2 * cs5536 mfgpt header file
3 */
4
5#ifndef _CS5536_MFGPT_H
6#define _CS5536_MFGPT_H
7
8#include <cs5536/cs5536.h>
9#include <cs5536/cs5536_pci.h>
10
11#ifdef CONFIG_CS5536_MFGPT
12extern void setup_mfgpt0_timer(void);
13extern void disable_mfgpt0_counter(void);
14extern void enable_mfgpt0_counter(void);
15#else
16static inline void __maybe_unused setup_mfgpt0_timer(void)
17{
18}
19static inline void __maybe_unused disable_mfgpt0_counter(void)
20{
21}
22static inline void __maybe_unused enable_mfgpt0_counter(void)
23{
24}
25#endif
26
27#define MFGPT_TICK_RATE 14318000
28#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ)
29
30#define MFGPT_BASE mfgpt_base
31#define MFGPT0_CMP2 (MFGPT_BASE + 2)
32#define MFGPT0_CNT (MFGPT_BASE + 4)
33#define MFGPT0_SETUP (MFGPT_BASE + 6)
34
35#endif /*!_CS5536_MFGPT_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
new file mode 100644
index 000000000000..0dca9c89ee7c
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -0,0 +1,153 @@
1/*
2 * the definition file of cs5536 Virtual Support Module(VSM).
3 * pci configuration space can be accessed through the VSM, so
4 * there is no need of the MSR read/write now, except the spec.
5 * MSR registers which are not implemented yet.
6 *
7 * Copyright (C) 2007 Lemote Inc.
8 * Author : jlliu, liujl@lemote.com
9 */
10
11#ifndef _CS5536_PCI_H
12#define _CS5536_PCI_H
13
14#include <linux/types.h>
15#include <linux/pci_regs.h>
16
17extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
18extern u32 cs5536_pci_conf_read4(int function, int reg);
19
20#define CS5536_ACC_INTR 9
21#define CS5536_IDE_INTR 14
22#define CS5536_USB_INTR 11
23#define CS5536_MFGPT_INTR 5
24#define CS5536_UART1_INTR 4
25#define CS5536_UART2_INTR 3
26
27/************** PCI BUS DEVICE FUNCTION ***************/
28
29/*
30 * PCI bus device function
31 */
32#define PCI_BUS_CS5536 0
33#define PCI_IDSEL_CS5536 14
34
35/********** STANDARD PCI-2.2 EXPANSION ****************/
36
37/*
38 * PCI configuration space
39 * we have to virtualize the PCI configure space head, so we should
40 * define the necessary IDs and some others.
41 */
42
43/* CONFIG of PCI VENDOR ID*/
44#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
45 (((mod_dev_id) << 16) | (sys_vendor_id))
46
47/* VENDOR ID */
48#define CS5536_VENDOR_ID 0x1022
49
50/* DEVICE ID */
51#define CS5536_ISA_DEVICE_ID 0x2090
52#define CS5536_IDE_DEVICE_ID 0x209a
53#define CS5536_ACC_DEVICE_ID 0x2093
54#define CS5536_OHCI_DEVICE_ID 0x2094
55#define CS5536_EHCI_DEVICE_ID 0x2095
56
57/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
58#define CS5536_ISA_CLASS_CODE 0x060100
59#define CS5536_IDE_CLASS_CODE 0x010180
60#define CS5536_ACC_CLASS_CODE 0x040100
61#define CS5536_OHCI_CLASS_CODE 0x0C0310
62#define CS5536_EHCI_CLASS_CODE 0x0C0320
63
64/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
65
66#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \
67 ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
68 | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
69
70#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
71#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
72#define PCI_NORMAL_HEADER_TYPE 0x00
73#define PCI_NORMAL_LATENCY_TIMER 0x00
74#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
75
76/* BAR */
77#define PCI_BAR0_REG 0x10
78#define PCI_BAR1_REG 0x14
79#define PCI_BAR2_REG 0x18
80#define PCI_BAR3_REG 0x1c
81#define PCI_BAR4_REG 0x20
82#define PCI_BAR5_REG 0x24
83#define PCI_BAR_COUNT 6
84#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
85
86/* CARDBUS CIS POINTER */
87#define PCI_CARDBUS_CIS_POINTER 0x00000000
88
89/* SUBSYSTEM VENDOR ID */
90#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
91
92/* SUBSYSTEM ID */
93#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
94#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
95#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
96#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
97#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
98
99/* EXPANSION ROM BAR */
100#define PCI_EXPANSION_ROM_BAR 0x00000000
101
102/* CAPABILITIES POINTER */
103#define PCI_CAPLIST_POINTER 0x00000000
104#define PCI_CAPLIST_USB_POINTER 0x40
105/* INTERRUPT */
106
107#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
108 ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
109 ((pin) << 8) | (mod_intr))
110
111#define PCI_MAX_LATENCY 0x40
112#define PCI_MIN_GRANT 0x00
113#define PCI_DEFAULT_PIN 0x01
114
115/*********** EXPANSION PCI REG ************************/
116
117/*
118 * ISA EXPANSION
119 */
120#define PCI_UART1_INT_REG 0x50
121#define PCI_UART2_INT_REG 0x54
122#define PCI_ISA_FIXUP_REG 0x58
123
124/*
125 * IDE EXPANSION
126 */
127#define PCI_IDE_CFG_REG 0x40
128#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
129#define PCI_IDE_DTC_REG 0x48
130#define PCI_IDE_CAST_REG 0x4C
131#define PCI_IDE_ETC_REG 0x50
132#define PCI_IDE_PM_REG 0x54
133#define PCI_IDE_INT_REG 0x60
134
135/*
136 * ACC EXPANSION
137 */
138#define PCI_ACC_INT_REG 0x50
139
140/*
141 * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
142 */
143#define PCI_OHCI_PM_REG 0x40
144#define PCI_OHCI_INT_REG 0x50
145
146/*
147 * EHCI EXPANSION
148 */
149#define PCI_EHCI_LEGSMIEN_REG 0x50
150#define PCI_EHCI_LEGSMISTS_REG 0x54
151#define PCI_EHCI_FLADJ_REG 0x60
152
153#endif /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
new file mode 100644
index 000000000000..21c4ecedebe7
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -0,0 +1,31 @@
1/*
2 * the read/write interfaces for Virtual Support Module(VSM)
3 *
4 * Copyright (C) 2009 Lemote, Inc.
5 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
6 */
7
8#ifndef _CS5536_VSM_H
9#define _CS5536_VSM_H
10
11#include <linux/types.h>
12
13typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
14typedef u32 (*cs5536_pci_vsm_read)(int reg);
15
16#define DECLARE_CS5536_MODULE(name) \
17extern void pci_##name##_write_reg(int reg, u32 value); \
18extern u32 pci_##name##_read_reg(int reg);
19
20/* ide module */
21DECLARE_CS5536_MODULE(ide)
22/* acc module */
23DECLARE_CS5536_MODULE(acc)
24/* ohci module */
25DECLARE_CS5536_MODULE(ohci)
26/* isa module */
27DECLARE_CS5536_MODULE(isa)
28/* ehci module */
29DECLARE_CS5536_MODULE(ehci)
30
31#endif /* _CS5536_VSM_H */
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index 71a6851ba833..981c75f91a7d 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
28static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 28static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
29 dma_addr_t dma_addr) 29 dma_addr_t dma_addr)
30{ 30{
31#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
32 return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
33#else
31 return dma_addr & 0x7fffffff; 34 return dma_addr & 0x7fffffff;
35#endif
32} 36}
33 37
34static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, 38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index da70bcf2304e..fcdbe3a4ce1f 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -1,12 +1,11 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your 7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version. 8 * option) any later version.
9 *
10 */ 9 */
11 10
12#ifndef __ASM_MACH_LOONGSON_LOONGSON_H 11#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
@@ -15,9 +14,6 @@
15#include <linux/io.h> 14#include <linux/io.h>
16#include <linux/init.h> 15#include <linux/init.h>
17 16
18/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
19#include <asm/mips-boards/bonito64.h>
20
21/* loongson internal northbridge initialization */ 17/* loongson internal northbridge initialization */
22extern void bonito_irq_init(void); 18extern void bonito_irq_init(void);
23 19
@@ -26,13 +22,25 @@ extern void mach_prepare_reboot(void);
26extern void mach_prepare_shutdown(void); 22extern void mach_prepare_shutdown(void);
27 23
28/* environment arguments from bootloader */ 24/* environment arguments from bootloader */
29extern unsigned long bus_clock, cpu_clock_freq; 25extern unsigned long cpu_clock_freq;
30extern unsigned long memsize, highmemsize; 26extern unsigned long memsize, highmemsize;
31 27
32/* loongson-specific command line, env and memory initialization */ 28/* loongson-specific command line, env and memory initialization */
33extern void __init prom_init_memory(void); 29extern void __init prom_init_memory(void);
34extern void __init prom_init_cmdline(void); 30extern void __init prom_init_cmdline(void);
31extern void __init prom_init_machtype(void);
35extern void __init prom_init_env(void); 32extern void __init prom_init_env(void);
33#ifdef CONFIG_LOONGSON_UART_BASE
34extern unsigned long _loongson_uart_base, loongson_uart_base;
35extern void prom_init_loongson_uart_base(void);
36#endif
37
38static inline void prom_init_uart_base(void)
39{
40#ifdef CONFIG_LOONGSON_UART_BASE
41 prom_init_loongson_uart_base();
42#endif
43}
36 44
37/* irq operation functions */ 45/* irq operation functions */
38extern void bonito_irqdispatch(void); 46extern void bonito_irqdispatch(void);
@@ -40,25 +48,276 @@ extern void __init bonito_irq_init(void);
40extern void __init set_irq_trigger_mode(void); 48extern void __init set_irq_trigger_mode(void);
41extern void __init mach_init_irq(void); 49extern void __init mach_init_irq(void);
42extern void mach_irq_dispatch(unsigned int pending); 50extern void mach_irq_dispatch(unsigned int pending);
51extern int mach_i8259_irq(void);
52
53/* We need this in some places... */
54#define delay() ({ \
55 int x; \
56 for (x = 0; x < 100000; x++) \
57 __asm__ __volatile__(""); \
58})
59
60#define LOONGSON_REG(x) \
61 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
62
63#define LOONGSON_IRQ_BASE 32
64#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
65
66#define LOONGSON_FLASH_BASE 0x1c000000
67#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
68#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
69
70#define LOONGSON_LIO0_BASE 0x1e000000
71#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
72#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
73
74#define LOONGSON_BOOT_BASE 0x1fc00000
75#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
76#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
77#define LOONGSON_REG_BASE 0x1fe00000
78#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
79#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
80
81#define LOONGSON_LIO1_BASE 0x1ff00000
82#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
83#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
84
85#define LOONGSON_PCILO0_BASE 0x10000000
86#define LOONGSON_PCILO1_BASE 0x14000000
87#define LOONGSON_PCILO2_BASE 0x18000000
88#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
89#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
90#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
91
92#define LOONGSON_PCICFG_BASE 0x1fe80000
93#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
94#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
95#define LOONGSON_PCIIO_BASE 0x1fd00000
96#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
97#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
98
99/* Loongson Register Bases */
100
101#define LOONGSON_PCICONFIGBASE 0x00
102#define LOONGSON_REGBASE 0x100
43 103
44/* PCI Configuration Registers */ 104/* PCI Configuration Registers */
45#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) 105
106#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
107#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
108#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
109#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
110#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
111#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
112#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
113#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
114#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
115#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
116#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
117#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
118
119#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
120
121#define LOONGSON_PCICMD_PERR_CLR 0x80000000
122#define LOONGSON_PCICMD_SERR_CLR 0x40000000
123#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
124#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
125#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
126#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
127#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
128#define LOONGSON_PCICMD_ASTEPEN 0x00000080
129#define LOONGSON_PCICMD_SERREN 0x00000100
130#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
131#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
132
133/* Loongson h/w Configuration */
134
135#define LOONGSON_GENCFG_OFFSET 0x4
136#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
137
138#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
139#define LOONGSON_GENCFG_SNOOPEN 0x00000002
140#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
141
142#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
143#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
144#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
145#define LOONGSON_GENCFG_BYTESWAP 0x00000040
146
147#define LOONGSON_GENCFG_UNCACHED 0x00000080
148#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
149#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
150#define LOONGSON_GENCFG_CACHEALG 0x00000c00
151#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
152#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
153#define LOONGSON_GENCFG_CACHESTOP 0x00002000
154#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
155#define LOONGSON_GENCFG_BUSERREN 0x00008000
156#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
157#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
158
159/* PCI address map control */
160
161#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
162#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
163#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
164
165/* GPIO Regs - r/w */
166
167#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
168#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
169
170/* ICU Configuration Regs - r/w */
171
172#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
173#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
174#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
175
176/* ICU Enable Regs - IntEn & IntISR are r/o. */
177
178#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
179#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
180#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
181#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
182
183/* ICU */
184#define LOONGSON_ICU_MBOXES 0x0000000f
185#define LOONGSON_ICU_MBOXES_SHIFT 0
186#define LOONGSON_ICU_DMARDY 0x00000010
187#define LOONGSON_ICU_DMAEMPTY 0x00000020
188#define LOONGSON_ICU_COPYRDY 0x00000040
189#define LOONGSON_ICU_COPYEMPTY 0x00000080
190#define LOONGSON_ICU_COPYERR 0x00000100
191#define LOONGSON_ICU_PCIIRQ 0x00000200
192#define LOONGSON_ICU_MASTERERR 0x00000400
193#define LOONGSON_ICU_SYSTEMERR 0x00000800
194#define LOONGSON_ICU_DRAMPERR 0x00001000
195#define LOONGSON_ICU_RETRYERR 0x00002000
196#define LOONGSON_ICU_GPIOS 0x01ff0000
197#define LOONGSON_ICU_GPIOS_SHIFT 16
198#define LOONGSON_ICU_GPINS 0x7e000000
199#define LOONGSON_ICU_GPINS_SHIFT 25
200#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
201#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
202#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
203
204/* PCI prefetch window base & mask */
205
206#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
207#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
208#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
209#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
46 210
47/* PCI_Hit*_Sel_* */ 211/* PCI_Hit*_Sel_* */
48 212
49#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) 213#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
50#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) 214#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
51#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) 215#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
52#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) 216#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
53#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) 217#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
54#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) 218#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
55 219
56/* PXArb Config & Status */ 220/* PXArb Config & Status */
57 221
58#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) 222#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
59#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) 223#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
224
225/* pcimap */
226
227#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
228#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
229#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
230#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
231#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
232#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
233#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
234#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
235 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
236
237#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
238#include <linux/cpufreq.h>
239extern void loongson2_cpu_wait(void);
240extern struct cpufreq_frequency_table loongson2_clockmod_table[];
241
242/* Chip Config */
243#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
244#endif
245
246/*
247 * address windows configuration module
248 *
249 * loongson2e do not have this module
250 */
251#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
252
253/* address window config module base address */
254#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
255#define LOONGSON_ADDRWINCFG_SIZE 0x180
256
257extern unsigned long _loongson_addrwincfg_base;
258#define LOONGSON_ADDRWINCFG(offset) \
259 (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
260
261#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
262#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
263#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
264#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
265
266#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
267#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
268#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
269#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
270
271#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
272#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
273#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
274#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
275
276#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
277#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
278#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
279#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
280
281#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
282#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
283#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
284#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
285
286#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
287#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
288#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
289#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
290
291#define ADDRWIN_WIN0 0
292#define ADDRWIN_WIN1 1
293#define ADDRWIN_WIN2 2
294#define ADDRWIN_WIN3 3
295
296#define ADDRWIN_MAP_DST_DDR 0
297#define ADDRWIN_MAP_DST_PCI 1
298#define ADDRWIN_MAP_DST_LIO 1
299
300/*
301 * s: CPU, PCIDMA
302 * d: DDR, PCI, LIO
303 * win: 0, 1, 2, 3
304 * src: map source
305 * dst: map destination
306 * size: ~mask + 1
307 */
308#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
309 s##_WIN##w##_BASE = (src); \
310 s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
311 s##_WIN##w##_MASK = ~(size-1); \
312} while (0)
313
314#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
315 LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
316#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
317 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
318#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
319 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
60 320
61/* loongson2-specific perf counter IRQ */ 321#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
62#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6)
63 322
64#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ 323#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 206ea2067916..43213388c174 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -13,10 +13,15 @@
13 13
14#ifdef CONFIG_LEMOTE_FULOONG2E 14#ifdef CONFIG_LEMOTE_FULOONG2E
15 15
16#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
17
18#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E 16#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
19 17
20#endif 18#endif
21 19
20/* use fuloong2f as the default machine of LEMOTE_MACH2F */
21#ifdef CONFIG_LEMOTE_MACH2F
22
23#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
24
25#endif
26
22#endif /* __ASM_MACH_LOONGSON_MACHINE_H */ 27#endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index bd7b3cba7e35..3b23ee8647d6 100644
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -12,19 +12,30 @@
12#define __ASM_MACH_LOONGSON_MEM_H 12#define __ASM_MACH_LOONGSON_MEM_H
13 13
14/* 14/*
15 * On Lemote Loongson 2e 15 * high memory space
16 * 16 *
17 * the high memory space starts from 512M. 17 * in loongson2e, starts from 512M
18 * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. 18 * in loongson2f, starts from 2G 256M
19 */ 19 */
20#ifdef CONFIG_CPU_LOONGSON2E
21#define LOONGSON_HIGHMEM_START 0x20000000
22#else
23#define LOONGSON_HIGHMEM_START 0x90000000
24#endif
20 25
21#ifdef CONFIG_LEMOTE_FULOONG2E 26/*
22 27 * the peripheral registers(MMIO):
23#define LOONGSON_HIGHMEM_START 0x20000000 28 *
29 * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
30 * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
31 */
24 32
25#define LOONGSON_MMIO_MEM_START 0x10000000 33#define LOONGSON_MMIO_MEM_START 0x10000000
26#define LOONGSON_MMIO_MEM_END 0x20000000
27 34
35#ifdef CONFIG_CPU_LOONGSON2E
36#define LOONGSON_MMIO_MEM_END 0x20000000
37#else
38#define LOONGSON_MMIO_MEM_END 0x80000000
28#endif 39#endif
29 40
30#endif /* __ASM_MACH_LOONGSON_MEM_H */ 41#endif /* __ASM_MACH_LOONGSON_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index f1663ca81da0..bc99dab4ef63 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -1,37 +1,50 @@
1/* 1/*
2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> 2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
3 * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
3 * 4 *
4 * This program is free software; you can redistribute it 5 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General 6 * and/or modify it under the terms of the GNU General
6 * Public License as published by the Free Software 7 * Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your 8 * Foundation; either version 2 of the License, or (at your
8 * option) any later version. 9 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be
11 * useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public
17 * License along with this program; if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
19 * 02139, USA.
20 */ 10 */
21 11
22#ifndef __ASM_MACH_LOONGSON_PCI_H_ 12#ifndef __ASM_MACH_LOONGSON_PCI_H_
23#define __ASM_MACH_LOONGSON_PCI_H_ 13#define __ASM_MACH_LOONGSON_PCI_H_
24 14
25extern struct pci_ops bonito64_pci_ops; 15extern struct pci_ops loongson_pci_ops;
16
17/* this is an offset from mips_io_port_base */
18#define LOONGSON_PCI_IO_START 0x00004000UL
19
20#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
21
22/*
23 * we use address window2 to map cpu address space to pci space
24 * window2: cpu [1G, 2G] -> pci [1G, 2G]
25 * why not use window 0 & 1? because they are used by cpu when booting.
26 * window0: cpu [0, 256M] -> ddr [0, 256M]
27 * window1: cpu [256M, 512M] -> pci [256M, 512M]
28 */
29
30/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
31#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
32#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
33
34#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
35#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
36
37#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
38 LOONGSON_PCI_MEM_START + 1)
26 39
27#ifdef CONFIG_LEMOTE_FULOONG2E 40#else /* loongson2f/32bit & loongson2e */
28 41
29/* this pci memory space is mapped by pcimap in pci.c */ 42/* this pci memory space is mapped by pcimap in pci.c */
30#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE 43#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
31#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) 44#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
32/* this is an offset from mips_io_port_base */ 45/* this is an offset from mips_io_port_base */
33#define LOONGSON_PCI_IO_START 0x00004000UL 46#define LOONGSON_PCI_IO_START 0x00004000UL
34 47
35#endif 48#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
36 49
37#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ 50#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h
deleted file mode 100644
index b1a60f1cbd02..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1100.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Alchemy Semi Pb1100 Referrence Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1100_H
27#define __ASM_PB1100_H
28
29#define PB1100_IDENT 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31# define PB1100_ROM_SEL (1 << 15)
32# define PB1100_ROM_SIZ (1 << 14)
33# define PB1100_SWAP_BOOT (1 << 13)
34# define PB1100_FLASH_WP (1 << 12)
35# define PB1100_ROM_H_STS (1 << 11)
36# define PB1100_ROM_L_STS (1 << 10)
37# define PB1100_FLASH_H_STS (1 << 9)
38# define PB1100_FLASH_L_STS (1 << 8)
39# define PB1100_SRAM_SIZ (1 << 7)
40# define PB1100_TSC_BUSY (1 << 6)
41# define PB1100_PCMCIA_VS_MASK (3 << 4)
42# define PB1100_RS232_CD (1 << 3)
43# define PB1100_RS232_CTS (1 << 2)
44# define PB1100_RS232_DSR (1 << 1)
45# define PB1100_RS232_RI (1 << 0)
46
47#define PB1100_IRDA_RS232 0xAE00000C
48# define PB1100_IRDA_FULL (0 << 14) /* full power */
49# define PB1100_IRDA_SHUTDOWN (1 << 14)
50# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
51# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
52# define PB1100_IRDA_FIR (1 << 13)
53
54#define PCMCIA_BOARD_REG 0xAE000010
55# define PB1100_SD_WP1_RO (1 << 15) /* read only */
56# define PB1100_SD_WP0_RO (1 << 14) /* read only */
57# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
58# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
59# define PB1100_SEL_SD_CONN1 (1 << 9)
60# define PB1100_SEL_SD_CONN0 (1 << 8)
61# define PC_DEASSERT_RST (1 << 7)
62# define PC_DRV_EN (1 << 4)
63
64#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
65
66#define PB1100_RST_VDDI 0xAE00001C
67# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
68# define PB1100_VDDI_MASK 0x1F
69
70#define PB1100_LEDS 0xAE000018
71
72/*
73 * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
74 * 7:0 is the LED Display's decimal points.
75 */
76#define PB1100_HEX_LED 0xAE000018
77
78/* PCMCIA Pb1100 specific defines */
79#define PCMCIA_MAX_SOCK 0
80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
81
82/* VPP/VCC */
83#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
84
85#endif /* __ASM_PB1100_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index c8618df88cb5..962eb55dc880 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -25,6 +25,7 @@
25#define __ASM_PB1200_H 25#define __ASM_PB1200_H
26 26
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 29#include <asm/mach-au1x00/au1xxx_psc.h>
29 30
30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 31#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
@@ -43,113 +44,8 @@
43 * Refer to board documentation. 44 * Refer to board documentation.
44 */ 45 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR 46#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR 47#define I2S_PSC_BASE PSC1_BASE_ADDR
47 48
48#define BCSR_KSEG1_ADDR 0xAD800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_SD1WP 0x0800
106#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000
108
109#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080
111#define BCSR_SWITCHES_DIP_2 0x0040
112#define BCSR_SWITCHES_DIP_3 0x0020
113#define BCSR_SWITCHES_DIP_4 0x0010
114#define BCSR_SWITCHES_DIP_5 0x0008
115#define BCSR_SWITCHES_DIP_6 0x0004
116#define BCSR_SWITCHES_DIP_7 0x0002
117#define BCSR_SWITCHES_DIP_8 0x0001
118#define BCSR_SWITCHES_ROTARY 0x0F00
119
120#define BCSR_RESETS_ETH 0x0001
121#define BCSR_RESETS_CAMERA 0x0002
122#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008
124/* not resets but in the same register */
125#define BCSR_RESETS_WSCFSM 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129#define BCSR_RESETS_SD1MUX 0x8000
130
131#define BCSR_PCMCIA_PC0VPP 0x0003
132#define BCSR_PCMCIA_PC0VCC 0x000C
133#define BCSR_PCMCIA_PC0DRVEN 0x0010
134#define BCSR_PCMCIA_PC0RST 0x0080
135#define BCSR_PCMCIA_PC1VPP 0x0300
136#define BCSR_PCMCIA_PC1VCC 0x0C00
137#define BCSR_PCMCIA_PC1DRVEN 0x1000
138#define BCSR_PCMCIA_PC1RST 0x8000
139
140#define BCSR_BOARD_LCDVEE 0x0001
141#define BCSR_BOARD_LCDVDD 0x0002
142#define BCSR_BOARD_LCDBL 0x0004
143#define BCSR_BOARD_CAMSNAP 0x0010
144#define BCSR_BOARD_CAMPWR 0x0020
145#define BCSR_BOARD_SD0PWR 0x0040
146#define BCSR_BOARD_SD1PWR 0x0080
147
148#define BCSR_LEDS_DECIMALS 0x00FF
149#define BCSR_LEDS_LED0 0x0100
150#define BCSR_LEDS_LED1 0x0200
151#define BCSR_LEDS_LED2 0x0400
152#define BCSR_LEDS_LED3 0x0800
153 49
154#define BCSR_SYSTEM_VDDI 0x001F 50#define BCSR_SYSTEM_VDDI 0x001F
155#define BCSR_SYSTEM_POWEROFF 0x4000 51#define BCSR_SYSTEM_POWEROFF 0x4000
@@ -239,20 +135,6 @@ enum external_pb1200_ints {
239 PB1200_INT_END = PB1200_INT_BEGIN + 15 135 PB1200_INT_END = PB1200_INT_BEGIN + 15
240}; 136};
241 137
242/*
243 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
244 */
245#define PCMCIA_MAX_SOCK 1
246#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
247
248/* VPP/VCC */
249#define SET_VCC_VPP(VCC, VPP, SLOT) \
250 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
251
252#define BOARD_PC0_INT PB1200_PC0_INT
253#define BOARD_PC1_INT PB1200_PC1_INT
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
255
256/* NAND chip select */ 138/* NAND chip select */
257#define NAND_CS 1 139#define NAND_CS 1
258 140
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h
deleted file mode 100644
index da51a2eb7b82..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1500.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Alchemy Semi Pb1500 Referrence Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1500_H
27#define __ASM_PB1500_H
28
29#define IDENT_BOARD_REG 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31#define PCI_BOARD_REG 0xAE000010
32#define PCMCIA_BOARD_REG 0xAE000010
33# define PC_DEASSERT_RST 0x80
34# define PC_DRV_EN 0x10
35#define PB1500_G_CONTROL 0xAE000014
36#define PB1500_RST_VDDI 0xAE00001C
37#define PB1500_LEDS 0xAE000018
38
39#define PB1500_HEX_LED 0xAF000004
40#define PB1500_HEX_LED_BLANK 0xAF000008
41
42/* PCMCIA Pb1500 specific defines */
43#define PCMCIA_MAX_SOCK 0
44#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
45
46/* VPP/VCC */
47#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
48
49#endif /* __ASM_PB1500_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 6704a11497db..58796410bd6e 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -40,102 +40,6 @@
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR 41#define I2S_PSC_BASE PSC3_BASE_ADDR
42 42
43#define BCSR_PHYS_ADDR 0xAF000000
44
45typedef volatile struct
46{
47 /*00*/ u16 whoami;
48 u16 reserved0;
49 /*04*/ u16 status;
50 u16 reserved1;
51 /*08*/ u16 switches;
52 u16 reserved2;
53 /*0C*/ u16 resets;
54 u16 reserved3;
55 /*10*/ u16 pcmcia;
56 u16 reserved4;
57 /*14*/ u16 pci;
58 u16 reserved5;
59 /*18*/ u16 leds;
60 u16 reserved6;
61 /*1C*/ u16 system;
62 u16 reserved7;
63
64} BCSR;
65
66static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
67
68/*
69 * Register bit definitions for the BCSRs
70 */
71#define BCSR_WHOAMI_DCID 0x000F
72#define BCSR_WHOAMI_CPLD 0x00F0
73#define BCSR_WHOAMI_BOARD 0x0F00
74
75#define BCSR_STATUS_PCMCIA0VS 0x0003
76#define BCSR_STATUS_PCMCIA1VS 0x000C
77#define BCSR_STATUS_PCMCIA0FI 0x0010
78#define BCSR_STATUS_PCMCIA1FI 0x0020
79#define BCSR_STATUS_SWAPBOOT 0x0040
80#define BCSR_STATUS_SRAMWIDTH 0x0080
81#define BCSR_STATUS_FLASHBUSY 0x0100
82#define BCSR_STATUS_ROMBUSY 0x0200
83#define BCSR_STATUS_USBOTGID 0x0800
84#define BCSR_STATUS_U0RXD 0x1000
85#define BCSR_STATUS_U1RXD 0x2000
86#define BCSR_STATUS_U3RXD 0x8000
87
88#define BCSR_SWITCHES_OCTAL 0x00FF
89#define BCSR_SWITCHES_DIP_1 0x0080
90#define BCSR_SWITCHES_DIP_2 0x0040
91#define BCSR_SWITCHES_DIP_3 0x0020
92#define BCSR_SWITCHES_DIP_4 0x0010
93#define BCSR_SWITCHES_DIP_5 0x0008
94#define BCSR_SWITCHES_DIP_6 0x0004
95#define BCSR_SWITCHES_DIP_7 0x0002
96#define BCSR_SWITCHES_DIP_8 0x0001
97#define BCSR_SWITCHES_ROTARY 0x0F00
98
99#define BCSR_RESETS_PHY0 0x0001
100#define BCSR_RESETS_PHY1 0x0002
101#define BCSR_RESETS_DC 0x0004
102#define BCSR_RESETS_WSC 0x2000
103#define BCSR_RESETS_SPISEL 0x4000
104#define BCSR_RESETS_DMAREQ 0x8000
105
106#define BCSR_PCMCIA_PC0VPP 0x0003
107#define BCSR_PCMCIA_PC0VCC 0x000C
108#define BCSR_PCMCIA_PC0DRVEN 0x0010
109#define BCSR_PCMCIA_PC0RST 0x0080
110#define BCSR_PCMCIA_PC1VPP 0x0300
111#define BCSR_PCMCIA_PC1VCC 0x0C00
112#define BCSR_PCMCIA_PC1DRVEN 0x1000
113#define BCSR_PCMCIA_PC1RST 0x8000
114
115#define BCSR_PCI_M66EN 0x0001
116#define BCSR_PCI_M33 0x0100
117#define BCSR_PCI_EXTERNARB 0x0200
118#define BCSR_PCI_GPIO200RST 0x0400
119#define BCSR_PCI_CLKOUT 0x0800
120#define BCSR_PCI_CFGHOST 0x1000
121
122#define BCSR_LEDS_DECIMALS 0x00FF
123#define BCSR_LEDS_LED0 0x0100
124#define BCSR_LEDS_LED1 0x0200
125#define BCSR_LEDS_LED2 0x0400
126#define BCSR_LEDS_LED3 0x0800
127
128#define BCSR_SYSTEM_VDDI 0x001F
129#define BCSR_SYSTEM_POWEROFF 0x4000
130#define BCSR_SYSTEM_RESET 0x8000
131
132#define PCMCIA_MAX_SOCK 1
133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
134
135/* VPP/VCC */
136#define SET_VCC_VPP(VCC, VPP, SLOT) \
137 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
138
139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 43#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
140#define PB1550_BOTH_BANKS 44#define PB1550_BOTH_BANKS
141#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER) 45#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h
index 8de0eb9c98a3..ed3a88da70f6 100644
--- a/arch/mips/include/asm/mach-pnx833x/gpio.h
+++ b/arch/mips/include/asm/mach-pnx833x/gpio.h
@@ -24,7 +24,7 @@
24 24
25/* BIG FAT WARNING: races danger! 25/* BIG FAT WARNING: races danger!
26 No protections exist here. Current users are only early init code, 26 No protections exist here. Current users are only early init code,
27 when locking is not needed because no cuncurency yet exists there, 27 when locking is not needed because no concurrency yet exists there,
28 and GPIO IRQ dispatcher, which does locking. 28 and GPIO IRQ dispatcher, which does locking.
29 However, if many uses will ever happen, proper locking will be needed 29 However, if many uses will ever happen, proper locking will be needed
30 - including locking between different uses 30 - including locking between different uses
diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
index 657f089b1724..6d70264557b2 100644
--- a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
+++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
@@ -123,4 +123,3 @@
123#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) 123#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
124 124
125#endif 125#endif
126
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
new file mode 100644
index 000000000000..bcad43a93ebf
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_ASIC_H
20#define _ASM_MACH_POWERTV_ASIC_H
21
22#include <linux/ioport.h>
23#include <asm/mach-powertv/asic_regs.h>
24
25#define DVR_CAPABLE (1<<0)
26#define PCIE_CAPABLE (1<<1)
27#define FFS_CAPABLE (1<<2)
28#define DISPLAY_CAPABLE (1<<3)
29
30/* Platform Family types
31 * For compitability, the new value must be added in the end */
32enum family_type {
33 FAMILY_8500,
34 FAMILY_8500RNG,
35 FAMILY_4500,
36 FAMILY_1500,
37 FAMILY_8600,
38 FAMILY_4600,
39 FAMILY_4600VZA,
40 FAMILY_8600VZB,
41 FAMILY_1500VZE,
42 FAMILY_1500VZF,
43 FAMILIES
44};
45
46/* Register maps for each ASIC */
47extern const struct register_map calliope_register_map;
48extern const struct register_map cronus_register_map;
49extern const struct register_map zeus_register_map;
50
51extern struct resource dvr_cronus_resources[];
52extern struct resource dvr_zeus_resources[];
53extern struct resource non_dvr_calliope_resources[];
54extern struct resource non_dvr_cronus_resources[];
55extern struct resource non_dvr_cronuslite_resources[];
56extern struct resource non_dvr_vz_calliope_resources[];
57extern struct resource non_dvr_vze_calliope_resources[];
58extern struct resource non_dvr_vzf_calliope_resources[];
59extern struct resource non_dvr_zeus_resources[];
60
61extern void powertv_platform_init(void);
62extern void platform_alloc_bootmem(void);
63extern enum asic_type platform_get_asic(void);
64extern enum family_type platform_get_family(void);
65extern int platform_supports_dvr(void);
66extern int platform_supports_ffs(void);
67extern int platform_supports_pcie(void);
68extern int platform_supports_display(void);
69extern void configure_platform(void);
70extern void platform_configure_usb_ehci(void);
71extern void platform_unconfigure_usb_ehci(void);
72extern void platform_configure_usb_ohci(void);
73extern void platform_unconfigure_usb_ohci(void);
74
75/* Platform Resources */
76#define ASIC_RESOURCE_GET_EXISTS 1
77extern struct resource *asic_resource_get(const char *name);
78extern void platform_release_memory(void *baddr, int size);
79
80/* Reboot Cause */
81extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
82extern void set_locked_reboot_cause(char code, unsigned int data,
83 unsigned int data2);
84
85enum sys_reboot_type {
86 sys_unknown_reboot = 0x00, /* Unknown reboot cause */
87 sys_davic_change = 0x01, /* Reboot due to change in DAVIC
88 * mode */
89 sys_user_reboot = 0x02, /* Reboot initiated by user */
90 sys_system_reboot = 0x03, /* Reboot initiated by OS */
91 sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
92 sys_silent_reboot = 0x05, /* Silent reboot */
93 sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
94 sys_power_up_reboot = 0x07, /* Power on bootup. Older
95 * drivers may report as
96 * userReboot. */
97 sys_code_change = 0x08, /* Reboot to take code change.
98 * Older drivers may report as
99 * userReboot. */
100 sys_hardware_reset = 0x09, /* HW watchdog or front-panel
101 * reset button reset. Older
102 * drivers may report as
103 * userReboot. */
104 sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
105};
106
107#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
new file mode 100644
index 000000000000..6f26cb09828e
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
@@ -0,0 +1,90 @@
1/*
2 * asic_reg_map.h
3 *
4 * A macro-enclosed list of the elements for the register_map structure for
5 * use in defining and manipulating the structure.
6 *
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
25REGISTER_MAP_ELEMENT(eic_cfg_bits)
26REGISTER_MAP_ELEMENT(eic_ready_status)
27REGISTER_MAP_ELEMENT(chipver3)
28REGISTER_MAP_ELEMENT(chipver2)
29REGISTER_MAP_ELEMENT(chipver1)
30REGISTER_MAP_ELEMENT(chipver0)
31REGISTER_MAP_ELEMENT(uart1_intstat)
32REGISTER_MAP_ELEMENT(uart1_inten)
33REGISTER_MAP_ELEMENT(uart1_config1)
34REGISTER_MAP_ELEMENT(uart1_config2)
35REGISTER_MAP_ELEMENT(uart1_divisorhi)
36REGISTER_MAP_ELEMENT(uart1_divisorlo)
37REGISTER_MAP_ELEMENT(uart1_data)
38REGISTER_MAP_ELEMENT(uart1_status)
39REGISTER_MAP_ELEMENT(int_stat_3)
40REGISTER_MAP_ELEMENT(int_stat_2)
41REGISTER_MAP_ELEMENT(int_stat_1)
42REGISTER_MAP_ELEMENT(int_stat_0)
43REGISTER_MAP_ELEMENT(int_config)
44REGISTER_MAP_ELEMENT(int_int_scan)
45REGISTER_MAP_ELEMENT(ien_int_3)
46REGISTER_MAP_ELEMENT(ien_int_2)
47REGISTER_MAP_ELEMENT(ien_int_1)
48REGISTER_MAP_ELEMENT(ien_int_0)
49REGISTER_MAP_ELEMENT(int_level_3_3)
50REGISTER_MAP_ELEMENT(int_level_3_2)
51REGISTER_MAP_ELEMENT(int_level_3_1)
52REGISTER_MAP_ELEMENT(int_level_3_0)
53REGISTER_MAP_ELEMENT(int_level_2_3)
54REGISTER_MAP_ELEMENT(int_level_2_2)
55REGISTER_MAP_ELEMENT(int_level_2_1)
56REGISTER_MAP_ELEMENT(int_level_2_0)
57REGISTER_MAP_ELEMENT(int_level_1_3)
58REGISTER_MAP_ELEMENT(int_level_1_2)
59REGISTER_MAP_ELEMENT(int_level_1_1)
60REGISTER_MAP_ELEMENT(int_level_1_0)
61REGISTER_MAP_ELEMENT(int_level_0_3)
62REGISTER_MAP_ELEMENT(int_level_0_2)
63REGISTER_MAP_ELEMENT(int_level_0_1)
64REGISTER_MAP_ELEMENT(int_level_0_0)
65REGISTER_MAP_ELEMENT(int_docsis_en)
66REGISTER_MAP_ELEMENT(mips_pll_setup)
67REGISTER_MAP_ELEMENT(usb_fs)
68REGISTER_MAP_ELEMENT(test_bus)
69REGISTER_MAP_ELEMENT(crt_spare)
70REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
71REGISTER_MAP_ELEMENT(usb2_strap)
72REGISTER_MAP_ELEMENT(ehci_hcapbase)
73REGISTER_MAP_ELEMENT(ohci_hc_revision)
74REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
75REGISTER_MAP_ELEMENT(usb2_control)
76REGISTER_MAP_ELEMENT(usb2_stbus_obc)
77REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
78REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
79REGISTER_MAP_ELEMENT(pcie_regs)
80REGISTER_MAP_ELEMENT(tim_ch)
81REGISTER_MAP_ELEMENT(tim_cl)
82REGISTER_MAP_ELEMENT(gpio_dout)
83REGISTER_MAP_ELEMENT(gpio_din)
84REGISTER_MAP_ELEMENT(gpio_dir)
85REGISTER_MAP_ELEMENT(watchdog)
86REGISTER_MAP_ELEMENT(front_panel)
87REGISTER_MAP_ELEMENT(misc_clk_ctl1)
88REGISTER_MAP_ELEMENT(misc_clk_ctl2)
89REGISTER_MAP_ELEMENT(crt_ext_ctl)
90REGISTER_MAP_ELEMENT(register_maps)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
new file mode 100644
index 000000000000..1e11236c6dbc
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -0,0 +1,122 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_MACH_POWERTV_ASIC_H_
20#define __ASM_MACH_POWERTV_ASIC_H_
21#include <linux/io.h>
22
23/* ASIC types */
24enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASICS
31};
32
33/* hardcoded values read from Chip Version registers */
34#define CRONUS_10 0x0B4C1C20
35#define CRONUS_11 0x0B4C1C21
36#define CRONUSLITE_10 0x0B4C1C40
37
38#define NAND_FLASH_BASE 0x03000000
39#define CALLIOPE_IO_BASE 0x08000000
40#define CRONUS_IO_BASE 0x09000000
41#define ZEUS_IO_BASE 0x09000000
42
43#define ASIC_IO_SIZE 0x01000000
44
45/* Definitions for backward compatibility */
46#define UART1_INTSTAT uart1_intstat
47#define UART1_INTEN uart1_inten
48#define UART1_CONFIG1 uart1_config1
49#define UART1_CONFIG2 uart1_config2
50#define UART1_DIVISORHI uart1_divisorhi
51#define UART1_DIVISORLO uart1_divisorlo
52#define UART1_DATA uart1_data
53#define UART1_STATUS uart1_status
54
55/* ASIC register enumeration */
56union register_map_entry {
57 unsigned long phys;
58 u32 *virt;
59};
60
61#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
62struct register_map {
63#include <asm/mach-powertv/asic_reg_map.h>
64};
65#undef REGISTER_MAP_ELEMENT
66
67/**
68 * register_map_offset_phys - add an offset to the physical address
69 * @map: Pointer to the &struct register_map
70 * @offset: Value to add
71 *
72 * Only adds the base to non-zero physical addresses
73 */
74static inline void register_map_offset_phys(struct register_map *map,
75 unsigned long offset)
76{
77#define REGISTER_MAP_ELEMENT(x) do { \
78 if (map->x.phys != 0) \
79 map->x.phys += offset; \
80 } while (false);
81
82#include <asm/mach-powertv/asic_reg_map.h>
83#undef REGISTER_MAP_ELEMENT
84}
85
86/**
87 * register_map_virtualize - Convert &register_map to virtual addresses
88 * @map: Pointer to &register_map to virtualize
89 */
90static inline void register_map_virtualize(struct register_map *map)
91{
92#define REGISTER_MAP_ELEMENT(x) do { \
93 map->x.virt = (!map->x.phys) ? NULL : \
94 UNCAC_ADDR(phys_to_virt(map->x.phys)); \
95 } while (false);
96
97#include <asm/mach-powertv/asic_reg_map.h>
98#undef REGISTER_MAP_ELEMENT
99}
100
101extern struct register_map _asic_register_map;
102
103/*
104 * Macros to interface to registers through their ioremapped address
105 * asic_reg_phys_addr Returns the physical address of the given register
106 * asic_reg_addr Returns the iomapped virtual address of the given
107 * register.
108 */
109#define asic_reg_addr(x) (_asic_register_map.x.virt)
110#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
111 (unsigned long) asic_reg_addr(x))))
112
113/*
114 * The asic_reg macro is gone. It should be replaced by either asic_read or
115 * asic_write, as appropriate.
116 */
117
118#define asic_read(x) readl(asic_reg_addr(x))
119#define asic_write(v, x) writel(v, asic_reg_addr(x))
120
121extern void asic_irq_init(void);
122#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
new file mode 100644
index 000000000000..5b8d5ebeb838
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -0,0 +1,119 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Version from mach-generic modified to support PowerTV port
7 * Portions Copyright (C) 2009 Cisco Systems, Inc.
8 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 *
10 */
11
12#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14
15#include <linux/sched.h>
16#include <linux/version.h>
17#include <linux/device.h>
18#include <asm/mach-powertv/asic.h>
19
20static inline bool is_kseg2(void *addr)
21{
22 return (unsigned long)addr >= KSEG2;
23}
24
25static inline unsigned long virt_to_phys_from_pte(void *addr)
26{
27 pgd_t *pgd;
28 pud_t *pud;
29 pmd_t *pmd;
30 pte_t *ptep, pte;
31
32 unsigned long virt_addr = (unsigned long)addr;
33 unsigned long phys_addr = 0UL;
34
35 /* get the page global directory. */
36 pgd = pgd_offset_k(virt_addr);
37
38 if (!pgd_none(*pgd)) {
39 /* get the page upper directory */
40 pud = pud_offset(pgd, virt_addr);
41 if (!pud_none(*pud)) {
42 /* get the page middle directory */
43 pmd = pmd_offset(pud, virt_addr);
44 if (!pmd_none(*pmd)) {
45 /* get a pointer to the page table entry */
46 ptep = pte_offset(pmd, virt_addr);
47 pte = *ptep;
48 /* check for a valid page */
49 if (pte_present(pte)) {
50 /* get the physical address the page is
51 * refering to */
52 phys_addr = (unsigned long)
53 page_to_phys(pte_page(pte));
54 /* add the offset within the page */
55 phys_addr |= (virt_addr & ~PAGE_MASK);
56 }
57 }
58 }
59 }
60
61 return phys_addr;
62}
63
64static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
65 size_t size)
66{
67 if (is_kseg2(addr))
68 return phys_to_bus(virt_to_phys_from_pte(addr));
69 else
70 return phys_to_bus(virt_to_phys(addr));
71}
72
73static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
74 struct page *page)
75{
76 return phys_to_bus(page_to_phys(page));
77}
78
79static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
80 dma_addr_t dma_addr)
81{
82 return bus_to_phys(dma_addr);
83}
84
85static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
86 size_t size, enum dma_data_direction direction)
87{
88}
89
90static inline int plat_dma_supported(struct device *dev, u64 mask)
91{
92 /*
93 * we fall back to GFP_DMA when the mask isn't all 1s,
94 * so we can't guarantee allocations that must be
95 * within a tighter range than GFP_DMA..
96 */
97 if (mask < DMA_BIT_MASK(24))
98 return 0;
99
100 return 1;
101}
102
103static inline void plat_extra_sync_for_device(struct device *dev)
104{
105 return;
106}
107
108static inline int plat_dma_mapping_error(struct device *dev,
109 dma_addr_t dma_addr)
110{
111 return 0;
112}
113
114static inline int plat_device_is_coherent(struct device *dev)
115{
116 return 0;
117}
118
119#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
new file mode 100644
index 000000000000..4fd652ceb52a
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -0,0 +1,253 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21
22/*
23 * Defines for all of the interrupt lines
24 */
25
26/* Definitions for backward compatibility */
27#define kIrq_Uart1 irq_uart1
28
29#define ibase 0
30
31/*------------- Register: int_stat_3 */
32/* 126 unused (bit 31) */
33#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39 * Interrupt */
40#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42 * -- Ored by glue logic inside
43 * SPARC ILC (see
44 * INT_MEM_PROT_STAT, below,
45 * for individual interrupts)
46 */
47/* 118 unused (bit 22) */
48#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside
57 * SPARC ILC (see
58 * INT_MAILBOX_STAT, below, for
59 * individual interrupts) */
60#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63 * Status 3 */
64#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65 * Status 3 */
66#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67 * Interrupt */
68#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69 * Interrupt */
70#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71 * Interrupt */
72#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73 * Interrupt */
74#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75 * Interrupt */
76#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77 * Interrupt */
78#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80 * Interrupt */
81#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87/*------------- Register: int_stat_2 */
88#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90#define irq_timer2 (ibase+93) /* Programmable Timer
91 * Interrupt 2 */
92#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108 * Host module) */
109#define irq_pod (ibase+78) /* POD Interrupt */
110#define irq_slave_usb (ibase+77) /* Slave USB */
111#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */
139#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */
147#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148 * Interrupt */
149#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150 * Interrupt */
151#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152 * (Chans 63-32) */
153#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154 * (Chans 31-0) */
155#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156 * (Chans 63-32) */
157#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158 * (Chans 31-0) */
159#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160 * Interrupt */
161#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163 * Interrupt */
164#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */
173#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174 * (PEI) */
175#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176 * detect */
177#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178/*------------- Register: int_stat_0 */
179#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180 * Module */
181#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182 * Module */
183#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184 * (chan 3) Transmission
185 * Completed OK */
186#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187 * Transmission Completed OK */
188#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189 * (chan 1) Transmission
190 * Completed OK */
191#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192 * (chan 3)Transmission
193 * completed with Errors. */
194#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195 * Transmission completed with
196 * Errors. */
197#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198 * (chan 1) Transmission
199 * completed with Errors */
200#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201 * for N times. Aloha retry
202 * timeout for channel 3. */
203#define irq_timer1 (ibase+22) /* Programmable Timer
204 * Interrupt */
205#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207#define irq_spi (ibase+19) /* SPI Module Interrupt */
208#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210 * Splice Detect Interrupt */
211#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212 * Interrupt */
213#define irq_uart1 (ibase+15) /* UART Interrupt */
214#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */
220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference -
228 * every 3ms when forward Mbits
229 * and forward slot control
230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference -
233 * delayed from forward mark by
234 * the ranging delay plus a
235 * fixed amount. When reverse
236 * Mbits and reverse slot
237 * control bytes are updated.
238 * Occurs every 3ms for 3.0M and
239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream
241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed
246 * or Slotted aloha verify for
247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation
250 * increment completed for
251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
new file mode 100644
index 000000000000..e6276d5146e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -0,0 +1,90 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * Portions Copyright (C) Cisco Systems, Inc.
8 */
9#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10#define __ASM_MACH_POWERTV_IOREMAP_H
11
12#include <linux/types.h>
13
14#define LOW_MEM_BOUNDARY_PHYS 0x20000000
15#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1))
16
17/*
18 * The bus addresses are different than the physical addresses that
19 * the processor sees by an offset. This offset varies by ASIC
20 * version. Define a variable to hold the offset and some macros to
21 * make the conversion simpler. */
22extern unsigned long phys_to_bus_offset;
23
24#ifdef CONFIG_HIGHMEM
25#define MEM_GAP_PHYS 0x60000000
26/*
27 * TODO: We will use the hard code for conversion between physical and
28 * bus until the bootloader releases their device tree to us.
29 */
30#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
31 ((x) + phys_to_bus_offset) : (x))
32#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
33 ((x) - phys_to_bus_offset) : (x))
34#else
35#define phys_to_bus(x) ((x) + phys_to_bus_offset)
36#define bus_to_phys(x) ((x) - phys_to_bus_offset)
37#endif
38
39/*
40 * Determine whether the address we are given is for an ASIC device
41 * Params: addr Address to check
42 * Returns: Zero if the address is not for ASIC devices, non-zero
43 * if it is.
44 */
45static inline int asic_is_device_addr(phys_t addr)
46{
47 return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
48}
49
50/*
51 * Determine whether the address we are given is external RAM mappable
52 * into KSEG1.
53 * Params: addr Address to check
54 * Returns: Zero if the address is not for external RAM and
55 */
56static inline int asic_is_lowmem_ram_addr(phys_t addr)
57{
58 /*
59 * The RAM always starts at the following address in the processor's
60 * physical address space
61 */
62 static const phys_t phys_ram_base = 0x10000000;
63 phys_t bus_ram_base;
64
65 bus_ram_base = phys_to_bus_offset + phys_ram_base;
66
67 return addr >= bus_ram_base &&
68 addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
69}
70
71/*
72 * Allow physical addresses to be fixed up to help peripherals located
73 * outside the low 32-bit range -- generic pass-through version.
74 */
75static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
76{
77 return phys_addr;
78}
79
80static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
81 unsigned long flags)
82{
83 return NULL;
84}
85
86static inline int plat_iounmap(const volatile void __iomem *addr)
87{
88 return 0;
89}
90#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
new file mode 100644
index 000000000000..4bd5d0c61a91
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/irq.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_IRQ_H
20#define _ASM_MACH_POWERTV_IRQ_H
21#include <asm/mach-powertv/interrupts.h>
22
23#define MIPS_CPU_IRQ_BASE ibase
24#define NR_IRQS 127
25#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
new file mode 100644
index 000000000000..6f3e9a0fcf8c
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18/*
19 * Local definitions for the powertv PCI code
20 */
21
22#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23#define _POWERTV_PCI_POWERTV_PCI_H_
24extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25extern int asic_pcie_init(void);
26extern int asic_pcie_init(void);
27
28extern int log_level;
29#endif
diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 1f82180c1598..7ac05ecc512b 100644
--- a/arch/mips/include/asm/mach-excite/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -3,10 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * This version for the PowerTV platform copied from the Malta version.
7 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
7 */ 10 */
8#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H 11#ifndef __ASM_MACH_POWERTV_WAR_H
9#define __ASM_MIPS_MACH_EXCITE_WAR_H 12#define __ASM_MACH_POWERTV_WAR_H
10 13
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 14#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 15#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -14,12 +17,12 @@
14#define R5432_CP0_INTERRUPT_WAR 0 17#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0 18#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0 19#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0 20#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0 21#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 22#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1 23#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 24#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 25#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 26#define MIPS34K_MISSED_ITLB_WAR 0
24 27
25#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ 28#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 7950ef4f032c..743385d7b5f2 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -16,7 +16,11 @@
16#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ 16#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
17 defined(CONFIG_SB1_PASS_2_WORKAROUNDS) 17 defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
18 18
19#define BCM1250_M3_WAR 1 19#ifndef __ASSEMBLY__
20extern int sb1250_m3_workaround_needed(void);
21#endif
22
23#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
20#define SIBYTE_1956_WAR 1 24#define SIBYTE_1956_WAR 1
21 25
22#else 26#else
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a576ce044c3c..d14e2adc4be5 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -26,11 +26,6 @@
26/* offsets from base register */ 26/* offsets from base register */
27#define BONITO(x) (x) 27#define BONITO(x) (x)
28 28
29#elif defined(CONFIG_LEMOTE_FULOONG2E)
30
31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32#define BONITO_IRQ_BASE 32
33
34#else 29#else
35 30
36/* 31/*
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index a581d60cbcc2..c6e3c93ce7c7 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -135,6 +135,12 @@
135#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 135#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
136 136
137/* 137/*
138 * Bits 18 - 20 of the FPU Status Register will be read as 0,
139 * and should be written as zero.
140 */
141#define FPU_CSR_RSVD 0x001c0000
142
143/*
138 * X the exception cause indicator 144 * X the exception cause indicator
139 * E the exception enable 145 * E the exception enable
140 * S the sticky/flag bit 146 * S the sticky/flag bit
@@ -161,7 +167,8 @@
161#define FPU_CSR_UDF_S 0x00000008 167#define FPU_CSR_UDF_S 0x00000008
162#define FPU_CSR_INE_S 0x00000004 168#define FPU_CSR_INE_S 0x00000004
163 169
164/* rounding mode */ 170/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
171#define FPU_CSR_RM 0x00000003
165#define FPU_CSR_RN 0x0 /* nearest */ 172#define FPU_CSR_RN 0x0 /* nearest */
166#define FPU_CSR_RZ 0x1 /* towards zero */ 173#define FPU_CSR_RZ 0x1 /* towards zero */
167#define FPU_CSR_RU 0x2 /* towards +Infinity */ 174#define FPU_CSR_RU 0x2 /* towards +Infinity */
@@ -251,6 +258,14 @@
251#define PL_256M 28 258#define PL_256M 28
252 259
253/* 260/*
261 * PageGrain bits
262 */
263#define PG_RIE (_ULCAST_(1) << 31)
264#define PG_XIE (_ULCAST_(1) << 30)
265#define PG_ELPA (_ULCAST_(1) << 29)
266#define PG_ESP (_ULCAST_(1) << 28)
267
268/*
254 * R4x00 interrupt enable / cause bits 269 * R4x00 interrupt enable / cause bits
255 */ 270 */
256#define IE_SW0 (_ULCAST_(1) << 8) 271#define IE_SW0 (_ULCAST_(1) << 8)
@@ -406,6 +421,16 @@
406#define ST0_XX 0x80000000 /* MIPS IV naming */ 421#define ST0_XX 0x80000000 /* MIPS IV naming */
407 422
408/* 423/*
424 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
425 *
426 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
427 */
428#define INTCTLB_IPPCI 26
429#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
430#define INTCTLB_IPTI 29
431#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
432
433/*
409 * Bitfields and bit numbers in the coprocessor 0 cause register. 434 * Bitfields and bit numbers in the coprocessor 0 cause register.
410 * 435 *
411 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 436 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
@@ -434,6 +459,8 @@
434#define CAUSEF_IV (_ULCAST_(1) << 23) 459#define CAUSEF_IV (_ULCAST_(1) << 23)
435#define CAUSEB_CE 28 460#define CAUSEB_CE 28
436#define CAUSEF_CE (_ULCAST_(3) << 28) 461#define CAUSEF_CE (_ULCAST_(3) << 28)
462#define CAUSEB_TI 30
463#define CAUSEF_TI (_ULCAST_(1) << 30)
437#define CAUSEB_BD 31 464#define CAUSEB_BD 31
438#define CAUSEF_BD (_ULCAST_(1) << 31) 465#define CAUSEF_BD (_ULCAST_(1) << 31)
439 466
@@ -564,6 +591,10 @@
564#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 591#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
565#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 592#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
566 593
594#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
595#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
596#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
597
567#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 598#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
568 599
569#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 600#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
@@ -814,6 +845,9 @@ do { \
814#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 845#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
815#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 846#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
816 847
848#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
849#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
850
817#define read_c0_wired() __read_32bit_c0_register($6, 0) 851#define read_c0_wired() __read_32bit_c0_register($6, 0)
818#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 852#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
819 853
diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h
index 4063edd79623..c436138945a8 100644
--- a/arch/mips/include/asm/mmu.h
+++ b/arch/mips/include/asm/mmu.h
@@ -1,6 +1,9 @@
1#ifndef __ASM_MMU_H 1#ifndef __ASM_MMU_H
2#define __ASM_MMU_H 2#define __ASM_MMU_H
3 3
4typedef unsigned long mm_context_t[NR_CPUS]; 4typedef struct {
5 unsigned long asid[NR_CPUS];
6 void *vdso;
7} mm_context_t;
5 8
6#endif /* __ASM_MMU_H */ 9#endif /* __ASM_MMU_H */
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 6083db586500..d9592733a7ba 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -24,6 +24,33 @@
24#endif /* SMTC */ 24#endif /* SMTC */
25#include <asm-generic/mm_hooks.h> 25#include <asm-generic/mm_hooks.h>
26 26
27#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30 tlbmiss_handler_setup_pgd((unsigned long)(pgd))
31
32static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
33{
34 /* Check for swapper_pg_dir and convert to physical address. */
35 if ((pgd & CKSEG3) == CKSEG0)
36 pgd = CPHYSADDR(pgd);
37 write_c0_context(pgd << 11);
38}
39
40#define TLBMISS_HANDLER_SETUP() \
41 do { \
42 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
43 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
44 } while (0)
45
46
47static inline unsigned long get_current_pgd(void)
48{
49 return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
50}
51
52#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
53
27/* 54/*
28 * For the fast tlb miss handlers, we keep a per cpu array of pointers 55 * For the fast tlb miss handlers, we keep a per cpu array of pointers
29 * to the current pgd for each processor. Also, the proc. id is stuffed 56 * to the current pgd for each processor. Also, the proc. id is stuffed
@@ -46,7 +73,7 @@ extern unsigned long pgd_current[];
46 back_to_back_c0_hazard(); \ 73 back_to_back_c0_hazard(); \
47 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 74 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
48#endif 75#endif
49 76#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
50#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 77#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
51 78
52#define ASID_INC 0x40 79#define ASID_INC 0x40
@@ -77,7 +104,7 @@ extern unsigned long smtc_asid_mask;
77 104
78#endif 105#endif
79 106
80#define cpu_context(cpu, mm) ((mm)->context[cpu]) 107#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
81#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 108#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
82#define asid_cache(cpu) (cpu_data[cpu].asid_cache) 109#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
83 110
diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h
index 7989b9ffc1d2..d92406ae2841 100644
--- a/arch/mips/include/asm/msc01_ic.h
+++ b/arch/mips/include/asm/msc01_ic.h
@@ -145,4 +145,3 @@ extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_i
145extern void ll_msc_irq(void); 145extern void ll_msc_irq(void);
146 146
147#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ 147#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
148
diff --git a/arch/mips/include/asm/nile4.h b/arch/mips/include/asm/nile4.h
index c3ca959aa4d9..af0e51a9f68a 100644
--- a/arch/mips/include/asm/nile4.h
+++ b/arch/mips/include/asm/nile4.h
@@ -307,4 +307,3 @@ extern u8 nile4_i8259_iack(void);
307extern void nile4_dump_irq_status(void); /* Debug */ 307extern void nile4_dump_irq_status(void); /* Debug */
308 308
309#endif 309#endif
310
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
new file mode 100644
index 000000000000..ec94b9ab7be1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -0,0 +1,1194 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_AGL_DEFS_H__
29#define __CVMX_AGL_DEFS_H__
30
31#define CVMX_AGL_GMX_BAD_REG \
32 CVMX_ADD_IO_SEG(0x00011800E0000518ull)
33#define CVMX_AGL_GMX_BIST \
34 CVMX_ADD_IO_SEG(0x00011800E0000400ull)
35#define CVMX_AGL_GMX_DRV_CTL \
36 CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
37#define CVMX_AGL_GMX_INF_MODE \
38 CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
39#define CVMX_AGL_GMX_PRTX_CFG(offset) \
40 CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
41#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
42 CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
43#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
44 CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
45#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
46 CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
47#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
48 CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
49#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
50 CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
51#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
52 CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
53#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
54 CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
55#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
56 CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
57#define CVMX_AGL_GMX_RXX_DECISION(offset) \
58 CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
59#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
60 CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
61#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
62 CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
63#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
64 CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
65#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
66 CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
67#define CVMX_AGL_GMX_RXX_IFG(offset) \
68 CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
69#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
70 CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
71#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
72 CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
73#define CVMX_AGL_GMX_RXX_JABBER(offset) \
74 CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
75#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
76 CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
77#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
78 CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
79#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
80 CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
81#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
82 CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
83#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
84 CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
85#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
86 CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
87#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
88 CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
89#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
90 CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
91#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
92 CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
93#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
94 CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
95#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
96 CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
97#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
98 CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
99#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
100 CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
101#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
102 CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
103#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
104 CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
105#define CVMX_AGL_GMX_RX_PRT_INFO \
106 CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
107#define CVMX_AGL_GMX_RX_TX_STATUS \
108 CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
109#define CVMX_AGL_GMX_SMACX(offset) \
110 CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
111#define CVMX_AGL_GMX_STAT_BP \
112 CVMX_ADD_IO_SEG(0x00011800E0000520ull)
113#define CVMX_AGL_GMX_TXX_APPEND(offset) \
114 CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
115#define CVMX_AGL_GMX_TXX_CTL(offset) \
116 CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
117#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
118 CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
119#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
120 CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
121#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
122 CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
123#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
124 CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
125#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
126 CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
127#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
128 CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
129#define CVMX_AGL_GMX_TXX_STAT0(offset) \
130 CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
131#define CVMX_AGL_GMX_TXX_STAT1(offset) \
132 CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
133#define CVMX_AGL_GMX_TXX_STAT2(offset) \
134 CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
135#define CVMX_AGL_GMX_TXX_STAT3(offset) \
136 CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
137#define CVMX_AGL_GMX_TXX_STAT4(offset) \
138 CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
139#define CVMX_AGL_GMX_TXX_STAT5(offset) \
140 CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
141#define CVMX_AGL_GMX_TXX_STAT6(offset) \
142 CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
143#define CVMX_AGL_GMX_TXX_STAT7(offset) \
144 CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
145#define CVMX_AGL_GMX_TXX_STAT8(offset) \
146 CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
147#define CVMX_AGL_GMX_TXX_STAT9(offset) \
148 CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
149#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
150 CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
151#define CVMX_AGL_GMX_TXX_THRESH(offset) \
152 CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
153#define CVMX_AGL_GMX_TX_BP \
154 CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
155#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
156 CVMX_ADD_IO_SEG(0x00011800E0000498ull)
157#define CVMX_AGL_GMX_TX_IFG \
158 CVMX_ADD_IO_SEG(0x00011800E0000488ull)
159#define CVMX_AGL_GMX_TX_INT_EN \
160 CVMX_ADD_IO_SEG(0x00011800E0000508ull)
161#define CVMX_AGL_GMX_TX_INT_REG \
162 CVMX_ADD_IO_SEG(0x00011800E0000500ull)
163#define CVMX_AGL_GMX_TX_JAM \
164 CVMX_ADD_IO_SEG(0x00011800E0000490ull)
165#define CVMX_AGL_GMX_TX_LFSR \
166 CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
167#define CVMX_AGL_GMX_TX_OVR_BP \
168 CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
169#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
170 CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
171#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
172 CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
173
174union cvmx_agl_gmx_bad_reg {
175 uint64_t u64;
176 struct cvmx_agl_gmx_bad_reg_s {
177 uint64_t reserved_38_63:26;
178 uint64_t txpsh1:1;
179 uint64_t txpop1:1;
180 uint64_t ovrflw1:1;
181 uint64_t txpsh:1;
182 uint64_t txpop:1;
183 uint64_t ovrflw:1;
184 uint64_t reserved_27_31:5;
185 uint64_t statovr:1;
186 uint64_t reserved_23_25:3;
187 uint64_t loststat:1;
188 uint64_t reserved_4_21:18;
189 uint64_t out_ovr:2;
190 uint64_t reserved_0_1:2;
191 } s;
192 struct cvmx_agl_gmx_bad_reg_s cn52xx;
193 struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
194 struct cvmx_agl_gmx_bad_reg_cn56xx {
195 uint64_t reserved_35_63:29;
196 uint64_t txpsh:1;
197 uint64_t txpop:1;
198 uint64_t ovrflw:1;
199 uint64_t reserved_27_31:5;
200 uint64_t statovr:1;
201 uint64_t reserved_23_25:3;
202 uint64_t loststat:1;
203 uint64_t reserved_3_21:19;
204 uint64_t out_ovr:1;
205 uint64_t reserved_0_1:2;
206 } cn56xx;
207 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
208};
209
210union cvmx_agl_gmx_bist {
211 uint64_t u64;
212 struct cvmx_agl_gmx_bist_s {
213 uint64_t reserved_10_63:54;
214 uint64_t status:10;
215 } s;
216 struct cvmx_agl_gmx_bist_s cn52xx;
217 struct cvmx_agl_gmx_bist_s cn52xxp1;
218 struct cvmx_agl_gmx_bist_s cn56xx;
219 struct cvmx_agl_gmx_bist_s cn56xxp1;
220};
221
222union cvmx_agl_gmx_drv_ctl {
223 uint64_t u64;
224 struct cvmx_agl_gmx_drv_ctl_s {
225 uint64_t reserved_49_63:15;
226 uint64_t byp_en1:1;
227 uint64_t reserved_45_47:3;
228 uint64_t pctl1:5;
229 uint64_t reserved_37_39:3;
230 uint64_t nctl1:5;
231 uint64_t reserved_17_31:15;
232 uint64_t byp_en:1;
233 uint64_t reserved_13_15:3;
234 uint64_t pctl:5;
235 uint64_t reserved_5_7:3;
236 uint64_t nctl:5;
237 } s;
238 struct cvmx_agl_gmx_drv_ctl_s cn52xx;
239 struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
240 struct cvmx_agl_gmx_drv_ctl_cn56xx {
241 uint64_t reserved_17_63:47;
242 uint64_t byp_en:1;
243 uint64_t reserved_13_15:3;
244 uint64_t pctl:5;
245 uint64_t reserved_5_7:3;
246 uint64_t nctl:5;
247 } cn56xx;
248 struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
249};
250
251union cvmx_agl_gmx_inf_mode {
252 uint64_t u64;
253 struct cvmx_agl_gmx_inf_mode_s {
254 uint64_t reserved_2_63:62;
255 uint64_t en:1;
256 uint64_t reserved_0_0:1;
257 } s;
258 struct cvmx_agl_gmx_inf_mode_s cn52xx;
259 struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
260 struct cvmx_agl_gmx_inf_mode_s cn56xx;
261 struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
262};
263
264union cvmx_agl_gmx_prtx_cfg {
265 uint64_t u64;
266 struct cvmx_agl_gmx_prtx_cfg_s {
267 uint64_t reserved_6_63:58;
268 uint64_t tx_en:1;
269 uint64_t rx_en:1;
270 uint64_t slottime:1;
271 uint64_t duplex:1;
272 uint64_t speed:1;
273 uint64_t en:1;
274 } s;
275 struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
276 struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
277 struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
278 struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
279};
280
281union cvmx_agl_gmx_rxx_adr_cam0 {
282 uint64_t u64;
283 struct cvmx_agl_gmx_rxx_adr_cam0_s {
284 uint64_t adr:64;
285 } s;
286 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
287 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
288 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
289 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
290};
291
292union cvmx_agl_gmx_rxx_adr_cam1 {
293 uint64_t u64;
294 struct cvmx_agl_gmx_rxx_adr_cam1_s {
295 uint64_t adr:64;
296 } s;
297 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
298 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
299 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
300 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
301};
302
303union cvmx_agl_gmx_rxx_adr_cam2 {
304 uint64_t u64;
305 struct cvmx_agl_gmx_rxx_adr_cam2_s {
306 uint64_t adr:64;
307 } s;
308 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
309 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
310 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
311 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
312};
313
314union cvmx_agl_gmx_rxx_adr_cam3 {
315 uint64_t u64;
316 struct cvmx_agl_gmx_rxx_adr_cam3_s {
317 uint64_t adr:64;
318 } s;
319 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
320 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
321 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
322 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
323};
324
325union cvmx_agl_gmx_rxx_adr_cam4 {
326 uint64_t u64;
327 struct cvmx_agl_gmx_rxx_adr_cam4_s {
328 uint64_t adr:64;
329 } s;
330 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
331 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
332 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
333 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
334};
335
336union cvmx_agl_gmx_rxx_adr_cam5 {
337 uint64_t u64;
338 struct cvmx_agl_gmx_rxx_adr_cam5_s {
339 uint64_t adr:64;
340 } s;
341 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
342 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
343 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
344 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
345};
346
347union cvmx_agl_gmx_rxx_adr_cam_en {
348 uint64_t u64;
349 struct cvmx_agl_gmx_rxx_adr_cam_en_s {
350 uint64_t reserved_8_63:56;
351 uint64_t en:8;
352 } s;
353 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
354 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
355 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
356 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
357};
358
359union cvmx_agl_gmx_rxx_adr_ctl {
360 uint64_t u64;
361 struct cvmx_agl_gmx_rxx_adr_ctl_s {
362 uint64_t reserved_4_63:60;
363 uint64_t cam_mode:1;
364 uint64_t mcst:2;
365 uint64_t bcst:1;
366 } s;
367 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
368 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
369 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
370 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
371};
372
373union cvmx_agl_gmx_rxx_decision {
374 uint64_t u64;
375 struct cvmx_agl_gmx_rxx_decision_s {
376 uint64_t reserved_5_63:59;
377 uint64_t cnt:5;
378 } s;
379 struct cvmx_agl_gmx_rxx_decision_s cn52xx;
380 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
381 struct cvmx_agl_gmx_rxx_decision_s cn56xx;
382 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
383};
384
385union cvmx_agl_gmx_rxx_frm_chk {
386 uint64_t u64;
387 struct cvmx_agl_gmx_rxx_frm_chk_s {
388 uint64_t reserved_9_63:55;
389 uint64_t skperr:1;
390 uint64_t rcverr:1;
391 uint64_t lenerr:1;
392 uint64_t alnerr:1;
393 uint64_t fcserr:1;
394 uint64_t jabber:1;
395 uint64_t maxerr:1;
396 uint64_t reserved_1_1:1;
397 uint64_t minerr:1;
398 } s;
399 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
400 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
401 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
402 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
403};
404
405union cvmx_agl_gmx_rxx_frm_ctl {
406 uint64_t u64;
407 struct cvmx_agl_gmx_rxx_frm_ctl_s {
408 uint64_t reserved_10_63:54;
409 uint64_t pre_align:1;
410 uint64_t pad_len:1;
411 uint64_t vlan_len:1;
412 uint64_t pre_free:1;
413 uint64_t ctl_smac:1;
414 uint64_t ctl_mcst:1;
415 uint64_t ctl_bck:1;
416 uint64_t ctl_drp:1;
417 uint64_t pre_strp:1;
418 uint64_t pre_chk:1;
419 } s;
420 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
421 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
422 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
423 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
424};
425
426union cvmx_agl_gmx_rxx_frm_max {
427 uint64_t u64;
428 struct cvmx_agl_gmx_rxx_frm_max_s {
429 uint64_t reserved_16_63:48;
430 uint64_t len:16;
431 } s;
432 struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
433 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
434 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
435 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
436};
437
438union cvmx_agl_gmx_rxx_frm_min {
439 uint64_t u64;
440 struct cvmx_agl_gmx_rxx_frm_min_s {
441 uint64_t reserved_16_63:48;
442 uint64_t len:16;
443 } s;
444 struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
445 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
446 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
447 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
448};
449
450union cvmx_agl_gmx_rxx_ifg {
451 uint64_t u64;
452 struct cvmx_agl_gmx_rxx_ifg_s {
453 uint64_t reserved_4_63:60;
454 uint64_t ifg:4;
455 } s;
456 struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
457 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
458 struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
459 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
460};
461
462union cvmx_agl_gmx_rxx_int_en {
463 uint64_t u64;
464 struct cvmx_agl_gmx_rxx_int_en_s {
465 uint64_t reserved_20_63:44;
466 uint64_t pause_drp:1;
467 uint64_t reserved_16_18:3;
468 uint64_t ifgerr:1;
469 uint64_t coldet:1;
470 uint64_t falerr:1;
471 uint64_t rsverr:1;
472 uint64_t pcterr:1;
473 uint64_t ovrerr:1;
474 uint64_t reserved_9_9:1;
475 uint64_t skperr:1;
476 uint64_t rcverr:1;
477 uint64_t lenerr:1;
478 uint64_t alnerr:1;
479 uint64_t fcserr:1;
480 uint64_t jabber:1;
481 uint64_t maxerr:1;
482 uint64_t reserved_1_1:1;
483 uint64_t minerr:1;
484 } s;
485 struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
486 struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
487 struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
488 struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
489};
490
491union cvmx_agl_gmx_rxx_int_reg {
492 uint64_t u64;
493 struct cvmx_agl_gmx_rxx_int_reg_s {
494 uint64_t reserved_20_63:44;
495 uint64_t pause_drp:1;
496 uint64_t reserved_16_18:3;
497 uint64_t ifgerr:1;
498 uint64_t coldet:1;
499 uint64_t falerr:1;
500 uint64_t rsverr:1;
501 uint64_t pcterr:1;
502 uint64_t ovrerr:1;
503 uint64_t reserved_9_9:1;
504 uint64_t skperr:1;
505 uint64_t rcverr:1;
506 uint64_t lenerr:1;
507 uint64_t alnerr:1;
508 uint64_t fcserr:1;
509 uint64_t jabber:1;
510 uint64_t maxerr:1;
511 uint64_t reserved_1_1:1;
512 uint64_t minerr:1;
513 } s;
514 struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
515 struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
516 struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
517 struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
518};
519
520union cvmx_agl_gmx_rxx_jabber {
521 uint64_t u64;
522 struct cvmx_agl_gmx_rxx_jabber_s {
523 uint64_t reserved_16_63:48;
524 uint64_t cnt:16;
525 } s;
526 struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
527 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
528 struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
529 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
530};
531
532union cvmx_agl_gmx_rxx_pause_drop_time {
533 uint64_t u64;
534 struct cvmx_agl_gmx_rxx_pause_drop_time_s {
535 uint64_t reserved_16_63:48;
536 uint64_t status:16;
537 } s;
538 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
539 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
540 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
541 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
542};
543
544union cvmx_agl_gmx_rxx_stats_ctl {
545 uint64_t u64;
546 struct cvmx_agl_gmx_rxx_stats_ctl_s {
547 uint64_t reserved_1_63:63;
548 uint64_t rd_clr:1;
549 } s;
550 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
551 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
552 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
553 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
554};
555
556union cvmx_agl_gmx_rxx_stats_octs {
557 uint64_t u64;
558 struct cvmx_agl_gmx_rxx_stats_octs_s {
559 uint64_t reserved_48_63:16;
560 uint64_t cnt:48;
561 } s;
562 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
563 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
564 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
565 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
566};
567
568union cvmx_agl_gmx_rxx_stats_octs_ctl {
569 uint64_t u64;
570 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
571 uint64_t reserved_48_63:16;
572 uint64_t cnt:48;
573 } s;
574 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
575 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
576 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
577 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
578};
579
580union cvmx_agl_gmx_rxx_stats_octs_dmac {
581 uint64_t u64;
582 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
583 uint64_t reserved_48_63:16;
584 uint64_t cnt:48;
585 } s;
586 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
587 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
588 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
589 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
590};
591
592union cvmx_agl_gmx_rxx_stats_octs_drp {
593 uint64_t u64;
594 struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
595 uint64_t reserved_48_63:16;
596 uint64_t cnt:48;
597 } s;
598 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
599 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
600 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
601 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
602};
603
604union cvmx_agl_gmx_rxx_stats_pkts {
605 uint64_t u64;
606 struct cvmx_agl_gmx_rxx_stats_pkts_s {
607 uint64_t reserved_32_63:32;
608 uint64_t cnt:32;
609 } s;
610 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
611 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
612 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
613 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
614};
615
616union cvmx_agl_gmx_rxx_stats_pkts_bad {
617 uint64_t u64;
618 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
619 uint64_t reserved_32_63:32;
620 uint64_t cnt:32;
621 } s;
622 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
623 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
624 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
625 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
626};
627
628union cvmx_agl_gmx_rxx_stats_pkts_ctl {
629 uint64_t u64;
630 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
631 uint64_t reserved_32_63:32;
632 uint64_t cnt:32;
633 } s;
634 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
635 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
636 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
637 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
638};
639
640union cvmx_agl_gmx_rxx_stats_pkts_dmac {
641 uint64_t u64;
642 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
643 uint64_t reserved_32_63:32;
644 uint64_t cnt:32;
645 } s;
646 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
647 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
648 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
649 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
650};
651
652union cvmx_agl_gmx_rxx_stats_pkts_drp {
653 uint64_t u64;
654 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
655 uint64_t reserved_32_63:32;
656 uint64_t cnt:32;
657 } s;
658 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
659 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
660 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
661 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
662};
663
664union cvmx_agl_gmx_rxx_udd_skp {
665 uint64_t u64;
666 struct cvmx_agl_gmx_rxx_udd_skp_s {
667 uint64_t reserved_9_63:55;
668 uint64_t fcssel:1;
669 uint64_t reserved_7_7:1;
670 uint64_t len:7;
671 } s;
672 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
673 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
674 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
675 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
676};
677
678union cvmx_agl_gmx_rx_bp_dropx {
679 uint64_t u64;
680 struct cvmx_agl_gmx_rx_bp_dropx_s {
681 uint64_t reserved_6_63:58;
682 uint64_t mark:6;
683 } s;
684 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
685 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
686 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
687 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
688};
689
690union cvmx_agl_gmx_rx_bp_offx {
691 uint64_t u64;
692 struct cvmx_agl_gmx_rx_bp_offx_s {
693 uint64_t reserved_6_63:58;
694 uint64_t mark:6;
695 } s;
696 struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
697 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
698 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
699 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
700};
701
702union cvmx_agl_gmx_rx_bp_onx {
703 uint64_t u64;
704 struct cvmx_agl_gmx_rx_bp_onx_s {
705 uint64_t reserved_9_63:55;
706 uint64_t mark:9;
707 } s;
708 struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
709 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
710 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
711 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
712};
713
714union cvmx_agl_gmx_rx_prt_info {
715 uint64_t u64;
716 struct cvmx_agl_gmx_rx_prt_info_s {
717 uint64_t reserved_18_63:46;
718 uint64_t drop:2;
719 uint64_t reserved_2_15:14;
720 uint64_t commit:2;
721 } s;
722 struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
723 struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
724 struct cvmx_agl_gmx_rx_prt_info_cn56xx {
725 uint64_t reserved_17_63:47;
726 uint64_t drop:1;
727 uint64_t reserved_1_15:15;
728 uint64_t commit:1;
729 } cn56xx;
730 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
731};
732
733union cvmx_agl_gmx_rx_tx_status {
734 uint64_t u64;
735 struct cvmx_agl_gmx_rx_tx_status_s {
736 uint64_t reserved_6_63:58;
737 uint64_t tx:2;
738 uint64_t reserved_2_3:2;
739 uint64_t rx:2;
740 } s;
741 struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
742 struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
743 struct cvmx_agl_gmx_rx_tx_status_cn56xx {
744 uint64_t reserved_5_63:59;
745 uint64_t tx:1;
746 uint64_t reserved_1_3:3;
747 uint64_t rx:1;
748 } cn56xx;
749 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
750};
751
752union cvmx_agl_gmx_smacx {
753 uint64_t u64;
754 struct cvmx_agl_gmx_smacx_s {
755 uint64_t reserved_48_63:16;
756 uint64_t smac:48;
757 } s;
758 struct cvmx_agl_gmx_smacx_s cn52xx;
759 struct cvmx_agl_gmx_smacx_s cn52xxp1;
760 struct cvmx_agl_gmx_smacx_s cn56xx;
761 struct cvmx_agl_gmx_smacx_s cn56xxp1;
762};
763
764union cvmx_agl_gmx_stat_bp {
765 uint64_t u64;
766 struct cvmx_agl_gmx_stat_bp_s {
767 uint64_t reserved_17_63:47;
768 uint64_t bp:1;
769 uint64_t cnt:16;
770 } s;
771 struct cvmx_agl_gmx_stat_bp_s cn52xx;
772 struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
773 struct cvmx_agl_gmx_stat_bp_s cn56xx;
774 struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
775};
776
777union cvmx_agl_gmx_txx_append {
778 uint64_t u64;
779 struct cvmx_agl_gmx_txx_append_s {
780 uint64_t reserved_4_63:60;
781 uint64_t force_fcs:1;
782 uint64_t fcs:1;
783 uint64_t pad:1;
784 uint64_t preamble:1;
785 } s;
786 struct cvmx_agl_gmx_txx_append_s cn52xx;
787 struct cvmx_agl_gmx_txx_append_s cn52xxp1;
788 struct cvmx_agl_gmx_txx_append_s cn56xx;
789 struct cvmx_agl_gmx_txx_append_s cn56xxp1;
790};
791
792union cvmx_agl_gmx_txx_ctl {
793 uint64_t u64;
794 struct cvmx_agl_gmx_txx_ctl_s {
795 uint64_t reserved_2_63:62;
796 uint64_t xsdef_en:1;
797 uint64_t xscol_en:1;
798 } s;
799 struct cvmx_agl_gmx_txx_ctl_s cn52xx;
800 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
801 struct cvmx_agl_gmx_txx_ctl_s cn56xx;
802 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
803};
804
805union cvmx_agl_gmx_txx_min_pkt {
806 uint64_t u64;
807 struct cvmx_agl_gmx_txx_min_pkt_s {
808 uint64_t reserved_8_63:56;
809 uint64_t min_size:8;
810 } s;
811 struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
812 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
813 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
814 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
815};
816
817union cvmx_agl_gmx_txx_pause_pkt_interval {
818 uint64_t u64;
819 struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
820 uint64_t reserved_16_63:48;
821 uint64_t interval:16;
822 } s;
823 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
824 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
825 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
826 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
827};
828
829union cvmx_agl_gmx_txx_pause_pkt_time {
830 uint64_t u64;
831 struct cvmx_agl_gmx_txx_pause_pkt_time_s {
832 uint64_t reserved_16_63:48;
833 uint64_t time:16;
834 } s;
835 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
836 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
837 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
838 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
839};
840
841union cvmx_agl_gmx_txx_pause_togo {
842 uint64_t u64;
843 struct cvmx_agl_gmx_txx_pause_togo_s {
844 uint64_t reserved_16_63:48;
845 uint64_t time:16;
846 } s;
847 struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
848 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
849 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
850 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
851};
852
853union cvmx_agl_gmx_txx_pause_zero {
854 uint64_t u64;
855 struct cvmx_agl_gmx_txx_pause_zero_s {
856 uint64_t reserved_1_63:63;
857 uint64_t send:1;
858 } s;
859 struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
860 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
861 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
862 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
863};
864
865union cvmx_agl_gmx_txx_soft_pause {
866 uint64_t u64;
867 struct cvmx_agl_gmx_txx_soft_pause_s {
868 uint64_t reserved_16_63:48;
869 uint64_t time:16;
870 } s;
871 struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
872 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
873 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
874 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
875};
876
877union cvmx_agl_gmx_txx_stat0 {
878 uint64_t u64;
879 struct cvmx_agl_gmx_txx_stat0_s {
880 uint64_t xsdef:32;
881 uint64_t xscol:32;
882 } s;
883 struct cvmx_agl_gmx_txx_stat0_s cn52xx;
884 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
885 struct cvmx_agl_gmx_txx_stat0_s cn56xx;
886 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
887};
888
889union cvmx_agl_gmx_txx_stat1 {
890 uint64_t u64;
891 struct cvmx_agl_gmx_txx_stat1_s {
892 uint64_t scol:32;
893 uint64_t mcol:32;
894 } s;
895 struct cvmx_agl_gmx_txx_stat1_s cn52xx;
896 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
897 struct cvmx_agl_gmx_txx_stat1_s cn56xx;
898 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
899};
900
901union cvmx_agl_gmx_txx_stat2 {
902 uint64_t u64;
903 struct cvmx_agl_gmx_txx_stat2_s {
904 uint64_t reserved_48_63:16;
905 uint64_t octs:48;
906 } s;
907 struct cvmx_agl_gmx_txx_stat2_s cn52xx;
908 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
909 struct cvmx_agl_gmx_txx_stat2_s cn56xx;
910 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
911};
912
913union cvmx_agl_gmx_txx_stat3 {
914 uint64_t u64;
915 struct cvmx_agl_gmx_txx_stat3_s {
916 uint64_t reserved_32_63:32;
917 uint64_t pkts:32;
918 } s;
919 struct cvmx_agl_gmx_txx_stat3_s cn52xx;
920 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
921 struct cvmx_agl_gmx_txx_stat3_s cn56xx;
922 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
923};
924
925union cvmx_agl_gmx_txx_stat4 {
926 uint64_t u64;
927 struct cvmx_agl_gmx_txx_stat4_s {
928 uint64_t hist1:32;
929 uint64_t hist0:32;
930 } s;
931 struct cvmx_agl_gmx_txx_stat4_s cn52xx;
932 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
933 struct cvmx_agl_gmx_txx_stat4_s cn56xx;
934 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
935};
936
937union cvmx_agl_gmx_txx_stat5 {
938 uint64_t u64;
939 struct cvmx_agl_gmx_txx_stat5_s {
940 uint64_t hist3:32;
941 uint64_t hist2:32;
942 } s;
943 struct cvmx_agl_gmx_txx_stat5_s cn52xx;
944 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
945 struct cvmx_agl_gmx_txx_stat5_s cn56xx;
946 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
947};
948
949union cvmx_agl_gmx_txx_stat6 {
950 uint64_t u64;
951 struct cvmx_agl_gmx_txx_stat6_s {
952 uint64_t hist5:32;
953 uint64_t hist4:32;
954 } s;
955 struct cvmx_agl_gmx_txx_stat6_s cn52xx;
956 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
957 struct cvmx_agl_gmx_txx_stat6_s cn56xx;
958 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
959};
960
961union cvmx_agl_gmx_txx_stat7 {
962 uint64_t u64;
963 struct cvmx_agl_gmx_txx_stat7_s {
964 uint64_t hist7:32;
965 uint64_t hist6:32;
966 } s;
967 struct cvmx_agl_gmx_txx_stat7_s cn52xx;
968 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
969 struct cvmx_agl_gmx_txx_stat7_s cn56xx;
970 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
971};
972
973union cvmx_agl_gmx_txx_stat8 {
974 uint64_t u64;
975 struct cvmx_agl_gmx_txx_stat8_s {
976 uint64_t mcst:32;
977 uint64_t bcst:32;
978 } s;
979 struct cvmx_agl_gmx_txx_stat8_s cn52xx;
980 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
981 struct cvmx_agl_gmx_txx_stat8_s cn56xx;
982 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
983};
984
985union cvmx_agl_gmx_txx_stat9 {
986 uint64_t u64;
987 struct cvmx_agl_gmx_txx_stat9_s {
988 uint64_t undflw:32;
989 uint64_t ctl:32;
990 } s;
991 struct cvmx_agl_gmx_txx_stat9_s cn52xx;
992 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
993 struct cvmx_agl_gmx_txx_stat9_s cn56xx;
994 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
995};
996
997union cvmx_agl_gmx_txx_stats_ctl {
998 uint64_t u64;
999 struct cvmx_agl_gmx_txx_stats_ctl_s {
1000 uint64_t reserved_1_63:63;
1001 uint64_t rd_clr:1;
1002 } s;
1003 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
1004 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1005 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1006 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1007};
1008
1009union cvmx_agl_gmx_txx_thresh {
1010 uint64_t u64;
1011 struct cvmx_agl_gmx_txx_thresh_s {
1012 uint64_t reserved_6_63:58;
1013 uint64_t cnt:6;
1014 } s;
1015 struct cvmx_agl_gmx_txx_thresh_s cn52xx;
1016 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1017 struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1018 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1019};
1020
1021union cvmx_agl_gmx_tx_bp {
1022 uint64_t u64;
1023 struct cvmx_agl_gmx_tx_bp_s {
1024 uint64_t reserved_2_63:62;
1025 uint64_t bp:2;
1026 } s;
1027 struct cvmx_agl_gmx_tx_bp_s cn52xx;
1028 struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
1029 struct cvmx_agl_gmx_tx_bp_cn56xx {
1030 uint64_t reserved_1_63:63;
1031 uint64_t bp:1;
1032 } cn56xx;
1033 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
1034};
1035
1036union cvmx_agl_gmx_tx_col_attempt {
1037 uint64_t u64;
1038 struct cvmx_agl_gmx_tx_col_attempt_s {
1039 uint64_t reserved_5_63:59;
1040 uint64_t limit:5;
1041 } s;
1042 struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
1043 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
1044 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
1045 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
1046};
1047
1048union cvmx_agl_gmx_tx_ifg {
1049 uint64_t u64;
1050 struct cvmx_agl_gmx_tx_ifg_s {
1051 uint64_t reserved_8_63:56;
1052 uint64_t ifg2:4;
1053 uint64_t ifg1:4;
1054 } s;
1055 struct cvmx_agl_gmx_tx_ifg_s cn52xx;
1056 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
1057 struct cvmx_agl_gmx_tx_ifg_s cn56xx;
1058 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
1059};
1060
1061union cvmx_agl_gmx_tx_int_en {
1062 uint64_t u64;
1063 struct cvmx_agl_gmx_tx_int_en_s {
1064 uint64_t reserved_18_63:46;
1065 uint64_t late_col:2;
1066 uint64_t reserved_14_15:2;
1067 uint64_t xsdef:2;
1068 uint64_t reserved_10_11:2;
1069 uint64_t xscol:2;
1070 uint64_t reserved_4_7:4;
1071 uint64_t undflw:2;
1072 uint64_t reserved_1_1:1;
1073 uint64_t pko_nxa:1;
1074 } s;
1075 struct cvmx_agl_gmx_tx_int_en_s cn52xx;
1076 struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
1077 struct cvmx_agl_gmx_tx_int_en_cn56xx {
1078 uint64_t reserved_17_63:47;
1079 uint64_t late_col:1;
1080 uint64_t reserved_13_15:3;
1081 uint64_t xsdef:1;
1082 uint64_t reserved_9_11:3;
1083 uint64_t xscol:1;
1084 uint64_t reserved_3_7:5;
1085 uint64_t undflw:1;
1086 uint64_t reserved_1_1:1;
1087 uint64_t pko_nxa:1;
1088 } cn56xx;
1089 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
1090};
1091
1092union cvmx_agl_gmx_tx_int_reg {
1093 uint64_t u64;
1094 struct cvmx_agl_gmx_tx_int_reg_s {
1095 uint64_t reserved_18_63:46;
1096 uint64_t late_col:2;
1097 uint64_t reserved_14_15:2;
1098 uint64_t xsdef:2;
1099 uint64_t reserved_10_11:2;
1100 uint64_t xscol:2;
1101 uint64_t reserved_4_7:4;
1102 uint64_t undflw:2;
1103 uint64_t reserved_1_1:1;
1104 uint64_t pko_nxa:1;
1105 } s;
1106 struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
1107 struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
1108 struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1109 uint64_t reserved_17_63:47;
1110 uint64_t late_col:1;
1111 uint64_t reserved_13_15:3;
1112 uint64_t xsdef:1;
1113 uint64_t reserved_9_11:3;
1114 uint64_t xscol:1;
1115 uint64_t reserved_3_7:5;
1116 uint64_t undflw:1;
1117 uint64_t reserved_1_1:1;
1118 uint64_t pko_nxa:1;
1119 } cn56xx;
1120 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
1121};
1122
1123union cvmx_agl_gmx_tx_jam {
1124 uint64_t u64;
1125 struct cvmx_agl_gmx_tx_jam_s {
1126 uint64_t reserved_8_63:56;
1127 uint64_t jam:8;
1128 } s;
1129 struct cvmx_agl_gmx_tx_jam_s cn52xx;
1130 struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
1131 struct cvmx_agl_gmx_tx_jam_s cn56xx;
1132 struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
1133};
1134
1135union cvmx_agl_gmx_tx_lfsr {
1136 uint64_t u64;
1137 struct cvmx_agl_gmx_tx_lfsr_s {
1138 uint64_t reserved_16_63:48;
1139 uint64_t lfsr:16;
1140 } s;
1141 struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
1142 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
1143 struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
1144 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
1145};
1146
1147union cvmx_agl_gmx_tx_ovr_bp {
1148 uint64_t u64;
1149 struct cvmx_agl_gmx_tx_ovr_bp_s {
1150 uint64_t reserved_10_63:54;
1151 uint64_t en:2;
1152 uint64_t reserved_6_7:2;
1153 uint64_t bp:2;
1154 uint64_t reserved_2_3:2;
1155 uint64_t ign_full:2;
1156 } s;
1157 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
1158 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
1159 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1160 uint64_t reserved_9_63:55;
1161 uint64_t en:1;
1162 uint64_t reserved_5_7:3;
1163 uint64_t bp:1;
1164 uint64_t reserved_1_3:3;
1165 uint64_t ign_full:1;
1166 } cn56xx;
1167 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
1168};
1169
1170union cvmx_agl_gmx_tx_pause_pkt_dmac {
1171 uint64_t u64;
1172 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1173 uint64_t reserved_48_63:16;
1174 uint64_t dmac:48;
1175 } s;
1176 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
1177 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
1178 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
1179 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
1180};
1181
1182union cvmx_agl_gmx_tx_pause_pkt_type {
1183 uint64_t u64;
1184 struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1185 uint64_t reserved_16_63:48;
1186 uint64_t type:16;
1187 } s;
1188 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
1189 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
1190 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
1191 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
1192};
1193
1194#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
new file mode 100644
index 000000000000..dab6dca492f9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -0,0 +1,248 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIXX_DEFS_H__
29#define __CVMX_MIXX_DEFS_H__
30
31#define CVMX_MIXX_BIST(offset) \
32 CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
33#define CVMX_MIXX_CTL(offset) \
34 CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
35#define CVMX_MIXX_INTENA(offset) \
36 CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
37#define CVMX_MIXX_IRCNT(offset) \
38 CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
39#define CVMX_MIXX_IRHWM(offset) \
40 CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
41#define CVMX_MIXX_IRING1(offset) \
42 CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
43#define CVMX_MIXX_IRING2(offset) \
44 CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
45#define CVMX_MIXX_ISR(offset) \
46 CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
47#define CVMX_MIXX_ORCNT(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
49#define CVMX_MIXX_ORHWM(offset) \
50 CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
51#define CVMX_MIXX_ORING1(offset) \
52 CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
53#define CVMX_MIXX_ORING2(offset) \
54 CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
55#define CVMX_MIXX_REMCNT(offset) \
56 CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
57
58union cvmx_mixx_bist {
59 uint64_t u64;
60 struct cvmx_mixx_bist_s {
61 uint64_t reserved_4_63:60;
62 uint64_t mrqdat:1;
63 uint64_t ipfdat:1;
64 uint64_t irfdat:1;
65 uint64_t orfdat:1;
66 } s;
67 struct cvmx_mixx_bist_s cn52xx;
68 struct cvmx_mixx_bist_s cn52xxp1;
69 struct cvmx_mixx_bist_s cn56xx;
70 struct cvmx_mixx_bist_s cn56xxp1;
71};
72
73union cvmx_mixx_ctl {
74 uint64_t u64;
75 struct cvmx_mixx_ctl_s {
76 uint64_t reserved_8_63:56;
77 uint64_t crc_strip:1;
78 uint64_t busy:1;
79 uint64_t en:1;
80 uint64_t reset:1;
81 uint64_t lendian:1;
82 uint64_t nbtarb:1;
83 uint64_t mrq_hwm:2;
84 } s;
85 struct cvmx_mixx_ctl_s cn52xx;
86 struct cvmx_mixx_ctl_s cn52xxp1;
87 struct cvmx_mixx_ctl_s cn56xx;
88 struct cvmx_mixx_ctl_s cn56xxp1;
89};
90
91union cvmx_mixx_intena {
92 uint64_t u64;
93 struct cvmx_mixx_intena_s {
94 uint64_t reserved_7_63:57;
95 uint64_t orunena:1;
96 uint64_t irunena:1;
97 uint64_t data_drpena:1;
98 uint64_t ithena:1;
99 uint64_t othena:1;
100 uint64_t ivfena:1;
101 uint64_t ovfena:1;
102 } s;
103 struct cvmx_mixx_intena_s cn52xx;
104 struct cvmx_mixx_intena_s cn52xxp1;
105 struct cvmx_mixx_intena_s cn56xx;
106 struct cvmx_mixx_intena_s cn56xxp1;
107};
108
109union cvmx_mixx_ircnt {
110 uint64_t u64;
111 struct cvmx_mixx_ircnt_s {
112 uint64_t reserved_20_63:44;
113 uint64_t ircnt:20;
114 } s;
115 struct cvmx_mixx_ircnt_s cn52xx;
116 struct cvmx_mixx_ircnt_s cn52xxp1;
117 struct cvmx_mixx_ircnt_s cn56xx;
118 struct cvmx_mixx_ircnt_s cn56xxp1;
119};
120
121union cvmx_mixx_irhwm {
122 uint64_t u64;
123 struct cvmx_mixx_irhwm_s {
124 uint64_t reserved_40_63:24;
125 uint64_t ibplwm:20;
126 uint64_t irhwm:20;
127 } s;
128 struct cvmx_mixx_irhwm_s cn52xx;
129 struct cvmx_mixx_irhwm_s cn52xxp1;
130 struct cvmx_mixx_irhwm_s cn56xx;
131 struct cvmx_mixx_irhwm_s cn56xxp1;
132};
133
134union cvmx_mixx_iring1 {
135 uint64_t u64;
136 struct cvmx_mixx_iring1_s {
137 uint64_t reserved_60_63:4;
138 uint64_t isize:20;
139 uint64_t reserved_36_39:4;
140 uint64_t ibase:33;
141 uint64_t reserved_0_2:3;
142 } s;
143 struct cvmx_mixx_iring1_s cn52xx;
144 struct cvmx_mixx_iring1_s cn52xxp1;
145 struct cvmx_mixx_iring1_s cn56xx;
146 struct cvmx_mixx_iring1_s cn56xxp1;
147};
148
149union cvmx_mixx_iring2 {
150 uint64_t u64;
151 struct cvmx_mixx_iring2_s {
152 uint64_t reserved_52_63:12;
153 uint64_t itlptr:20;
154 uint64_t reserved_20_31:12;
155 uint64_t idbell:20;
156 } s;
157 struct cvmx_mixx_iring2_s cn52xx;
158 struct cvmx_mixx_iring2_s cn52xxp1;
159 struct cvmx_mixx_iring2_s cn56xx;
160 struct cvmx_mixx_iring2_s cn56xxp1;
161};
162
163union cvmx_mixx_isr {
164 uint64_t u64;
165 struct cvmx_mixx_isr_s {
166 uint64_t reserved_7_63:57;
167 uint64_t orun:1;
168 uint64_t irun:1;
169 uint64_t data_drp:1;
170 uint64_t irthresh:1;
171 uint64_t orthresh:1;
172 uint64_t idblovf:1;
173 uint64_t odblovf:1;
174 } s;
175 struct cvmx_mixx_isr_s cn52xx;
176 struct cvmx_mixx_isr_s cn52xxp1;
177 struct cvmx_mixx_isr_s cn56xx;
178 struct cvmx_mixx_isr_s cn56xxp1;
179};
180
181union cvmx_mixx_orcnt {
182 uint64_t u64;
183 struct cvmx_mixx_orcnt_s {
184 uint64_t reserved_20_63:44;
185 uint64_t orcnt:20;
186 } s;
187 struct cvmx_mixx_orcnt_s cn52xx;
188 struct cvmx_mixx_orcnt_s cn52xxp1;
189 struct cvmx_mixx_orcnt_s cn56xx;
190 struct cvmx_mixx_orcnt_s cn56xxp1;
191};
192
193union cvmx_mixx_orhwm {
194 uint64_t u64;
195 struct cvmx_mixx_orhwm_s {
196 uint64_t reserved_20_63:44;
197 uint64_t orhwm:20;
198 } s;
199 struct cvmx_mixx_orhwm_s cn52xx;
200 struct cvmx_mixx_orhwm_s cn52xxp1;
201 struct cvmx_mixx_orhwm_s cn56xx;
202 struct cvmx_mixx_orhwm_s cn56xxp1;
203};
204
205union cvmx_mixx_oring1 {
206 uint64_t u64;
207 struct cvmx_mixx_oring1_s {
208 uint64_t reserved_60_63:4;
209 uint64_t osize:20;
210 uint64_t reserved_36_39:4;
211 uint64_t obase:33;
212 uint64_t reserved_0_2:3;
213 } s;
214 struct cvmx_mixx_oring1_s cn52xx;
215 struct cvmx_mixx_oring1_s cn52xxp1;
216 struct cvmx_mixx_oring1_s cn56xx;
217 struct cvmx_mixx_oring1_s cn56xxp1;
218};
219
220union cvmx_mixx_oring2 {
221 uint64_t u64;
222 struct cvmx_mixx_oring2_s {
223 uint64_t reserved_52_63:12;
224 uint64_t otlptr:20;
225 uint64_t reserved_20_31:12;
226 uint64_t odbell:20;
227 } s;
228 struct cvmx_mixx_oring2_s cn52xx;
229 struct cvmx_mixx_oring2_s cn52xxp1;
230 struct cvmx_mixx_oring2_s cn56xx;
231 struct cvmx_mixx_oring2_s cn56xxp1;
232};
233
234union cvmx_mixx_remcnt {
235 uint64_t u64;
236 struct cvmx_mixx_remcnt_s {
237 uint64_t reserved_52_63:12;
238 uint64_t iremcnt:20;
239 uint64_t reserved_20_31:12;
240 uint64_t oremcnt:20;
241 } s;
242 struct cvmx_mixx_remcnt_s cn52xx;
243 struct cvmx_mixx_remcnt_s cn52xxp1;
244 struct cvmx_mixx_remcnt_s cn56xx;
245 struct cvmx_mixx_remcnt_s cn56xxp1;
246};
247
248#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
new file mode 100644
index 000000000000..9ae45fcbe3e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -0,0 +1,178 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SMIX_DEFS_H__
29#define __CVMX_SMIX_DEFS_H__
30
31#define CVMX_SMIX_CLK(offset) \
32 CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
33#define CVMX_SMIX_CMD(offset) \
34 CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
35#define CVMX_SMIX_EN(offset) \
36 CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
37#define CVMX_SMIX_RD_DAT(offset) \
38 CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
39#define CVMX_SMIX_WR_DAT(offset) \
40 CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
41
42union cvmx_smix_clk {
43 uint64_t u64;
44 struct cvmx_smix_clk_s {
45 uint64_t reserved_25_63:39;
46 uint64_t mode:1;
47 uint64_t reserved_21_23:3;
48 uint64_t sample_hi:5;
49 uint64_t sample_mode:1;
50 uint64_t reserved_14_14:1;
51 uint64_t clk_idle:1;
52 uint64_t preamble:1;
53 uint64_t sample:4;
54 uint64_t phase:8;
55 } s;
56 struct cvmx_smix_clk_cn30xx {
57 uint64_t reserved_21_63:43;
58 uint64_t sample_hi:5;
59 uint64_t reserved_14_15:2;
60 uint64_t clk_idle:1;
61 uint64_t preamble:1;
62 uint64_t sample:4;
63 uint64_t phase:8;
64 } cn30xx;
65 struct cvmx_smix_clk_cn30xx cn31xx;
66 struct cvmx_smix_clk_cn30xx cn38xx;
67 struct cvmx_smix_clk_cn30xx cn38xxp2;
68 struct cvmx_smix_clk_cn50xx {
69 uint64_t reserved_25_63:39;
70 uint64_t mode:1;
71 uint64_t reserved_21_23:3;
72 uint64_t sample_hi:5;
73 uint64_t reserved_14_15:2;
74 uint64_t clk_idle:1;
75 uint64_t preamble:1;
76 uint64_t sample:4;
77 uint64_t phase:8;
78 } cn50xx;
79 struct cvmx_smix_clk_s cn52xx;
80 struct cvmx_smix_clk_cn50xx cn52xxp1;
81 struct cvmx_smix_clk_s cn56xx;
82 struct cvmx_smix_clk_cn50xx cn56xxp1;
83 struct cvmx_smix_clk_cn30xx cn58xx;
84 struct cvmx_smix_clk_cn30xx cn58xxp1;
85};
86
87union cvmx_smix_cmd {
88 uint64_t u64;
89 struct cvmx_smix_cmd_s {
90 uint64_t reserved_18_63:46;
91 uint64_t phy_op:2;
92 uint64_t reserved_13_15:3;
93 uint64_t phy_adr:5;
94 uint64_t reserved_5_7:3;
95 uint64_t reg_adr:5;
96 } s;
97 struct cvmx_smix_cmd_cn30xx {
98 uint64_t reserved_17_63:47;
99 uint64_t phy_op:1;
100 uint64_t reserved_13_15:3;
101 uint64_t phy_adr:5;
102 uint64_t reserved_5_7:3;
103 uint64_t reg_adr:5;
104 } cn30xx;
105 struct cvmx_smix_cmd_cn30xx cn31xx;
106 struct cvmx_smix_cmd_cn30xx cn38xx;
107 struct cvmx_smix_cmd_cn30xx cn38xxp2;
108 struct cvmx_smix_cmd_s cn50xx;
109 struct cvmx_smix_cmd_s cn52xx;
110 struct cvmx_smix_cmd_s cn52xxp1;
111 struct cvmx_smix_cmd_s cn56xx;
112 struct cvmx_smix_cmd_s cn56xxp1;
113 struct cvmx_smix_cmd_cn30xx cn58xx;
114 struct cvmx_smix_cmd_cn30xx cn58xxp1;
115};
116
117union cvmx_smix_en {
118 uint64_t u64;
119 struct cvmx_smix_en_s {
120 uint64_t reserved_1_63:63;
121 uint64_t en:1;
122 } s;
123 struct cvmx_smix_en_s cn30xx;
124 struct cvmx_smix_en_s cn31xx;
125 struct cvmx_smix_en_s cn38xx;
126 struct cvmx_smix_en_s cn38xxp2;
127 struct cvmx_smix_en_s cn50xx;
128 struct cvmx_smix_en_s cn52xx;
129 struct cvmx_smix_en_s cn52xxp1;
130 struct cvmx_smix_en_s cn56xx;
131 struct cvmx_smix_en_s cn56xxp1;
132 struct cvmx_smix_en_s cn58xx;
133 struct cvmx_smix_en_s cn58xxp1;
134};
135
136union cvmx_smix_rd_dat {
137 uint64_t u64;
138 struct cvmx_smix_rd_dat_s {
139 uint64_t reserved_18_63:46;
140 uint64_t pending:1;
141 uint64_t val:1;
142 uint64_t dat:16;
143 } s;
144 struct cvmx_smix_rd_dat_s cn30xx;
145 struct cvmx_smix_rd_dat_s cn31xx;
146 struct cvmx_smix_rd_dat_s cn38xx;
147 struct cvmx_smix_rd_dat_s cn38xxp2;
148 struct cvmx_smix_rd_dat_s cn50xx;
149 struct cvmx_smix_rd_dat_s cn52xx;
150 struct cvmx_smix_rd_dat_s cn52xxp1;
151 struct cvmx_smix_rd_dat_s cn56xx;
152 struct cvmx_smix_rd_dat_s cn56xxp1;
153 struct cvmx_smix_rd_dat_s cn58xx;
154 struct cvmx_smix_rd_dat_s cn58xxp1;
155};
156
157union cvmx_smix_wr_dat {
158 uint64_t u64;
159 struct cvmx_smix_wr_dat_s {
160 uint64_t reserved_18_63:46;
161 uint64_t pending:1;
162 uint64_t val:1;
163 uint64_t dat:16;
164 } s;
165 struct cvmx_smix_wr_dat_s cn30xx;
166 struct cvmx_smix_wr_dat_s cn31xx;
167 struct cvmx_smix_wr_dat_s cn38xx;
168 struct cvmx_smix_wr_dat_s cn38xxp2;
169 struct cvmx_smix_wr_dat_s cn50xx;
170 struct cvmx_smix_wr_dat_s cn52xx;
171 struct cvmx_smix_wr_dat_s cn52xxp1;
172 struct cvmx_smix_wr_dat_s cn56xx;
173 struct cvmx_smix_wr_dat_s cn56xxp1;
174 struct cvmx_smix_wr_dat_s cn58xx;
175 struct cvmx_smix_wr_dat_s cn58xxp1;
176};
177
178#endif
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index ef24a7b4ea57..cba6fbed9f43 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -99,6 +99,8 @@ static inline int octeon_has_feature(enum octeon_feature feature)
99 return !cvmx_fuse_read(90); 99 return !cvmx_fuse_read(90);
100 100
101 case OCTEON_FEATURE_PCIE: 101 case OCTEON_FEATURE_PCIE:
102 case OCTEON_FEATURE_MGMT_PORT:
103 case OCTEON_FEATURE_RAID:
102 return OCTEON_IS_MODEL(OCTEON_CN56XX) 104 return OCTEON_IS_MODEL(OCTEON_CN56XX)
103 || OCTEON_IS_MODEL(OCTEON_CN52XX); 105 || OCTEON_IS_MODEL(OCTEON_CN52XX);
104 106
@@ -110,12 +112,6 @@ static inline int octeon_has_feature(enum octeon_feature feature)
110 case OCTEON_FEATURE_TRA: 112 case OCTEON_FEATURE_TRA:
111 return !(OCTEON_IS_MODEL(OCTEON_CN30XX) 113 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
112 || OCTEON_IS_MODEL(OCTEON_CN50XX)); 114 || OCTEON_IS_MODEL(OCTEON_CN50XX));
113 case OCTEON_FEATURE_MGMT_PORT:
114 return OCTEON_IS_MODEL(OCTEON_CN56XX)
115 || OCTEON_IS_MODEL(OCTEON_CN52XX);
116 case OCTEON_FEATURE_RAID:
117 return OCTEON_IS_MODEL(OCTEON_CN56XX)
118 || OCTEON_IS_MODEL(OCTEON_CN52XX);
119 case OCTEON_FEATURE_USB: 115 case OCTEON_FEATURE_USB:
120 return !(OCTEON_IS_MODEL(OCTEON_CN38XX) 116 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
121 || OCTEON_IS_MODEL(OCTEON_CN58XX)); 117 || OCTEON_IS_MODEL(OCTEON_CN58XX));
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index cac9b1a206fc..ca6214b5ccb9 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -47,6 +47,7 @@ struct octeon_cop2_state;
47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); 47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
48extern void octeon_crypto_disable(struct octeon_cop2_state *state, 48extern void octeon_crypto_disable(struct octeon_cop2_state *state,
49 unsigned long flags); 49 unsigned long flags);
50extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
50 51
51extern void octeon_init_cvmcount(void); 52extern void octeon_init_cvmcount(void);
52 53
@@ -212,6 +213,11 @@ struct octeon_cf_data {
212 int dma_engine; /* -1 for no DMA */ 213 int dma_engine; /* -1 for no DMA */
213}; 214};
214 215
216struct octeon_i2c_data {
217 unsigned int sys_freq;
218 unsigned int i2c_freq;
219};
220
215extern void octeon_write_lcd(const char *s); 221extern void octeon_write_lcd(const char *s);
216extern void octeon_check_cpu_bist(void); 222extern void octeon_check_cpu_bist(void);
217extern int octeon_get_boot_debug_flag(void); 223extern int octeon_get_boot_debug_flag(void);
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f266295cce51..a16beafcea91 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -107,18 +107,6 @@ typedef struct { unsigned long pte; } pte_t;
107typedef struct page *pgtable_t; 107typedef struct page *pgtable_t;
108 108
109/* 109/*
110 * For 3-level pagetables we defines these ourselves, for 2-level the
111 * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
112 */
113#ifdef CONFIG_64BIT
114
115typedef struct { unsigned long pmd; } pmd_t;
116#define pmd_val(x) ((x).pmd)
117#define __pmd(x) ((pmd_t) { (x) } )
118
119#endif
120
121/*
122 * Right now we don't support 4-level pagetables, so all pud-related 110 * Right now we don't support 4-level pagetables, so all pud-related
123 * definitions come from <asm-generic/pgtable-nopud.h>. 111 * definitions come from <asm-generic/pgtable-nopud.h>.
124 */ 112 */
@@ -200,8 +188,10 @@ typedef struct { unsigned long pgprot; } pgprot_t;
200#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ 188#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
201 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 189 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
202 190
203#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) 191#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \
204#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) 192 PHYS_OFFSET)
193#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \
194 PHYS_OFFSET)
205 195
206#include <asm-generic/memory_model.h> 196#include <asm-generic/memory_model.h>
207#include <asm-generic/getorder.h> 197#include <asm-generic/getorder.h>
diff --git a/arch/mips/include/asm/param.h b/arch/mips/include/asm/param.h
index 1d9bb8c5ab24..da3920fce9ad 100644
--- a/arch/mips/include/asm/param.h
+++ b/arch/mips/include/asm/param.h
@@ -9,23 +9,8 @@
9#ifndef _ASM_PARAM_H 9#ifndef _ASM_PARAM_H
10#define _ASM_PARAM_H 10#define _ASM_PARAM_H
11 11
12#ifdef __KERNEL__
13
14# define HZ CONFIG_HZ /* Internal kernel timer frequency */
15# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
16# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
17#endif
18
19#ifndef HZ
20#define HZ 100
21#endif
22
23#define EXEC_PAGESIZE 65536 12#define EXEC_PAGESIZE 65536
24 13
25#ifndef NOGROUP 14#include <asm-generic/param.h>
26#define NOGROUP (-1)
27#endif
28
29#define MAXHOSTNAMELEN 64 /* max length of hostname */
30 15
31#endif /* _ASM_PARAM_H */ 16#endif /* _ASM_PARAM_H */
diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h
index f52656826cce..cf252af64590 100644
--- a/arch/mips/include/asm/parport.h
+++ b/arch/mips/include/asm/parport.h
@@ -1,15 +1 @@
1/* #include <asm-generic/parport.h>
2 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
3 *
4 * This file should only be included by drivers/parport/parport_pc.c.
5 */
6#ifndef _ASM_PARPORT_H
7#define _ASM_PARPORT_H
8
9static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
10static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
11{
12 return parport_pc_find_isa_ports(autoirq, autodma);
13}
14
15#endif /* _ASM_PARPORT_H */
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 5ebf82572ec0..3beea1479b43 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -102,28 +102,6 @@ struct pci_dev;
102 */ 102 */
103extern unsigned int PCI_DMA_BUS_IS_PHYS; 103extern unsigned int PCI_DMA_BUS_IS_PHYS;
104 104
105#ifdef CONFIG_DMA_NEED_PCI_MAP_STATE
106
107/* pci_unmap_{single,page} is not a nop, thus... */
108#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME;
109#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME;
110#define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
111#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
112#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
113#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
114
115#else /* CONFIG_DMA_NEED_PCI_MAP_STATE */
116
117/* pci_unmap_{page,single} is a nop so... */
118#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
119#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
120#define pci_unmap_addr(PTR, ADDR_NAME) (0)
121#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
122#define pci_unmap_len(PTR, LEN_NAME) (0)
123#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
124
125#endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */
126
127#ifdef CONFIG_PCI 105#ifdef CONFIG_PCI
128static inline void pci_dma_burst_advice(struct pci_dev *pdev, 106static inline void pci_dma_burst_advice(struct pci_dev *pdev,
129 enum pci_dma_burst_strategy *strat, 107 enum pci_dma_burst_strategy *strat,
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
index 3738f4b48cbd..881d18b4e298 100644
--- a/arch/mips/include/asm/pgalloc.h
+++ b/arch/mips/include/asm/pgalloc.h
@@ -31,7 +31,7 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
31 */ 31 */
32extern void pmd_init(unsigned long page, unsigned long pagetable); 32extern void pmd_init(unsigned long page, unsigned long pagetable);
33 33
34#ifdef CONFIG_64BIT 34#ifndef __PAGETABLE_PMD_FOLDED
35 35
36static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) 36static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
37{ 37{
@@ -104,7 +104,7 @@ do { \
104 tlb_remove_page((tlb), pte); \ 104 tlb_remove_page((tlb), pte); \
105} while (0) 105} while (0)
106 106
107#ifdef CONFIG_64BIT 107#ifndef __PAGETABLE_PMD_FOLDED
108 108
109static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) 109static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
110{ 110{
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 55813d6150c7..ae90412556d0 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -127,8 +127,8 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
127#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) 127#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
128#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) 128#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
129#else 129#else
130#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 130#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
132#endif 132#endif
133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
134 134
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 9cd508993956..1be4b0fa30da 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -16,7 +16,11 @@
16#include <asm/cachectl.h> 16#include <asm/cachectl.h>
17#include <asm/fixmap.h> 17#include <asm/fixmap.h>
18 18
19#ifdef CONFIG_PAGE_SIZE_64KB
20#include <asm-generic/pgtable-nopmd.h>
21#else
19#include <asm-generic/pgtable-nopud.h> 22#include <asm-generic/pgtable-nopud.h>
23#endif
20 24
21/* 25/*
22 * Each address space has 2 4K pages as its page directory, giving 1024 26 * Each address space has 2 4K pages as its page directory, giving 1024
@@ -37,13 +41,20 @@
37 * fault address - VMALLOC_START. 41 * fault address - VMALLOC_START.
38 */ 42 */
39 43
44
45/* PGDIR_SHIFT determines what a third-level page table entry can map */
46#ifdef __PAGETABLE_PMD_FOLDED
47#define PGDIR_SHIFT (PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3)
48#else
49
40/* PMD_SHIFT determines the size of the area a second-level page table can map */ 50/* PMD_SHIFT determines the size of the area a second-level page table can map */
41#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3)) 51#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
42#define PMD_SIZE (1UL << PMD_SHIFT) 52#define PMD_SIZE (1UL << PMD_SHIFT)
43#define PMD_MASK (~(PMD_SIZE-1)) 53#define PMD_MASK (~(PMD_SIZE-1))
44 54
45/* PGDIR_SHIFT determines what a third-level page table entry can map */ 55
46#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) 56#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
57#endif
47#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 58#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
48#define PGDIR_MASK (~(PGDIR_SIZE-1)) 59#define PGDIR_MASK (~(PGDIR_SIZE-1))
49 60
@@ -92,12 +103,14 @@
92#ifdef CONFIG_PAGE_SIZE_64KB 103#ifdef CONFIG_PAGE_SIZE_64KB
93#define PGD_ORDER 0 104#define PGD_ORDER 0
94#define PUD_ORDER aieeee_attempt_to_allocate_pud 105#define PUD_ORDER aieeee_attempt_to_allocate_pud
95#define PMD_ORDER 0 106#define PMD_ORDER aieeee_attempt_to_allocate_pmd
96#define PTE_ORDER 0 107#define PTE_ORDER 0
97#endif 108#endif
98 109
99#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) 110#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
111#ifndef __PAGETABLE_PMD_FOLDED
100#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) 112#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
113#endif
101#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) 114#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
102 115
103#if PGDIR_SIZE >= TASK_SIZE 116#if PGDIR_SIZE >= TASK_SIZE
@@ -107,10 +120,17 @@
107#endif 120#endif
108#define FIRST_USER_ADDRESS 0UL 121#define FIRST_USER_ADDRESS 0UL
109 122
110#define VMALLOC_START MAP_BASE 123/*
124 * TLB refill handlers also map the vmalloc area into xuseg. Avoid
125 * the first couple of pages so NULL pointer dereferences will still
126 * reliably trap.
127 */
128#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
111#define VMALLOC_END \ 129#define VMALLOC_END \
112 (VMALLOC_START + \ 130 (MAP_BASE + \
113 PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) 131 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
132 (1UL << cpu_vmbits)) - (1UL << 32))
133
114#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ 134#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
115 VMALLOC_START != CKSSEG 135 VMALLOC_START != CKSSEG
116/* Load modules into 32bit-compatible segment. */ 136/* Load modules into 32bit-compatible segment. */
@@ -120,15 +140,30 @@
120 140
121#define pte_ERROR(e) \ 141#define pte_ERROR(e) \
122 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 142 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
143#ifndef __PAGETABLE_PMD_FOLDED
123#define pmd_ERROR(e) \ 144#define pmd_ERROR(e) \
124 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 145 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
146#endif
125#define pgd_ERROR(e) \ 147#define pgd_ERROR(e) \
126 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 148 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
127 149
128extern pte_t invalid_pte_table[PTRS_PER_PTE]; 150extern pte_t invalid_pte_table[PTRS_PER_PTE];
129extern pte_t empty_bad_page_table[PTRS_PER_PTE]; 151extern pte_t empty_bad_page_table[PTRS_PER_PTE];
152
153
154#ifndef __PAGETABLE_PMD_FOLDED
155/*
156 * For 3-level pagetables we defines these ourselves, for 2-level the
157 * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
158 */
159typedef struct { unsigned long pmd; } pmd_t;
160#define pmd_val(x) ((x).pmd)
161#define __pmd(x) ((pmd_t) { (x) } )
162
163
130extern pmd_t invalid_pmd_table[PTRS_PER_PMD]; 164extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
131extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD]; 165extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
166#endif
132 167
133/* 168/*
134 * Empty pgd/pmd entries point to the invalid_pte_table. 169 * Empty pgd/pmd entries point to the invalid_pte_table.
@@ -149,6 +184,7 @@ static inline void pmd_clear(pmd_t *pmdp)
149{ 184{
150 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 185 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
151} 186}
187#ifndef __PAGETABLE_PMD_FOLDED
152 188
153/* 189/*
154 * Empty pud entries point to the invalid_pmd_table. 190 * Empty pud entries point to the invalid_pmd_table.
@@ -172,6 +208,7 @@ static inline void pud_clear(pud_t *pudp)
172{ 208{
173 pud_val(*pudp) = ((unsigned long) invalid_pmd_table); 209 pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
174} 210}
211#endif
175 212
176#define pte_page(x) pfn_to_page(pte_pfn(x)) 213#define pte_page(x) pfn_to_page(pte_pfn(x))
177 214
@@ -179,8 +216,8 @@ static inline void pud_clear(pud_t *pudp)
179#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) 216#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
180#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) 217#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
181#else 218#else
182#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 219#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
183#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 220#define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
184#endif 221#endif
185 222
186#define __pgd_offset(address) pgd_index(address) 223#define __pgd_offset(address) pgd_index(address)
@@ -196,6 +233,7 @@ static inline void pud_clear(pud_t *pudp)
196/* to find an entry in a page-table-directory */ 233/* to find an entry in a page-table-directory */
197#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) 234#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
198 235
236#ifndef __PAGETABLE_PMD_FOLDED
199static inline unsigned long pud_page_vaddr(pud_t pud) 237static inline unsigned long pud_page_vaddr(pud_t pud)
200{ 238{
201 return pud_val(pud); 239 return pud_val(pud);
@@ -208,6 +246,7 @@ static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
208{ 246{
209 return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address); 247 return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
210} 248}
249#endif
211 250
212/* Find an entry in the third-level page table.. */ 251/* Find an entry in the third-level page table.. */
213#define __pte_offset(address) \ 252#define __pte_offset(address) \
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 1073e6df8621..e9fe7e97ce4c 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -50,7 +50,7 @@
50#define _CACHE_SHIFT 3 50#define _CACHE_SHIFT 3
51#define _CACHE_MASK (7<<3) 51#define _CACHE_MASK (7<<3)
52 52
53#else 53#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
54 54
55#define _PAGE_PRESENT (1<<0) /* implemented in software */ 55#define _PAGE_PRESENT (1<<0) /* implemented in software */
56#define _PAGE_READ (1<<1) /* implemented in software */ 56#define _PAGE_READ (1<<1) /* implemented in software */
@@ -59,8 +59,6 @@
59#define _PAGE_MODIFIED (1<<4) /* implemented in software */ 59#define _PAGE_MODIFIED (1<<4) /* implemented in software */
60#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ 60#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */
61 61
62#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
63
64#define _PAGE_GLOBAL (1<<8) 62#define _PAGE_GLOBAL (1<<8)
65#define _PAGE_VALID (1<<9) 63#define _PAGE_VALID (1<<9)
66#define _PAGE_SILENT_READ (1<<9) /* synonym */ 64#define _PAGE_SILENT_READ (1<<9) /* synonym */
@@ -69,21 +67,113 @@
69#define _CACHE_UNCACHED (1<<11) 67#define _CACHE_UNCACHED (1<<11)
70#define _CACHE_MASK (1<<11) 68#define _CACHE_MASK (1<<11)
71 69
70#else /* 'Normal' r4K case */
71/*
72 * When using the RI/XI bit support, we have 13 bits of flags below
73 * the physical address. The RI/XI bits are placed such that a SRL 5
74 * can strip off the software bits, then a ROTR 2 can move the RI/XI
75 * into bits [63:62]. This also limits physical address to 56 bits,
76 * which is more than we need right now.
77 */
78
79/* implemented in software */
80#define _PAGE_PRESENT_SHIFT (0)
81#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
82/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */
83#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
84#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
85/* implemented in software */
86#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
87#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
88/* implemented in software */
89#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
90#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
91/* implemented in software */
92#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
93#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
94/* set:pagecache unset:swap */
95#define _PAGE_FILE (_PAGE_MODIFIED)
96
97#ifdef CONFIG_HUGETLB_PAGE
98/* huge tlb page */
99#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
100#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
72#else 101#else
102#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT)
103#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
104#endif
73 105
74#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ 106/* Page cannot be executed */
75#define _PAGE_HUGE (1<<5) /* huge tlb page */ 107#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
76#define _PAGE_GLOBAL (1<<6) 108#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
77#define _PAGE_VALID (1<<7) 109
78#define _PAGE_SILENT_READ (1<<7) /* synonym */ 110/* Page cannot be read */
79#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ 111#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
80#define _PAGE_SILENT_WRITE (1<<8) 112#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
81#define _CACHE_SHIFT 9 113
82#define _CACHE_MASK (7<<9) 114#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
115#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
116
117#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
118#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
119/* synonym */
120#define _PAGE_SILENT_READ (_PAGE_VALID)
121
122/* The MIPS dirty bit */
123#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
124#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
125#define _PAGE_SILENT_WRITE (_PAGE_DIRTY)
126
127#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
128#define _CACHE_MASK (7 << _CACHE_SHIFT)
129
130#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
83 131
84#endif
85#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ 132#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
86 133
134#ifndef _PFN_SHIFT
135#define _PFN_SHIFT PAGE_SHIFT
136#endif
137#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
138
139#ifndef _PAGE_NO_READ
140#define _PAGE_NO_READ ({BUG(); 0; })
141#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
142#endif
143#ifndef _PAGE_NO_EXEC
144#define _PAGE_NO_EXEC ({BUG(); 0; })
145#endif
146#ifndef _PAGE_GLOBAL_SHIFT
147#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL)
148#endif
149
150
151#ifndef __ASSEMBLY__
152/*
153 * pte_to_entrylo converts a page table entry (PTE) into a Mips
154 * entrylo0/1 value.
155 */
156static inline uint64_t pte_to_entrylo(unsigned long pte_val)
157{
158 if (kernel_uses_smartmips_rixi) {
159 int sa;
160#ifdef CONFIG_32BIT
161 sa = 31 - _PAGE_NO_READ_SHIFT;
162#else
163 sa = 63 - _PAGE_NO_READ_SHIFT;
164#endif
165 /*
166 * C has no way to express that this is a DSRL
167 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
168 * in the fast path this is done in assembly
169 */
170 return (pte_val >> _PAGE_GLOBAL_SHIFT) |
171 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
172 }
173
174 return pte_val >> _PAGE_GLOBAL_SHIFT;
175}
176#endif
87 177
88/* 178/*
89 * Cache attributes 179 * Cache attributes
@@ -130,9 +220,9 @@
130 220
131#endif 221#endif
132 222
133#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 223#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ))
134#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 224#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
135 225
136#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 226#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
137 227
138#endif /* _ASM_PGTABLE_BITS_H */ 228#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d6eb6134abec..7e40f3778179 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -22,23 +22,24 @@ struct mm_struct;
22struct vm_area_struct; 22struct vm_area_struct;
23 23
24#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) 24#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
25#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 25#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
26 _page_cachable_default) 26 _page_cachable_default)
27#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 27#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
28 _page_cachable_default) 28 (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default)
29#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 29#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
30 _page_cachable_default) 30 _page_cachable_default)
31#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ 31#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
32 _PAGE_GLOBAL | _page_cachable_default) 32 _PAGE_GLOBAL | _page_cachable_default)
33#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 33#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
34 _page_cachable_default) 34 _page_cachable_default)
35#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ 35#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
36 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) 36 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
37 37
38/* 38/*
39 * MIPS can't do page protection for execute, and considers that the same like 39 * If _PAGE_NO_EXEC is not defined, we can't do page protection for
40 * read. Also, write permissions imply read permissions. This is the closest 40 * execute, and consider it to be the same as read. Also, write
41 * we can get by reasonable means.. 41 * permissions imply read permissions. This is the closest we can get
42 * by reasonable means..
42 */ 43 */
43 44
44/* 45/*
@@ -177,7 +178,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
177 */ 178 */
178#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) 179#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
179 180
180#ifdef CONFIG_64BIT 181#ifndef __PAGETABLE_PMD_FOLDED
181/* 182/*
182 * (puds are folded into pgds so this doesn't get actually called, 183 * (puds are folded into pgds so this doesn't get actually called,
183 * but the define is needed for a generic inline function.) 184 * but the define is needed for a generic inline function.)
@@ -298,8 +299,13 @@ static inline pte_t pte_mkdirty(pte_t pte)
298static inline pte_t pte_mkyoung(pte_t pte) 299static inline pte_t pte_mkyoung(pte_t pte)
299{ 300{
300 pte_val(pte) |= _PAGE_ACCESSED; 301 pte_val(pte) |= _PAGE_ACCESSED;
301 if (pte_val(pte) & _PAGE_READ) 302 if (kernel_uses_smartmips_rixi) {
302 pte_val(pte) |= _PAGE_SILENT_READ; 303 if (!(pte_val(pte) & _PAGE_NO_READ))
304 pte_val(pte) |= _PAGE_SILENT_READ;
305 } else {
306 if (pte_val(pte) & _PAGE_READ)
307 pte_val(pte) |= _PAGE_SILENT_READ;
308 }
303 return pte; 309 return pte;
304} 310}
305 311
@@ -362,8 +368,9 @@ extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
362 pte_t pte); 368 pte_t pte);
363 369
364static inline void update_mmu_cache(struct vm_area_struct *vma, 370static inline void update_mmu_cache(struct vm_area_struct *vma,
365 unsigned long address, pte_t pte) 371 unsigned long address, pte_t *ptep)
366{ 372{
373 pte_t pte = *ptep;
367 __update_tlb(vma, address, pte); 374 __update_tlb(vma, address, pte);
368 __update_cache(vma, address, pte); 375 __update_cache(vma, address, pte);
369} 376}
@@ -390,6 +397,19 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
390#include <asm-generic/pgtable.h> 397#include <asm-generic/pgtable.h>
391 398
392/* 399/*
400 * uncached accelerated TLB map for video memory access
401 */
402#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
403#define __HAVE_PHYS_MEM_ACCESS_PROT
404
405struct file;
406pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
407 unsigned long size, pgprot_t vma_prot);
408int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
409 unsigned long size, pgprot_t *vma_prot);
410#endif
411
412/*
393 * We provide our own get_unmapped area to cope with the virtual aliasing 413 * We provide our own get_unmapped area to cope with the virtual aliasing
394 * constraints placed on us by the cache architecture. 414 * constraints placed on us by the cache architecture.
395 */ 415 */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 14ca7dc382a8..54ef1a96d7ce 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -118,7 +118,6 @@
118#define ZSP_DUET 'D' /* one DUET zsp engine */ 118#define ZSP_DUET 'D' /* one DUET zsp engine */
119#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */ 119#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
120 120
121extern char *prom_getcmdline(void);
122extern char *prom_getenv(char *name); 121extern char *prom_getenv(char *name);
123extern void prom_init_cmdline(void); 122extern void prom_init_cmdline(void);
124extern void prom_meminit(void); 123extern void prom_meminit(void);
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 087a8884ef06..ab387910009a 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -33,13 +33,19 @@ extern void (*cpu_wait)(void);
33 33
34extern unsigned int vced_count, vcei_count; 34extern unsigned int vced_count, vcei_count;
35 35
36/*
37 * A special page (the vdso) is mapped into all processes at the very
38 * top of the virtual memory space.
39 */
40#define SPECIAL_PAGES_SIZE PAGE_SIZE
41
36#ifdef CONFIG_32BIT 42#ifdef CONFIG_32BIT
37/* 43/*
38 * User space process size: 2GB. This is hardcoded into a few places, 44 * User space process size: 2GB. This is hardcoded into a few places,
39 * so don't change it unless you know what you are doing. 45 * so don't change it unless you know what you are doing.
40 */ 46 */
41#define TASK_SIZE 0x7fff8000UL 47#define TASK_SIZE 0x7fff8000UL
42#define STACK_TOP TASK_SIZE 48#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
43 49
44/* 50/*
45 * This decides where the kernel will search for a free chunk of vm 51 * This decides where the kernel will search for a free chunk of vm
@@ -59,7 +65,8 @@ extern unsigned int vced_count, vcei_count;
59#define TASK_SIZE32 0x7fff8000UL 65#define TASK_SIZE32 0x7fff8000UL
60#define TASK_SIZE 0x10000000000UL 66#define TASK_SIZE 0x10000000000UL
61#define STACK_TOP \ 67#define STACK_TOP \
62 (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) 68 (((test_thread_flag(TIF_32BIT_ADDR) ? \
69 TASK_SIZE32 : TASK_SIZE) & PAGE_MASK) - SPECIAL_PAGES_SIZE)
63 70
64/* 71/*
65 * This decides where the kernel will search for a free chunk of vm 72 * This decides where the kernel will search for a free chunk of vm
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index ce47118e52b7..cdc6a46efd98 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -142,9 +142,9 @@ extern int ptrace_set_watch_regs(struct task_struct *child,
142 142
143extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit); 143extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
144 144
145extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NORET; 145extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
146 146
147static inline void die_if_kernel(const char *str, const struct pt_regs *regs) 147static inline void die_if_kernel(const char *str, struct pt_regs *regs)
148{ 148{
149 if (unlikely(!user_mode(regs))) 149 if (unlikely(!user_mode(regs)))
150 die(str, regs); 150 die(str, regs);
diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h
index c07ebd8eb9e7..a0cb0caff152 100644
--- a/arch/mips/include/asm/serial.h
+++ b/arch/mips/include/asm/serial.h
@@ -1,22 +1 @@
1/* #include <asm-generic/serial.h>
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SERIAL_H
10#define _ASM_SERIAL_H
11
12
13/*
14 * This assumes you have a 1.8432 MHz clock for your UART.
15 *
16 * It'd be nice if someone built a serial card with a 24.576 MHz
17 * clock, since the 16550A is capable of handling a top speed of 1.5
18 * megabits/second; but this requires the faster clock.
19 */
20#define BASE_BAUD (1843200 / 16)
21
22#endif /* _ASM_SERIAL_H */
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
index 343ed15f8dc4..57a971904cfe 100644
--- a/arch/mips/include/asm/sgi/ioc.h
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -164,7 +164,7 @@ struct sgioc_regs {
164 u32 _unused5; 164 u32 _unused5;
165 u8 _write[3]; 165 u8 _write[3];
166 volatile u8 write; 166 volatile u8 write;
167#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */ 167#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshold */
168#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ 168#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */
169#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ 169#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
170#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ 170#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index bfce5c786f1c..2a2f1bddc276 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -33,14 +33,6 @@ extern int prom_flags;
33extern void prom_putchar(char c); 33extern void prom_putchar(char c);
34extern char prom_getchar(void); 34extern char prom_getchar(void);
35 35
36/* Memory descriptor management. */
37#define PROM_MAX_PMEMBLOCKS 32
38struct prom_pmemblock {
39 LONG base; /* Within KSEG0 or XKPHYS. */
40 ULONG size; /* In bytes. */
41 ULONG type; /* free or prom memory */
42};
43
44/* Get next memory descriptor after CURR, returns first descriptor 36/* Get next memory descriptor after CURR, returns first descriptor
45 * in chain is CURR is NULL. 37 * in chain is CURR is NULL.
46 */ 38 */
@@ -51,7 +43,6 @@ extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);
51 * array. 43 * array.
52 */ 44 */
53extern void prom_meminit(void); 45extern void prom_meminit(void);
54extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
55 46
56/* PROM device tree library routines. */ 47/* PROM device tree library routines. */
57#define PROM_NULL_COMPONENT ((pcomponent *) 0) 48#define PROM_NULL_COMPONENT ((pcomponent *) 0)
@@ -62,20 +53,6 @@ extern pcomponent *ArcGetPeer(pcomponent *this);
62/* Get child component of THIS. */ 53/* Get child component of THIS. */
63extern pcomponent *ArcGetChild(pcomponent *this); 54extern pcomponent *ArcGetChild(pcomponent *this);
64 55
65/* Get parent component of CHILD. */
66extern pcomponent *prom_getparent(pcomponent *child);
67
68/* Copy component opaque data of component THIS into BUFFER
69 * if component THIS has opaque data. Returns success or
70 * failure status.
71 */
72extern long prom_getcdata(void *buffer, pcomponent *this);
73
74/* Other misc. component routines. */
75extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data);
76extern long prom_delcomponent(pcomponent *this);
77extern pcomponent *prom_componentbypath(char *path);
78
79/* This is called at prom_init time to identify the 56/* This is called at prom_init time to identify the
80 * ARC architecture we are running on 57 * ARC architecture we are running on
81 */ 58 */
@@ -85,39 +62,16 @@ extern void prom_identify_arch(void);
85extern PCHAR ArcGetEnvironmentVariable(PCHAR name); 62extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
86extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); 63extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
87 64
88/* ARCS command line acquisition and parsing. */ 65/* ARCS command line parsing. */
89extern char *prom_getcmdline(void);
90extern void prom_init_cmdline(void); 66extern void prom_init_cmdline(void);
91 67
92/* Acquiring info about the current time, etc. */
93extern struct linux_tinfo *prom_gettinfo(void);
94extern unsigned long prom_getrtime(void);
95
96/* File operations. */ 68/* File operations. */
97extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt);
98extern long prom_open(char *name, enum linux_omode md, unsigned long *fd);
99extern long prom_close(unsigned long fd);
100extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt); 69extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
101extern long prom_getrstatus(unsigned long fd);
102extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt); 70extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
103extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm);
104extern long prom_mount(char *name, enum linux_mountops op);
105extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf);
106extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk);
107
108/* Running stand-along programs. */
109extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr);
110extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp);
111extern long prom_exec(char *name, long argc, char **argv, char **envp);
112 71
113/* Misc. routines. */ 72/* Misc. routines. */
114extern VOID prom_halt(VOID) __attribute__((noreturn));
115extern VOID prom_powerdown(VOID) __attribute__((noreturn));
116extern VOID prom_restart(VOID) __attribute__((noreturn));
117extern VOID ArcReboot(VOID) __attribute__((noreturn)); 73extern VOID ArcReboot(VOID) __attribute__((noreturn));
118extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); 74extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn));
119extern long prom_cfgsave(VOID);
120extern struct linux_sysid *prom_getsysid(VOID);
121extern VOID ArcFlushAllCaches(VOID); 75extern VOID ArcFlushAllCaches(VOID);
122extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID); 76extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID);
123 77
diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h
index ebefe797fc1d..2d1a26d3436a 100644
--- a/arch/mips/include/asm/sibyte/bigsur.h
+++ b/arch/mips/include/asm/sibyte/bigsur.h
@@ -46,4 +46,3 @@
46#endif 46#endif
47 47
48#endif /* __ASM_SIBYTE_BIGSUR_H */ 48#endif /* __ASM_SIBYTE_BIGSUR_H */
49
diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
index 081e8b1c4ad0..1e76cf137995 100644
--- a/arch/mips/include/asm/sibyte/sb1250_ldt.h
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
@@ -420,4 +420,3 @@
420#endif /* 1250 PASS2 || 112x PASS1 */ 420#endif /* 1250 PASS2 || 112x PASS1 */
421 421
422#endif 422#endif
423
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index b6faf08ca81d..591b9061fd8e 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -212,7 +212,7 @@
212#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) 212#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
213 213
214/* 214/*
215 * MAC Fifo Threshhold registers (Table 9-14) 215 * MAC Fifo Threshold registers (Table 9-14)
216 * Register: MAC_THRSH_CFG_0 216 * Register: MAC_THRSH_CFG_0
217 * Register: MAC_THRSH_CFG_1 217 * Register: MAC_THRSH_CFG_1
218 * Register: MAC_THRSH_CFG_2 218 * Register: MAC_THRSH_CFG_2
diff --git a/arch/mips/include/asm/sn/klkernvars.h b/arch/mips/include/asm/sn/klkernvars.h
index 5de4c5e8ab30..6af25ba41ade 100644
--- a/arch/mips/include/asm/sn/klkernvars.h
+++ b/arch/mips/include/asm/sn/klkernvars.h
@@ -26,4 +26,3 @@ typedef struct kern_vars_s {
26#endif /* !__ASSEMBLY__ */ 26#endif /* !__ASSEMBLY__ */
27 27
28#endif /* __ASM_SN_KLKERNVARS_H */ 28#endif /* __ASM_SN_KLKERNVARS_H */
29
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
index d0c29d4de084..31c76c021bb6 100644
--- a/arch/mips/include/asm/sn/sn0/hubio.h
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -825,7 +825,7 @@ typedef union iprb_u {
825 struct { 825 struct {
826 u64 rsvd1: 15, 826 u64 rsvd1: 15,
827 error: 1, /* Widget rcvd wr resp pkt w/ error */ 827 error: 1, /* Widget rcvd wr resp pkt w/ error */
828 ovflow: 5, /* Over flow count. perf measurement */ 828 ovflow: 5, /* Overflow count. perf measurement */
829 fire_and_forget: 1, /* Launch Write without response */ 829 fire_and_forget: 1, /* Launch Write without response */
830 mode: 2, /* Widget operation Mode */ 830 mode: 2, /* Widget operation Mode */
831 rsvd2: 2, 831 rsvd2: 2,
diff --git a/arch/mips/include/asm/socket.h b/arch/mips/include/asm/socket.h
index ae05accd9fe4..9de5190f2487 100644
--- a/arch/mips/include/asm/socket.h
+++ b/arch/mips/include/asm/socket.h
@@ -80,6 +80,8 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
80#define SO_TIMESTAMPING 37 80#define SO_TIMESTAMPING 37
81#define SCM_TIMESTAMPING SO_TIMESTAMPING 81#define SCM_TIMESTAMPING SO_TIMESTAMPING
82 82
83#define SO_RXQ_OVFL 40
84
83#ifdef __KERNEL__ 85#ifdef __KERNEL__
84 86
85/** sock_type - Socket types 87/** sock_type - Socket types
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 795ac6c23203..7165333ad043 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,4 +11,3 @@
11 11
12#endif /* CONFIG_SPARSEMEM */ 12#endif /* CONFIG_SPARSEMEM */
13#endif /* _MIPS_SPARSEMEM_H */ 13#endif /* _MIPS_SPARSEMEM_H */
14
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 5b60a09a0f08..396e402fbe2c 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -34,55 +34,55 @@
34 * becomes equal to the the initial value of the tail. 34 * becomes equal to the the initial value of the tail.
35 */ 35 */
36 36
37static inline int __raw_spin_is_locked(raw_spinlock_t *lock) 37static inline int arch_spin_is_locked(arch_spinlock_t *lock)
38{ 38{
39 unsigned int counters = ACCESS_ONCE(lock->lock); 39 u32 counters = ACCESS_ONCE(lock->lock);
40 40
41 return ((counters >> 14) ^ counters) & 0x1fff; 41 return ((counters >> 16) ^ counters) & 0xffff;
42} 42}
43 43
44#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) 44#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
45#define __raw_spin_unlock_wait(x) \ 45#define arch_spin_unlock_wait(x) \
46 while (__raw_spin_is_locked(x)) { cpu_relax(); } 46 while (arch_spin_is_locked(x)) { cpu_relax(); }
47 47
48static inline int __raw_spin_is_contended(raw_spinlock_t *lock) 48static inline int arch_spin_is_contended(arch_spinlock_t *lock)
49{ 49{
50 unsigned int counters = ACCESS_ONCE(lock->lock); 50 u32 counters = ACCESS_ONCE(lock->lock);
51 51
52 return (((counters >> 14) - counters) & 0x1fff) > 1; 52 return (((counters >> 16) - counters) & 0xffff) > 1;
53} 53}
54#define __raw_spin_is_contended __raw_spin_is_contended 54#define arch_spin_is_contended arch_spin_is_contended
55 55
56static inline void __raw_spin_lock(raw_spinlock_t *lock) 56static inline void arch_spin_lock(arch_spinlock_t *lock)
57{ 57{
58 int my_ticket; 58 int my_ticket;
59 int tmp; 59 int tmp;
60 int inc = 0x10000;
60 61
61 if (R10000_LLSC_WAR) { 62 if (R10000_LLSC_WAR) {
62 __asm__ __volatile__ ( 63 __asm__ __volatile__ (
63 " .set push # __raw_spin_lock \n" 64 " .set push # arch_spin_lock \n"
64 " .set noreorder \n" 65 " .set noreorder \n"
65 " \n" 66 " \n"
66 "1: ll %[ticket], %[ticket_ptr] \n" 67 "1: ll %[ticket], %[ticket_ptr] \n"
67 " addiu %[my_ticket], %[ticket], 0x4000 \n" 68 " addu %[my_ticket], %[ticket], %[inc] \n"
68 " sc %[my_ticket], %[ticket_ptr] \n" 69 " sc %[my_ticket], %[ticket_ptr] \n"
69 " beqzl %[my_ticket], 1b \n" 70 " beqzl %[my_ticket], 1b \n"
70 " nop \n" 71 " nop \n"
71 " srl %[my_ticket], %[ticket], 14 \n" 72 " srl %[my_ticket], %[ticket], 16 \n"
72 " andi %[my_ticket], %[my_ticket], 0x1fff \n" 73 " andi %[ticket], %[ticket], 0xffff \n"
73 " andi %[ticket], %[ticket], 0x1fff \n" 74 " andi %[my_ticket], %[my_ticket], 0xffff \n"
74 " bne %[ticket], %[my_ticket], 4f \n" 75 " bne %[ticket], %[my_ticket], 4f \n"
75 " subu %[ticket], %[my_ticket], %[ticket] \n" 76 " subu %[ticket], %[my_ticket], %[ticket] \n"
76 "2: \n" 77 "2: \n"
77 " .subsection 2 \n" 78 " .subsection 2 \n"
78 "4: andi %[ticket], %[ticket], 0x1fff \n" 79 "4: andi %[ticket], %[ticket], 0xffff \n"
79 " sll %[ticket], 5 \n" 80 " sll %[ticket], 5 \n"
80 " \n" 81 " \n"
81 "6: bnez %[ticket], 6b \n" 82 "6: bnez %[ticket], 6b \n"
82 " subu %[ticket], 1 \n" 83 " subu %[ticket], 1 \n"
83 " \n" 84 " \n"
84 " lw %[ticket], %[ticket_ptr] \n" 85 " lhu %[ticket], %[serving_now_ptr] \n"
85 " andi %[ticket], %[ticket], 0x1fff \n"
86 " beq %[ticket], %[my_ticket], 2b \n" 86 " beq %[ticket], %[my_ticket], 2b \n"
87 " subu %[ticket], %[my_ticket], %[ticket] \n" 87 " subu %[ticket], %[my_ticket], %[ticket] \n"
88 " b 4b \n" 88 " b 4b \n"
@@ -90,36 +90,33 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
90 " .previous \n" 90 " .previous \n"
91 " .set pop \n" 91 " .set pop \n"
92 : [ticket_ptr] "+m" (lock->lock), 92 : [ticket_ptr] "+m" (lock->lock),
93 [serving_now_ptr] "+m" (lock->h.serving_now),
93 [ticket] "=&r" (tmp), 94 [ticket] "=&r" (tmp),
94 [my_ticket] "=&r" (my_ticket)); 95 [my_ticket] "=&r" (my_ticket)
96 : [inc] "r" (inc));
95 } else { 97 } else {
96 __asm__ __volatile__ ( 98 __asm__ __volatile__ (
97 " .set push # __raw_spin_lock \n" 99 " .set push # arch_spin_lock \n"
98 " .set noreorder \n" 100 " .set noreorder \n"
99 " \n" 101 " \n"
100 " ll %[ticket], %[ticket_ptr] \n" 102 "1: ll %[ticket], %[ticket_ptr] \n"
101 "1: addiu %[my_ticket], %[ticket], 0x4000 \n" 103 " addu %[my_ticket], %[ticket], %[inc] \n"
102 " sc %[my_ticket], %[ticket_ptr] \n" 104 " sc %[my_ticket], %[ticket_ptr] \n"
103 " beqz %[my_ticket], 3f \n" 105 " beqz %[my_ticket], 1b \n"
104 " nop \n" 106 " srl %[my_ticket], %[ticket], 16 \n"
105 " srl %[my_ticket], %[ticket], 14 \n" 107 " andi %[ticket], %[ticket], 0xffff \n"
106 " andi %[my_ticket], %[my_ticket], 0x1fff \n" 108 " andi %[my_ticket], %[my_ticket], 0xffff \n"
107 " andi %[ticket], %[ticket], 0x1fff \n"
108 " bne %[ticket], %[my_ticket], 4f \n" 109 " bne %[ticket], %[my_ticket], 4f \n"
109 " subu %[ticket], %[my_ticket], %[ticket] \n" 110 " subu %[ticket], %[my_ticket], %[ticket] \n"
110 "2: \n" 111 "2: \n"
111 " .subsection 2 \n" 112 " .subsection 2 \n"
112 "3: b 1b \n"
113 " ll %[ticket], %[ticket_ptr] \n"
114 " \n"
115 "4: andi %[ticket], %[ticket], 0x1fff \n" 113 "4: andi %[ticket], %[ticket], 0x1fff \n"
116 " sll %[ticket], 5 \n" 114 " sll %[ticket], 5 \n"
117 " \n" 115 " \n"
118 "6: bnez %[ticket], 6b \n" 116 "6: bnez %[ticket], 6b \n"
119 " subu %[ticket], 1 \n" 117 " subu %[ticket], 1 \n"
120 " \n" 118 " \n"
121 " lw %[ticket], %[ticket_ptr] \n" 119 " lhu %[ticket], %[serving_now_ptr] \n"
122 " andi %[ticket], %[ticket], 0x1fff \n"
123 " beq %[ticket], %[my_ticket], 2b \n" 120 " beq %[ticket], %[my_ticket], 2b \n"
124 " subu %[ticket], %[my_ticket], %[ticket] \n" 121 " subu %[ticket], %[my_ticket], %[ticket] \n"
125 " b 4b \n" 122 " b 4b \n"
@@ -127,68 +124,39 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
127 " .previous \n" 124 " .previous \n"
128 " .set pop \n" 125 " .set pop \n"
129 : [ticket_ptr] "+m" (lock->lock), 126 : [ticket_ptr] "+m" (lock->lock),
127 [serving_now_ptr] "+m" (lock->h.serving_now),
130 [ticket] "=&r" (tmp), 128 [ticket] "=&r" (tmp),
131 [my_ticket] "=&r" (my_ticket)); 129 [my_ticket] "=&r" (my_ticket)
130 : [inc] "r" (inc));
132 } 131 }
133 132
134 smp_llsc_mb(); 133 smp_llsc_mb();
135} 134}
136 135
137static inline void __raw_spin_unlock(raw_spinlock_t *lock) 136static inline void arch_spin_unlock(arch_spinlock_t *lock)
138{ 137{
139 int tmp; 138 unsigned int serving_now = lock->h.serving_now + 1;
140 139 wmb();
141 smp_llsc_mb(); 140 lock->h.serving_now = (u16)serving_now;
142 141 nudge_writes();
143 if (R10000_LLSC_WAR) {
144 __asm__ __volatile__ (
145 " # __raw_spin_unlock \n"
146 "1: ll %[ticket], %[ticket_ptr] \n"
147 " addiu %[ticket], %[ticket], 1 \n"
148 " ori %[ticket], %[ticket], 0x2000 \n"
149 " xori %[ticket], %[ticket], 0x2000 \n"
150 " sc %[ticket], %[ticket_ptr] \n"
151 " beqzl %[ticket], 1b \n"
152 : [ticket_ptr] "+m" (lock->lock),
153 [ticket] "=&r" (tmp));
154 } else {
155 __asm__ __volatile__ (
156 " .set push # __raw_spin_unlock \n"
157 " .set noreorder \n"
158 " \n"
159 " ll %[ticket], %[ticket_ptr] \n"
160 "1: addiu %[ticket], %[ticket], 1 \n"
161 " ori %[ticket], %[ticket], 0x2000 \n"
162 " xori %[ticket], %[ticket], 0x2000 \n"
163 " sc %[ticket], %[ticket_ptr] \n"
164 " beqz %[ticket], 2f \n"
165 " nop \n"
166 " \n"
167 " .subsection 2 \n"
168 "2: b 1b \n"
169 " ll %[ticket], %[ticket_ptr] \n"
170 " .previous \n"
171 " .set pop \n"
172 : [ticket_ptr] "+m" (lock->lock),
173 [ticket] "=&r" (tmp));
174 }
175} 142}
176 143
177static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) 144static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
178{ 145{
179 int tmp, tmp2, tmp3; 146 int tmp, tmp2, tmp3;
147 int inc = 0x10000;
180 148
181 if (R10000_LLSC_WAR) { 149 if (R10000_LLSC_WAR) {
182 __asm__ __volatile__ ( 150 __asm__ __volatile__ (
183 " .set push # __raw_spin_trylock \n" 151 " .set push # arch_spin_trylock \n"
184 " .set noreorder \n" 152 " .set noreorder \n"
185 " \n" 153 " \n"
186 "1: ll %[ticket], %[ticket_ptr] \n" 154 "1: ll %[ticket], %[ticket_ptr] \n"
187 " srl %[my_ticket], %[ticket], 14 \n" 155 " srl %[my_ticket], %[ticket], 16 \n"
188 " andi %[my_ticket], %[my_ticket], 0x1fff \n" 156 " andi %[my_ticket], %[my_ticket], 0xffff \n"
189 " andi %[now_serving], %[ticket], 0x1fff \n" 157 " andi %[now_serving], %[ticket], 0xffff \n"
190 " bne %[my_ticket], %[now_serving], 3f \n" 158 " bne %[my_ticket], %[now_serving], 3f \n"
191 " addiu %[ticket], %[ticket], 0x4000 \n" 159 " addu %[ticket], %[ticket], %[inc] \n"
192 " sc %[ticket], %[ticket_ptr] \n" 160 " sc %[ticket], %[ticket_ptr] \n"
193 " beqzl %[ticket], 1b \n" 161 " beqzl %[ticket], 1b \n"
194 " li %[ticket], 1 \n" 162 " li %[ticket], 1 \n"
@@ -201,33 +169,33 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
201 : [ticket_ptr] "+m" (lock->lock), 169 : [ticket_ptr] "+m" (lock->lock),
202 [ticket] "=&r" (tmp), 170 [ticket] "=&r" (tmp),
203 [my_ticket] "=&r" (tmp2), 171 [my_ticket] "=&r" (tmp2),
204 [now_serving] "=&r" (tmp3)); 172 [now_serving] "=&r" (tmp3)
173 : [inc] "r" (inc));
205 } else { 174 } else {
206 __asm__ __volatile__ ( 175 __asm__ __volatile__ (
207 " .set push # __raw_spin_trylock \n" 176 " .set push # arch_spin_trylock \n"
208 " .set noreorder \n" 177 " .set noreorder \n"
209 " \n" 178 " \n"
210 " ll %[ticket], %[ticket_ptr] \n" 179 "1: ll %[ticket], %[ticket_ptr] \n"
211 "1: srl %[my_ticket], %[ticket], 14 \n" 180 " srl %[my_ticket], %[ticket], 16 \n"
212 " andi %[my_ticket], %[my_ticket], 0x1fff \n" 181 " andi %[my_ticket], %[my_ticket], 0xffff \n"
213 " andi %[now_serving], %[ticket], 0x1fff \n" 182 " andi %[now_serving], %[ticket], 0xffff \n"
214 " bne %[my_ticket], %[now_serving], 3f \n" 183 " bne %[my_ticket], %[now_serving], 3f \n"
215 " addiu %[ticket], %[ticket], 0x4000 \n" 184 " addu %[ticket], %[ticket], %[inc] \n"
216 " sc %[ticket], %[ticket_ptr] \n" 185 " sc %[ticket], %[ticket_ptr] \n"
217 " beqz %[ticket], 4f \n" 186 " beqz %[ticket], 1b \n"
218 " li %[ticket], 1 \n" 187 " li %[ticket], 1 \n"
219 "2: \n" 188 "2: \n"
220 " .subsection 2 \n" 189 " .subsection 2 \n"
221 "3: b 2b \n" 190 "3: b 2b \n"
222 " li %[ticket], 0 \n" 191 " li %[ticket], 0 \n"
223 "4: b 1b \n"
224 " ll %[ticket], %[ticket_ptr] \n"
225 " .previous \n" 192 " .previous \n"
226 " .set pop \n" 193 " .set pop \n"
227 : [ticket_ptr] "+m" (lock->lock), 194 : [ticket_ptr] "+m" (lock->lock),
228 [ticket] "=&r" (tmp), 195 [ticket] "=&r" (tmp),
229 [my_ticket] "=&r" (tmp2), 196 [my_ticket] "=&r" (tmp2),
230 [now_serving] "=&r" (tmp3)); 197 [now_serving] "=&r" (tmp3)
198 : [inc] "r" (inc));
231 } 199 }
232 200
233 smp_llsc_mb(); 201 smp_llsc_mb();
@@ -248,21 +216,21 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
248 * read_can_lock - would read_trylock() succeed? 216 * read_can_lock - would read_trylock() succeed?
249 * @lock: the rwlock in question. 217 * @lock: the rwlock in question.
250 */ 218 */
251#define __raw_read_can_lock(rw) ((rw)->lock >= 0) 219#define arch_read_can_lock(rw) ((rw)->lock >= 0)
252 220
253/* 221/*
254 * write_can_lock - would write_trylock() succeed? 222 * write_can_lock - would write_trylock() succeed?
255 * @lock: the rwlock in question. 223 * @lock: the rwlock in question.
256 */ 224 */
257#define __raw_write_can_lock(rw) (!(rw)->lock) 225#define arch_write_can_lock(rw) (!(rw)->lock)
258 226
259static inline void __raw_read_lock(raw_rwlock_t *rw) 227static inline void arch_read_lock(arch_rwlock_t *rw)
260{ 228{
261 unsigned int tmp; 229 unsigned int tmp;
262 230
263 if (R10000_LLSC_WAR) { 231 if (R10000_LLSC_WAR) {
264 __asm__ __volatile__( 232 __asm__ __volatile__(
265 " .set noreorder # __raw_read_lock \n" 233 " .set noreorder # arch_read_lock \n"
266 "1: ll %1, %2 \n" 234 "1: ll %1, %2 \n"
267 " bltz %1, 1b \n" 235 " bltz %1, 1b \n"
268 " addu %1, 1 \n" 236 " addu %1, 1 \n"
@@ -275,7 +243,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
275 : "memory"); 243 : "memory");
276 } else { 244 } else {
277 __asm__ __volatile__( 245 __asm__ __volatile__(
278 " .set noreorder # __raw_read_lock \n" 246 " .set noreorder # arch_read_lock \n"
279 "1: ll %1, %2 \n" 247 "1: ll %1, %2 \n"
280 " bltz %1, 2f \n" 248 " bltz %1, 2f \n"
281 " addu %1, 1 \n" 249 " addu %1, 1 \n"
@@ -301,15 +269,15 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
301/* Note the use of sub, not subu which will make the kernel die with an 269/* Note the use of sub, not subu which will make the kernel die with an
302 overflow exception if we ever try to unlock an rwlock that is already 270 overflow exception if we ever try to unlock an rwlock that is already
303 unlocked or is being held by a writer. */ 271 unlocked or is being held by a writer. */
304static inline void __raw_read_unlock(raw_rwlock_t *rw) 272static inline void arch_read_unlock(arch_rwlock_t *rw)
305{ 273{
306 unsigned int tmp; 274 unsigned int tmp;
307 275
308 smp_llsc_mb(); 276 smp_mb__before_llsc();
309 277
310 if (R10000_LLSC_WAR) { 278 if (R10000_LLSC_WAR) {
311 __asm__ __volatile__( 279 __asm__ __volatile__(
312 "1: ll %1, %2 # __raw_read_unlock \n" 280 "1: ll %1, %2 # arch_read_unlock \n"
313 " sub %1, 1 \n" 281 " sub %1, 1 \n"
314 " sc %1, %0 \n" 282 " sc %1, %0 \n"
315 " beqzl %1, 1b \n" 283 " beqzl %1, 1b \n"
@@ -318,7 +286,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
318 : "memory"); 286 : "memory");
319 } else { 287 } else {
320 __asm__ __volatile__( 288 __asm__ __volatile__(
321 " .set noreorder # __raw_read_unlock \n" 289 " .set noreorder # arch_read_unlock \n"
322 "1: ll %1, %2 \n" 290 "1: ll %1, %2 \n"
323 " sub %1, 1 \n" 291 " sub %1, 1 \n"
324 " sc %1, %0 \n" 292 " sc %1, %0 \n"
@@ -335,13 +303,13 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
335 } 303 }
336} 304}
337 305
338static inline void __raw_write_lock(raw_rwlock_t *rw) 306static inline void arch_write_lock(arch_rwlock_t *rw)
339{ 307{
340 unsigned int tmp; 308 unsigned int tmp;
341 309
342 if (R10000_LLSC_WAR) { 310 if (R10000_LLSC_WAR) {
343 __asm__ __volatile__( 311 __asm__ __volatile__(
344 " .set noreorder # __raw_write_lock \n" 312 " .set noreorder # arch_write_lock \n"
345 "1: ll %1, %2 \n" 313 "1: ll %1, %2 \n"
346 " bnez %1, 1b \n" 314 " bnez %1, 1b \n"
347 " lui %1, 0x8000 \n" 315 " lui %1, 0x8000 \n"
@@ -354,7 +322,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
354 : "memory"); 322 : "memory");
355 } else { 323 } else {
356 __asm__ __volatile__( 324 __asm__ __volatile__(
357 " .set noreorder # __raw_write_lock \n" 325 " .set noreorder # arch_write_lock \n"
358 "1: ll %1, %2 \n" 326 "1: ll %1, %2 \n"
359 " bnez %1, 2f \n" 327 " bnez %1, 2f \n"
360 " lui %1, 0x8000 \n" 328 " lui %1, 0x8000 \n"
@@ -377,26 +345,26 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
377 smp_llsc_mb(); 345 smp_llsc_mb();
378} 346}
379 347
380static inline void __raw_write_unlock(raw_rwlock_t *rw) 348static inline void arch_write_unlock(arch_rwlock_t *rw)
381{ 349{
382 smp_mb(); 350 smp_mb();
383 351
384 __asm__ __volatile__( 352 __asm__ __volatile__(
385 " # __raw_write_unlock \n" 353 " # arch_write_unlock \n"
386 " sw $0, %0 \n" 354 " sw $0, %0 \n"
387 : "=m" (rw->lock) 355 : "=m" (rw->lock)
388 : "m" (rw->lock) 356 : "m" (rw->lock)
389 : "memory"); 357 : "memory");
390} 358}
391 359
392static inline int __raw_read_trylock(raw_rwlock_t *rw) 360static inline int arch_read_trylock(arch_rwlock_t *rw)
393{ 361{
394 unsigned int tmp; 362 unsigned int tmp;
395 int ret; 363 int ret;
396 364
397 if (R10000_LLSC_WAR) { 365 if (R10000_LLSC_WAR) {
398 __asm__ __volatile__( 366 __asm__ __volatile__(
399 " .set noreorder # __raw_read_trylock \n" 367 " .set noreorder # arch_read_trylock \n"
400 " li %2, 0 \n" 368 " li %2, 0 \n"
401 "1: ll %1, %3 \n" 369 "1: ll %1, %3 \n"
402 " bltz %1, 2f \n" 370 " bltz %1, 2f \n"
@@ -413,7 +381,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
413 : "memory"); 381 : "memory");
414 } else { 382 } else {
415 __asm__ __volatile__( 383 __asm__ __volatile__(
416 " .set noreorder # __raw_read_trylock \n" 384 " .set noreorder # arch_read_trylock \n"
417 " li %2, 0 \n" 385 " li %2, 0 \n"
418 "1: ll %1, %3 \n" 386 "1: ll %1, %3 \n"
419 " bltz %1, 2f \n" 387 " bltz %1, 2f \n"
@@ -433,14 +401,14 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
433 return ret; 401 return ret;
434} 402}
435 403
436static inline int __raw_write_trylock(raw_rwlock_t *rw) 404static inline int arch_write_trylock(arch_rwlock_t *rw)
437{ 405{
438 unsigned int tmp; 406 unsigned int tmp;
439 int ret; 407 int ret;
440 408
441 if (R10000_LLSC_WAR) { 409 if (R10000_LLSC_WAR) {
442 __asm__ __volatile__( 410 __asm__ __volatile__(
443 " .set noreorder # __raw_write_trylock \n" 411 " .set noreorder # arch_write_trylock \n"
444 " li %2, 0 \n" 412 " li %2, 0 \n"
445 "1: ll %1, %3 \n" 413 "1: ll %1, %3 \n"
446 " bnez %1, 2f \n" 414 " bnez %1, 2f \n"
@@ -457,7 +425,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
457 : "memory"); 425 : "memory");
458 } else { 426 } else {
459 __asm__ __volatile__( 427 __asm__ __volatile__(
460 " .set noreorder # __raw_write_trylock \n" 428 " .set noreorder # arch_write_trylock \n"
461 " li %2, 0 \n" 429 " li %2, 0 \n"
462 "1: ll %1, %3 \n" 430 "1: ll %1, %3 \n"
463 " bnez %1, 2f \n" 431 " bnez %1, 2f \n"
@@ -480,11 +448,11 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
480 return ret; 448 return ret;
481} 449}
482 450
483#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock) 451#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
484#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock) 452#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
485 453
486#define _raw_spin_relax(lock) cpu_relax() 454#define arch_spin_relax(lock) cpu_relax()
487#define _raw_read_relax(lock) cpu_relax() 455#define arch_read_relax(lock) cpu_relax()
488#define _raw_write_relax(lock) cpu_relax() 456#define arch_write_relax(lock) cpu_relax()
489 457
490#endif /* _ASM_SPINLOCK_H */ 458#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
index adeedaa116c1..c52f36013a9d 100644
--- a/arch/mips/include/asm/spinlock_types.h
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -5,21 +5,33 @@
5# error "please don't include this file directly" 5# error "please don't include this file directly"
6#endif 6#endif
7 7
8typedef struct { 8#include <linux/types.h>
9
10#include <asm/byteorder.h>
11
12typedef union {
9 /* 13 /*
10 * bits 0..13: serving_now 14 * bits 0..15 : serving_now
11 * bits 14 : junk data 15 * bits 16..31 : ticket
12 * bits 15..28: ticket
13 */ 16 */
14 unsigned int lock; 17 u32 lock;
15} raw_spinlock_t; 18 struct {
19#ifdef __BIG_ENDIAN
20 u16 ticket;
21 u16 serving_now;
22#else
23 u16 serving_now;
24 u16 ticket;
25#endif
26 } h;
27} arch_spinlock_t;
16 28
17#define __RAW_SPIN_LOCK_UNLOCKED { 0 } 29#define __ARCH_SPIN_LOCK_UNLOCKED { .lock = 0 }
18 30
19typedef struct { 31typedef struct {
20 volatile unsigned int lock; 32 volatile unsigned int lock;
21} raw_rwlock_t; 33} arch_rwlock_t;
22 34
23#define __RAW_RW_LOCK_UNLOCKED { 0 } 35#define __ARCH_RW_LOCK_UNLOCKED { 0 }
24 36
25#endif 37#endif
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index db0fa7b5aeaf..58730c5ce4bf 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -51,9 +51,6 @@
51 LONG_S v1, PT_ACX(sp) 51 LONG_S v1, PT_ACX(sp)
52#else 52#else
53 mfhi v1 53 mfhi v1
54 LONG_S v1, PT_HI(sp)
55 mflo v1
56 LONG_S v1, PT_LO(sp)
57#endif 54#endif
58#ifdef CONFIG_32BIT 55#ifdef CONFIG_32BIT
59 LONG_S $8, PT_R8(sp) 56 LONG_S $8, PT_R8(sp)
@@ -62,10 +59,17 @@
62 LONG_S $10, PT_R10(sp) 59 LONG_S $10, PT_R10(sp)
63 LONG_S $11, PT_R11(sp) 60 LONG_S $11, PT_R11(sp)
64 LONG_S $12, PT_R12(sp) 61 LONG_S $12, PT_R12(sp)
62#ifndef CONFIG_CPU_HAS_SMARTMIPS
63 LONG_S v1, PT_HI(sp)
64 mflo v1
65#endif
65 LONG_S $13, PT_R13(sp) 66 LONG_S $13, PT_R13(sp)
66 LONG_S $14, PT_R14(sp) 67 LONG_S $14, PT_R14(sp)
67 LONG_S $15, PT_R15(sp) 68 LONG_S $15, PT_R15(sp)
68 LONG_S $24, PT_R24(sp) 69 LONG_S $24, PT_R24(sp)
70#ifndef CONFIG_CPU_HAS_SMARTMIPS
71 LONG_S v1, PT_LO(sp)
72#endif
69 .endm 73 .endm
70 74
71 .macro SAVE_STATIC 75 .macro SAVE_STATIC
@@ -83,15 +87,19 @@
83#ifdef CONFIG_SMP 87#ifdef CONFIG_SMP
84#ifdef CONFIG_MIPS_MT_SMTC 88#ifdef CONFIG_MIPS_MT_SMTC
85#define PTEBASE_SHIFT 19 /* TCBIND */ 89#define PTEBASE_SHIFT 19 /* TCBIND */
90#define CPU_ID_REG CP0_TCBIND
91#define CPU_ID_MFC0 mfc0
92#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
93#define PTEBASE_SHIFT 48 /* XCONTEXT */
94#define CPU_ID_REG CP0_XCONTEXT
95#define CPU_ID_MFC0 MFC0
86#else 96#else
87#define PTEBASE_SHIFT 23 /* CONTEXT */ 97#define PTEBASE_SHIFT 23 /* CONTEXT */
98#define CPU_ID_REG CP0_CONTEXT
99#define CPU_ID_MFC0 MFC0
88#endif 100#endif
89 .macro get_saved_sp /* SMP variation */ 101 .macro get_saved_sp /* SMP variation */
90#ifdef CONFIG_MIPS_MT_SMTC 102 CPU_ID_MFC0 k0, CPU_ID_REG
91 mfc0 k0, CP0_TCBIND
92#else
93 MFC0 k0, CP0_CONTEXT
94#endif
95#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 103#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
96 lui k1, %hi(kernelsp) 104 lui k1, %hi(kernelsp)
97#else 105#else
@@ -107,16 +115,31 @@
107 .endm 115 .endm
108 116
109 .macro set_saved_sp stackp temp temp2 117 .macro set_saved_sp stackp temp temp2
110#ifdef CONFIG_MIPS_MT_SMTC 118 CPU_ID_MFC0 \temp, CPU_ID_REG
111 mfc0 \temp, CP0_TCBIND
112#else
113 MFC0 \temp, CP0_CONTEXT
114#endif
115 LONG_SRL \temp, PTEBASE_SHIFT 119 LONG_SRL \temp, PTEBASE_SHIFT
116 LONG_S \stackp, kernelsp(\temp) 120 LONG_S \stackp, kernelsp(\temp)
117 .endm 121 .endm
118#else 122#else
119 .macro get_saved_sp /* Uniprocessor variation */ 123 .macro get_saved_sp /* Uniprocessor variation */
124#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
125 /*
126 * Clear BTB (branch target buffer), forbid RAS (return address
127 * stack) to workaround the Out-of-order Issue in Loongson2F
128 * via its diagnostic register.
129 */
130 move k0, ra
131 jal 1f
132 nop
1331: jal 1f
134 nop
1351: jal 1f
136 nop
1371: jal 1f
138 nop
1391: move ra, k0
140 li k0, 3
141 mtc0 k0, $22
142#endif /* CONFIG_CPU_LOONGSON2F */
120#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 143#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
121 lui k1, %hi(kernelsp) 144 lui k1, %hi(kernelsp)
122#else 145#else
@@ -166,7 +189,6 @@
166 LONG_S $0, PT_R0(sp) 189 LONG_S $0, PT_R0(sp)
167 mfc0 v1, CP0_STATUS 190 mfc0 v1, CP0_STATUS
168 LONG_S $2, PT_R2(sp) 191 LONG_S $2, PT_R2(sp)
169 LONG_S v1, PT_STATUS(sp)
170#ifdef CONFIG_MIPS_MT_SMTC 192#ifdef CONFIG_MIPS_MT_SMTC
171 /* 193 /*
172 * Ideally, these instructions would be shuffled in 194 * Ideally, these instructions would be shuffled in
@@ -178,20 +200,21 @@
178 LONG_S v1, PT_TCSTATUS(sp) 200 LONG_S v1, PT_TCSTATUS(sp)
179#endif /* CONFIG_MIPS_MT_SMTC */ 201#endif /* CONFIG_MIPS_MT_SMTC */
180 LONG_S $4, PT_R4(sp) 202 LONG_S $4, PT_R4(sp)
181 mfc0 v1, CP0_CAUSE
182 LONG_S $5, PT_R5(sp) 203 LONG_S $5, PT_R5(sp)
183 LONG_S v1, PT_CAUSE(sp) 204 LONG_S v1, PT_STATUS(sp)
205 mfc0 v1, CP0_CAUSE
184 LONG_S $6, PT_R6(sp) 206 LONG_S $6, PT_R6(sp)
185 MFC0 v1, CP0_EPC
186 LONG_S $7, PT_R7(sp) 207 LONG_S $7, PT_R7(sp)
208 LONG_S v1, PT_CAUSE(sp)
209 MFC0 v1, CP0_EPC
187#ifdef CONFIG_64BIT 210#ifdef CONFIG_64BIT
188 LONG_S $8, PT_R8(sp) 211 LONG_S $8, PT_R8(sp)
189 LONG_S $9, PT_R9(sp) 212 LONG_S $9, PT_R9(sp)
190#endif 213#endif
191 LONG_S v1, PT_EPC(sp)
192 LONG_S $25, PT_R25(sp) 214 LONG_S $25, PT_R25(sp)
193 LONG_S $28, PT_R28(sp) 215 LONG_S $28, PT_R28(sp)
194 LONG_S $31, PT_R31(sp) 216 LONG_S $31, PT_R31(sp)
217 LONG_S v1, PT_EPC(sp)
195 ori $28, sp, _THREAD_MASK 218 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK 219 xori $28, _THREAD_MASK
197#ifdef CONFIG_CPU_CAVIUM_OCTEON 220#ifdef CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index 83b5509e09e8..bb937ccfba1e 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -95,6 +95,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
95{ 95{
96 __u32 retval; 96 __u32 retval;
97 97
98 smp_mb__before_llsc();
99
98 if (kernel_uses_llsc && R10000_LLSC_WAR) { 100 if (kernel_uses_llsc && R10000_LLSC_WAR) {
99 unsigned long dummy; 101 unsigned long dummy;
100 102
@@ -147,6 +149,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
147{ 149{
148 __u64 retval; 150 __u64 retval;
149 151
152 smp_mb__before_llsc();
153
150 if (kernel_uses_llsc && R10000_LLSC_WAR) { 154 if (kernel_uses_llsc && R10000_LLSC_WAR) {
151 unsigned long dummy; 155 unsigned long dummy;
152 156
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index df6a430de5eb..c7f1bfef1574 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -84,8 +84,16 @@ static inline int init_mips_clocksource(void)
84#endif 84#endif
85} 85}
86 86
87extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); 87static inline void clocksource_set_clock(struct clocksource *cs,
88extern void clockevent_set_clock(struct clock_event_device *cd, 88 unsigned int clock)
89 unsigned int clock); 89{
90 clocksource_calc_mult_shift(cs, clock, 4);
91}
92
93static inline void clockevent_set_clock(struct clock_event_device *cd,
94 unsigned int clock)
95{
96 clockevents_calc_mult_shift(cd, clock, 4);
97}
90 98
91#endif /* _ASM_TIME_H */ 99#endif /* _ASM_TIME_H */
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 827dc22be2ea..64887d3c7ec3 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -42,7 +42,6 @@ struct txx9_board_vec {
42}; 42};
43extern struct txx9_board_vec *txx9_board_vec; 43extern struct txx9_board_vec *txx9_board_vec;
44extern int (*txx9_irq_dispatch)(int pending); 44extern int (*txx9_irq_dispatch)(int pending);
45char *prom_getcmdline(void);
46const char *prom_getenv(const char *name); 45const char *prom_getenv(const char *name);
47void txx9_wdt_init(unsigned long base); 46void txx9_wdt_init(unsigned long base);
48void txx9_wdt_now(unsigned long base); 47void txx9_wdt_now(unsigned long base);
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
new file mode 100644
index 000000000000..697e40c06497
--- /dev/null
+++ b/arch/mips/include/asm/uasm.h
@@ -0,0 +1,215 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
7 * Copyright (C) 2005 Maciej W. Rozycki
8 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
9 */
10
11#include <linux/types.h>
12
13#define Ip_u1u2u3(op) \
14void __cpuinit \
15uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
16
17#define Ip_u2u1u3(op) \
18void __cpuinit \
19uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
20
21#define Ip_u3u1u2(op) \
22void __cpuinit \
23uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
24
25#define Ip_u1u2s3(op) \
26void __cpuinit \
27uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
28
29#define Ip_u2s3u1(op) \
30void __cpuinit \
31uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
32
33#define Ip_u2u1s3(op) \
34void __cpuinit \
35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
36
37#define Ip_u2u1msbu3(op) \
38void __cpuinit \
39uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
40 unsigned int d)
41
42#define Ip_u1u2(op) \
43void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
44
45#define Ip_u1s2(op) \
46void __cpuinit uasm_i##op(u32 **buf, unsigned int a, signed int b)
47
48#define Ip_u1(op) void __cpuinit uasm_i##op(u32 **buf, unsigned int a)
49
50#define Ip_0(op) void __cpuinit uasm_i##op(u32 **buf)
51
52Ip_u2u1s3(_addiu);
53Ip_u3u1u2(_addu);
54Ip_u2u1u3(_andi);
55Ip_u3u1u2(_and);
56Ip_u1u2s3(_beq);
57Ip_u1u2s3(_beql);
58Ip_u1s2(_bgez);
59Ip_u1s2(_bgezl);
60Ip_u1s2(_bltz);
61Ip_u1s2(_bltzl);
62Ip_u1u2s3(_bne);
63Ip_u2s3u1(_cache);
64Ip_u1u2u3(_dmfc0);
65Ip_u1u2u3(_dmtc0);
66Ip_u2u1s3(_daddiu);
67Ip_u3u1u2(_daddu);
68Ip_u2u1u3(_dsll);
69Ip_u2u1u3(_dsll32);
70Ip_u2u1u3(_dsra);
71Ip_u2u1u3(_dsrl);
72Ip_u2u1u3(_dsrl32);
73Ip_u2u1u3(_drotr);
74Ip_u3u1u2(_dsubu);
75Ip_0(_eret);
76Ip_u1(_j);
77Ip_u1(_jal);
78Ip_u1(_jr);
79Ip_u2s3u1(_ld);
80Ip_u2s3u1(_ll);
81Ip_u2s3u1(_lld);
82Ip_u1s2(_lui);
83Ip_u2s3u1(_lw);
84Ip_u1u2u3(_mfc0);
85Ip_u1u2u3(_mtc0);
86Ip_u2u1u3(_ori);
87Ip_u3u1u2(_or);
88Ip_u2s3u1(_pref);
89Ip_0(_rfe);
90Ip_u2s3u1(_sc);
91Ip_u2s3u1(_scd);
92Ip_u2s3u1(_sd);
93Ip_u2u1u3(_sll);
94Ip_u2u1u3(_sra);
95Ip_u2u1u3(_srl);
96Ip_u2u1u3(_rotr);
97Ip_u3u1u2(_subu);
98Ip_u2s3u1(_sw);
99Ip_0(_tlbp);
100Ip_0(_tlbr);
101Ip_0(_tlbwi);
102Ip_0(_tlbwr);
103Ip_u3u1u2(_xor);
104Ip_u2u1u3(_xori);
105Ip_u2u1msbu3(_dins);
106Ip_u1(_syscall);
107
108/* Handle labels. */
109struct uasm_label {
110 u32 *addr;
111 int lab;
112};
113
114void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
115#ifdef CONFIG_64BIT
116int uasm_in_compat_space_p(long addr);
117#endif
118int uasm_rel_hi(long val);
119int uasm_rel_lo(long val);
120void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
121void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
122
123#define UASM_L_LA(lb) \
124static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
125{ \
126 uasm_build_label(lab, addr, label##lb); \
127}
128
129/* convenience macros for instructions */
130#ifdef CONFIG_64BIT
131# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off)
132# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
133# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
134# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
135# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
136# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
137# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
138# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
139# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
140# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
141# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
142# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
143# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
144#else
145# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
146# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
147# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
148# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
149# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
150# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
151# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
152# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
153# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
154# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
155# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
156# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
157# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
158#endif
159
160#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)
161#define uasm_i_beqz(buf, rs, off) uasm_i_beq(buf, rs, 0, off)
162#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off)
163#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off)
164#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
165#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
166#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
167#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
168#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
169
170static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
171 unsigned int a2, unsigned int a3)
172{
173 if (a3 < 32)
174 uasm_i_dsrl(p, a1, a2, a3);
175 else
176 uasm_i_dsrl32(p, a1, a2, a3 - 32);
177}
178
179static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
180 unsigned int a2, unsigned int a3)
181{
182 if (a3 < 32)
183 uasm_i_dsll(p, a1, a2, a3);
184 else
185 uasm_i_dsll32(p, a1, a2, a3 - 32);
186}
187
188/* Handle relocations. */
189struct uasm_reloc {
190 u32 *addr;
191 unsigned int type;
192 int lab;
193};
194
195/* This is zero so we can use zeroed label arrays. */
196#define UASM_LABEL_INVALID 0
197
198void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid);
199void uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab);
200void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off);
201void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off);
202void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
203 u32 *first, u32 *end, u32 *target);
204int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
205
206/* Convenience functions for labeled branches. */
207void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
208void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
209void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
210void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
211void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
212 unsigned int reg2, int lid);
213void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
214void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
215void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h
index 8a4b20e88b81..9bc07b9f30fb 100644
--- a/arch/mips/include/asm/ucontext.h
+++ b/arch/mips/include/asm/ucontext.h
@@ -1,21 +1 @@
1/* #include <asm-generic/ucontext.h>
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Low level exception handling
7 *
8 * Copyright (C) 1998, 1999 by Ralf Baechle
9 */
10#ifndef _ASM_UCONTEXT_H
11#define _ASM_UCONTEXT_H
12
13struct ucontext {
14 unsigned long uc_flags;
15 struct ucontext *uc_link;
16 stack_t uc_stack;
17 struct sigcontext uc_mcontext;
18 sigset_t uc_sigmask; /* mask last for extensibility */
19};
20
21#endif /* _ASM_UCONTEXT_H */
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 8c9dfa9e9018..1b5a6648eb86 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -355,16 +355,17 @@
355#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332) 355#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332)
356#define __NR_perf_event_open (__NR_Linux + 333) 356#define __NR_perf_event_open (__NR_Linux + 333)
357#define __NR_accept4 (__NR_Linux + 334) 357#define __NR_accept4 (__NR_Linux + 334)
358#define __NR_recvmmsg (__NR_Linux + 335)
358 359
359/* 360/*
360 * Offset of the last Linux o32 flavoured syscall 361 * Offset of the last Linux o32 flavoured syscall
361 */ 362 */
362#define __NR_Linux_syscalls 334 363#define __NR_Linux_syscalls 335
363 364
364#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 365#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
365 366
366#define __NR_O32_Linux 4000 367#define __NR_O32_Linux 4000
367#define __NR_O32_Linux_syscalls 334 368#define __NR_O32_Linux_syscalls 335
368 369
369#if _MIPS_SIM == _MIPS_SIM_ABI64 370#if _MIPS_SIM == _MIPS_SIM_ABI64
370 371
@@ -666,16 +667,17 @@
666#define __NR_rt_tgsigqueueinfo (__NR_Linux + 291) 667#define __NR_rt_tgsigqueueinfo (__NR_Linux + 291)
667#define __NR_perf_event_open (__NR_Linux + 292) 668#define __NR_perf_event_open (__NR_Linux + 292)
668#define __NR_accept4 (__NR_Linux + 293) 669#define __NR_accept4 (__NR_Linux + 293)
670#define __NR_recvmmsg (__NR_Linux + 294)
669 671
670/* 672/*
671 * Offset of the last Linux 64-bit flavoured syscall 673 * Offset of the last Linux 64-bit flavoured syscall
672 */ 674 */
673#define __NR_Linux_syscalls 293 675#define __NR_Linux_syscalls 294
674 676
675#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 677#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
676 678
677#define __NR_64_Linux 5000 679#define __NR_64_Linux 5000
678#define __NR_64_Linux_syscalls 293 680#define __NR_64_Linux_syscalls 294
679 681
680#if _MIPS_SIM == _MIPS_SIM_NABI32 682#if _MIPS_SIM == _MIPS_SIM_NABI32
681 683
@@ -981,16 +983,17 @@
981#define __NR_rt_tgsigqueueinfo (__NR_Linux + 295) 983#define __NR_rt_tgsigqueueinfo (__NR_Linux + 295)
982#define __NR_perf_event_open (__NR_Linux + 296) 984#define __NR_perf_event_open (__NR_Linux + 296)
983#define __NR_accept4 (__NR_Linux + 297) 985#define __NR_accept4 (__NR_Linux + 297)
986#define __NR_recvmmsg (__NR_Linux + 298)
984 987
985/* 988/*
986 * Offset of the last N32 flavoured syscall 989 * Offset of the last N32 flavoured syscall
987 */ 990 */
988#define __NR_Linux_syscalls 297 991#define __NR_Linux_syscalls 298
989 992
990#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 993#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
991 994
992#define __NR_N32_Linux 6000 995#define __NR_N32_Linux 6000
993#define __NR_N32_Linux_syscalls 297 996#define __NR_N32_Linux_syscalls 298
994 997
995#ifdef __KERNEL__ 998#ifdef __KERNEL__
996 999
@@ -1001,6 +1004,7 @@
1001#define __ARCH_WANT_OLD_READDIR 1004#define __ARCH_WANT_OLD_READDIR
1002#define __ARCH_WANT_SYS_ALARM 1005#define __ARCH_WANT_SYS_ALARM
1003#define __ARCH_WANT_SYS_GETHOSTNAME 1006#define __ARCH_WANT_SYS_GETHOSTNAME
1007#define __ARCH_WANT_SYS_IPC
1004#define __ARCH_WANT_SYS_PAUSE 1008#define __ARCH_WANT_SYS_PAUSE
1005#define __ARCH_WANT_SYS_SGETMASK 1009#define __ARCH_WANT_SYS_SGETMASK
1006#define __ARCH_WANT_SYS_UTIME 1010#define __ARCH_WANT_SYS_UTIME
@@ -1010,6 +1014,7 @@
1010#define __ARCH_WANT_SYS_LLSEEK 1014#define __ARCH_WANT_SYS_LLSEEK
1011#define __ARCH_WANT_SYS_NICE 1015#define __ARCH_WANT_SYS_NICE
1012#define __ARCH_WANT_SYS_OLD_GETRLIMIT 1016#define __ARCH_WANT_SYS_OLD_GETRLIMIT
1017#define __ARCH_WANT_SYS_OLD_UNAME
1013#define __ARCH_WANT_SYS_OLDUMOUNT 1018#define __ARCH_WANT_SYS_OLDUMOUNT
1014#define __ARCH_WANT_SYS_SIGPENDING 1019#define __ARCH_WANT_SYS_SIGPENDING
1015#define __ARCH_WANT_SYS_SIGPROCMASK 1020#define __ARCH_WANT_SYS_SIGPROCMASK
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
new file mode 100644
index 000000000000..cca56aa40ff4
--- /dev/null
+++ b/arch/mips/include/asm/vdso.h
@@ -0,0 +1,29 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Cavium Networks
7 */
8
9#ifndef __ASM_VDSO_H
10#define __ASM_VDSO_H
11
12#include <linux/types.h>
13
14
15#ifdef CONFIG_32BIT
16struct mips_vdso {
17 u32 signal_trampoline[2];
18 u32 rt_signal_trampoline[2];
19};
20#else /* !CONFIG_32BIT */
21struct mips_vdso {
22 u32 o32_signal_trampoline[2];
23 u32 o32_rt_signal_trampoline[2];
24 u32 rt_signal_trampoline[2];
25 u32 n32_rt_signal_trampoline[2];
26};
27#endif /* CONFIG_32BIT */
28
29#endif /* __ASM_VDSO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-02 19:24:34 -0400