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-rw-r--r--arch/mips/include/asm/bitops.h114
-rw-r--r--arch/mips/include/asm/break.h1
-rw-r--r--arch/mips/include/asm/byteorder.h40
-rw-r--r--arch/mips/include/asm/cpu-features.h2
-rw-r--r--arch/mips/include/asm/ds1286.h15
-rw-r--r--arch/mips/include/asm/emma/emma2rh.h (renamed from arch/mips/include/asm/emma2rh/emma2rh.h)15
-rw-r--r--arch/mips/include/asm/emma/markeins.h (renamed from arch/mips/include/asm/emma2rh/markeins.h)0
-rw-r--r--arch/mips/include/asm/fpu_emulator.h17
-rw-r--r--arch/mips/include/asm/m48t35.h27
-rw-r--r--arch/mips/include/asm/mach-lemote/pci.h30
-rw-r--r--arch/mips/include/asm/mach-pnx833x/gpio.h172
-rw-r--r--arch/mips/include/asm/mach-pnx833x/irq-mapping.h126
-rw-r--r--arch/mips/include/asm/mach-pnx833x/irq.h53
-rw-r--r--arch/mips/include/asm/mach-pnx833x/pnx833x.h202
-rw-r--r--arch/mips/include/asm/mach-pnx833x/war.h25
-rw-r--r--arch/mips/include/asm/mach-tx49xx/mangle-port.h26
-rw-r--r--arch/mips/include/asm/mipsregs.h1
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/ptrace.h17
-rw-r--r--arch/mips/include/asm/txx9/generic.h5
20 files changed, 769 insertions, 121 deletions
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 49df8c4c9d25..bac4a960b24c 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -558,39 +558,67 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
558 __clear_bit(nr, addr); 558 __clear_bit(nr, addr);
559} 559}
560 560
561#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
562
563/* 561/*
564 * Return the bit position (0..63) of the most significant 1 bit in a word 562 * Return the bit position (0..63) of the most significant 1 bit in a word
565 * Returns -1 if no 1 bit exists 563 * Returns -1 if no 1 bit exists
566 */ 564 */
567static inline unsigned long __fls(unsigned long x) 565static inline unsigned long __fls(unsigned long word)
568{ 566{
569 int lz; 567 int num;
570 568
571 if (sizeof(x) == 4) { 569 if (BITS_PER_LONG == 32 &&
570 __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
572 __asm__( 571 __asm__(
573 " .set push \n" 572 " .set push \n"
574 " .set mips32 \n" 573 " .set mips32 \n"
575 " clz %0, %1 \n" 574 " clz %0, %1 \n"
576 " .set pop \n" 575 " .set pop \n"
577 : "=r" (lz) 576 : "=r" (num)
578 : "r" (x)); 577 : "r" (word));
579 578
580 return 31 - lz; 579 return 31 - num;
581 } 580 }
582 581
583 BUG_ON(sizeof(x) != 8); 582 if (BITS_PER_LONG == 64 &&
583 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
584 __asm__(
585 " .set push \n"
586 " .set mips64 \n"
587 " dclz %0, %1 \n"
588 " .set pop \n"
589 : "=r" (num)
590 : "r" (word));
584 591
585 __asm__( 592 return 63 - num;
586 " .set push \n" 593 }
587 " .set mips64 \n" 594
588 " dclz %0, %1 \n" 595 num = BITS_PER_LONG - 1;
589 " .set pop \n"
590 : "=r" (lz)
591 : "r" (x));
592 596
593 return 63 - lz; 597#if BITS_PER_LONG == 64
598 if (!(word & (~0ul << 32))) {
599 num -= 32;
600 word <<= 32;
601 }
602#endif
603 if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
604 num -= 16;
605 word <<= 16;
606 }
607 if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
608 num -= 8;
609 word <<= 8;
610 }
611 if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
612 num -= 4;
613 word <<= 4;
614 }
615 if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
616 num -= 2;
617 word <<= 2;
618 }
619 if (!(word & (~0ul << (BITS_PER_LONG-1))))
620 num -= 1;
621 return num;
594} 622}
595 623
596/* 624/*
@@ -612,23 +640,43 @@ static inline unsigned long __ffs(unsigned long word)
612 * This is defined the same way as ffs. 640 * This is defined the same way as ffs.
613 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. 641 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
614 */ 642 */
615static inline int fls(int word) 643static inline int fls(int x)
616{ 644{
617 __asm__("clz %0, %1" : "=r" (word) : "r" (word)); 645 int r;
618 646
619 return 32 - word; 647 if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
620} 648 __asm__("clz %0, %1" : "=r" (x) : "r" (x));
621 649
622#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) 650 return 32 - x;
623static inline int fls64(__u64 word) 651 }
624{
625 __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
626 652
627 return 64 - word; 653 r = 32;
654 if (!x)
655 return 0;
656 if (!(x & 0xffff0000u)) {
657 x <<= 16;
658 r -= 16;
659 }
660 if (!(x & 0xff000000u)) {
661 x <<= 8;
662 r -= 8;
663 }
664 if (!(x & 0xf0000000u)) {
665 x <<= 4;
666 r -= 4;
667 }
668 if (!(x & 0xc0000000u)) {
669 x <<= 2;
670 r -= 2;
671 }
672 if (!(x & 0x80000000u)) {
673 x <<= 1;
674 r -= 1;
675 }
676 return r;
628} 677}
629#else 678
630#include <asm-generic/bitops/fls64.h> 679#include <asm-generic/bitops/fls64.h>
631#endif
632 680
633/* 681/*
634 * ffs - find first bit set. 682 * ffs - find first bit set.
@@ -646,16 +694,6 @@ static inline int ffs(int word)
646 return fls(word & -word); 694 return fls(word & -word);
647} 695}
648 696
649#else
650
651#include <asm-generic/bitops/__ffs.h>
652#include <asm-generic/bitops/__fls.h>
653#include <asm-generic/bitops/ffs.h>
654#include <asm-generic/bitops/fls.h>
655#include <asm-generic/bitops/fls64.h>
656
657#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
658
659#include <asm-generic/bitops/ffz.h> 697#include <asm-generic/bitops/ffz.h>
660#include <asm-generic/bitops/find.h> 698#include <asm-generic/bitops/find.h>
661 699
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 25b980c91e7e..44437ed765e8 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -29,6 +29,7 @@
29#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ 29#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */
30#define BRK_BUG 512 /* Used by BUG() */ 30#define BRK_BUG 512 /* Used by BUG() */
31#define BRK_KDB 513 /* Used in KDB_ENTER() */ 31#define BRK_KDB 513 /* Used in KDB_ENTER() */
32#define BRK_MEMU 514 /* Used by FPU emulator */
32#define BRK_MULOVF 1023 /* Multiply overflow */ 33#define BRK_MULOVF 1023 /* Multiply overflow */
33 34
34#endif /* __ASM_BREAK_H */ 35#endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index fe7dc2d59b69..2988d29a0867 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -11,11 +11,19 @@
11#include <linux/compiler.h> 11#include <linux/compiler.h>
12#include <asm/types.h> 12#include <asm/types.h>
13 13
14#ifdef __GNUC__ 14#if defined(__MIPSEB__)
15# define __BIG_ENDIAN
16#elif defined(__MIPSEL__)
17# define __LITTLE_ENDIAN
18#else
19# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
20#endif
21
22#define __SWAB_64_THRU_32__
15 23
16#ifdef CONFIG_CPU_MIPSR2 24#ifdef CONFIG_CPU_MIPSR2
17 25
18static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) 26static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
19{ 27{
20 __asm__( 28 __asm__(
21 " wsbh %0, %1 \n" 29 " wsbh %0, %1 \n"
@@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
24 32
25 return x; 33 return x;
26} 34}
27#define __arch__swab16(x) ___arch__swab16(x) 35#define __arch_swab16 __arch_swab16
28 36
29static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) 37static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
30{ 38{
31 __asm__( 39 __asm__(
32 " wsbh %0, %1 \n" 40 " wsbh %0, %1 \n"
@@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
36 44
37 return x; 45 return x;
38} 46}
39#define __arch__swab32(x) ___arch__swab32(x) 47#define __arch_swab32 __arch_swab32
40 48
41#ifdef CONFIG_CPU_MIPS64_R2 49#ifdef CONFIG_CPU_MIPS64_R2
42 50static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
43static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
44{ 51{
45 __asm__( 52 __asm__(
46 " dsbh %0, %1 \n" 53 " dsbh %0, %1 \n"
@@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
51 58
52 return x; 59 return x;
53} 60}
54 61#define __arch_swab64 __arch_swab64
55#define __arch__swab64(x) ___arch__swab64(x)
56
57#endif /* CONFIG_CPU_MIPS64_R2 */ 62#endif /* CONFIG_CPU_MIPS64_R2 */
58 63
59#endif /* CONFIG_CPU_MIPSR2 */ 64#endif /* CONFIG_CPU_MIPSR2 */
60 65
61#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) 66#include <linux/byteorder.h>
62# define __BYTEORDER_HAS_U64__
63# define __SWAB_64_THRU_32__
64#endif
65
66#endif /* __GNUC__ */
67
68#if defined(__MIPSEB__)
69# include <linux/byteorder/big_endian.h>
70#elif defined(__MIPSEL__)
71# include <linux/byteorder/little_endian.h>
72#else
73# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
74#endif
75 67
76#endif /* _ASM_BYTEORDER_H */ 68#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 5ea701fc3425..12d12dfe73c0 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -141,6 +141,8 @@
141#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 141#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
142#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 142#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
143#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 143#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
144#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
145 cpu_has_mips64r1 | cpu_has_mips64r2)
144 146
145#ifndef cpu_has_dsp 147#ifndef cpu_has_dsp
146#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 148#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h
deleted file mode 100644
index 6983b6ff0af3..000000000000
--- a/arch/mips/include/asm/ds1286.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Machine dependent access functions for RTC registers.
7 *
8 * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
9 */
10#ifndef _ASM_DS1286_H
11#define _ASM_DS1286_H
12
13#include <ds1286.h>
14
15#endif /* _ASM_DS1286_H */
diff --git a/arch/mips/include/asm/emma2rh/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 6a1af0af51e3..30aea91de626 100644
--- a/arch/mips/include/asm/emma2rh/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-mips/emma2rh/emma2rh.h 2 * arch/mips/include/asm/emma/emma2rh.h
3 * This file is EMMA2RH common header. 3 * This file is EMMA2RH common header.
4 * 4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006 5 * Copyright (C) NEC Electronics Corporation 2005-2006
@@ -21,8 +21,8 @@
21 * along with this program; if not, write to the Free Software 21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */ 23 */
24#ifndef __ASM_EMMA2RH_EMMA2RH_H 24#ifndef __ASM_EMMA_EMMA2RH_H
25#define __ASM_EMMA2RH_EMMA2RH_H 25#define __ASM_EMMA_EMMA2RH_H
26 26
27#include <irq.h> 27#include <irq.h>
28 28
@@ -206,7 +206,6 @@ static inline void emma2rh_out32(u32 offset, u32 val)
206static inline u32 emma2rh_in32(u32 offset) 206static inline u32 emma2rh_in32(u32 offset)
207{ 207{
208 u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); 208 u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
209 emma2rh_sync();
210 return val; 209 return val;
211} 210}
212 211
@@ -219,7 +218,6 @@ static inline void emma2rh_out16(u32 offset, u16 val)
219static inline u16 emma2rh_in16(u32 offset) 218static inline u16 emma2rh_in16(u32 offset)
220{ 219{
221 u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); 220 u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
222 emma2rh_sync();
223 return val; 221 return val;
224} 222}
225 223
@@ -232,7 +230,6 @@ static inline void emma2rh_out8(u32 offset, u8 val)
232static inline u8 emma2rh_in8(u32 offset) 230static inline u8 emma2rh_in8(u32 offset)
233{ 231{
234 u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); 232 u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
235 emma2rh_sync();
236 return val; 233 return val;
237} 234}
238 235
@@ -324,10 +321,10 @@ static inline u8 emma2rh_in8(u32 offset)
324/* 321/*
325 * include the board dependent part 322 * include the board dependent part
326 */ 323 */
327#if defined(CONFIG_MARKEINS) 324#ifdef CONFIG_NEC_MARKEINS
328#include <asm/emma2rh/markeins.h> 325#include <asm/emma/markeins.h>
329#else 326#else
330#error "Unknown EMMA2RH board!" 327#error "Unknown EMMA2RH board!"
331#endif 328#endif
332 329
333#endif /* __ASM_EMMA2RH_EMMA2RH_H */ 330#endif /* __ASM_EMMA_EMMA2RH_H */
diff --git a/arch/mips/include/asm/emma2rh/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 973b0628490d..973b0628490d 100644
--- a/arch/mips/include/asm/emma2rh/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index 2731c38bd7ae..e5189572956c 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -23,6 +23,9 @@
23#ifndef _ASM_FPU_EMULATOR_H 23#ifndef _ASM_FPU_EMULATOR_H
24#define _ASM_FPU_EMULATOR_H 24#define _ASM_FPU_EMULATOR_H
25 25
26#include <asm/break.h>
27#include <asm/inst.h>
28
26struct mips_fpu_emulator_stats { 29struct mips_fpu_emulator_stats {
27 unsigned int emulated; 30 unsigned int emulated;
28 unsigned int loads; 31 unsigned int loads;
@@ -34,4 +37,18 @@ struct mips_fpu_emulator_stats {
34 37
35extern struct mips_fpu_emulator_stats fpuemustats; 38extern struct mips_fpu_emulator_stats fpuemustats;
36 39
40extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
41 unsigned long cpc);
42extern int do_dsemulret(struct pt_regs *xcp);
43
44/*
45 * Instruction inserted following the badinst to further tag the sequence
46 */
47#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */
48
49/*
50 * Break instruction with special math emu break code set
51 */
52#define BREAK_MATH (0x0000000d | (BRK_MEMU << 16))
53
37#endif /* _ASM_FPU_EMULATOR_H */ 54#endif /* _ASM_FPU_EMULATOR_H */
diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h
deleted file mode 100644
index f44852e9a96d..000000000000
--- a/arch/mips/include/asm/m48t35.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
3 */
4#ifndef _ASM_M48T35_H
5#define _ASM_M48T35_H
6
7#include <linux/spinlock.h>
8
9extern spinlock_t rtc_lock;
10
11struct m48t35_rtc {
12 volatile u8 pad[0x7ff8]; /* starts at 0x7ff8 */
13 volatile u8 control;
14 volatile u8 sec;
15 volatile u8 min;
16 volatile u8 hour;
17 volatile u8 day;
18 volatile u8 date;
19 volatile u8 month;
20 volatile u8 year;
21};
22
23#define M48T35_RTC_SET 0x80
24#define M48T35_RTC_STOPPED 0x80
25#define M48T35_RTC_READ 0x40
26
27#endif /* _ASM_M48T35_H */
diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h
new file mode 100644
index 000000000000..ea6aa143b78e
--- /dev/null
+++ b/arch/mips/include/asm/mach-lemote/pci.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
3 *
4 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General
6 * Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be
11 * useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public
17 * License along with this program; if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
19 * 02139, USA.
20 */
21
22#ifndef _LEMOTE_PCI_H_
23#define _LEMOTE_PCI_H_
24
25#define LOONGSON2E_PCI_MEM_START 0x14000000UL
26#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL
27#define LOONGSON2E_PCI_IO_START 0x00004000UL
28#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL
29
30#endif /* !_LEMOTE_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h
new file mode 100644
index 000000000000..8de0eb9c98a3
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/gpio.h
@@ -0,0 +1,172 @@
1/*
2 * gpio.h: GPIO Support for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
23#define __ASM_MIPS_MACH_PNX833X_GPIO_H
24
25/* BIG FAT WARNING: races danger!
26 No protections exist here. Current users are only early init code,
27 when locking is not needed because no cuncurency yet exists there,
28 and GPIO IRQ dispatcher, which does locking.
29 However, if many uses will ever happen, proper locking will be needed
30 - including locking between different uses
31*/
32
33#include "pnx833x.h"
34
35#define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0)
36#define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0)
37
38/* Initialize GPIO to a known state */
39static inline void pnx833x_gpio_init(void)
40{
41 PNX833X_PIO_DIR = 0;
42 PNX833X_PIO_DIR2 = 0;
43 PNX833X_PIO_SEL = 0;
44 PNX833X_PIO_SEL2 = 0;
45 PNX833X_PIO_INT_EDGE = 0;
46 PNX833X_PIO_INT_HI = 0;
47 PNX833X_PIO_INT_LO = 0;
48
49 /* clear any GPIO interrupt requests */
50 PNX833X_PIO_INT_CLEAR = 0xffff;
51 PNX833X_PIO_INT_CLEAR = 0;
52 PNX833X_PIO_INT_ENABLE = 0;
53}
54
55/* Select GPIO direction for a pin */
56static inline void pnx833x_gpio_select_input(unsigned int pin)
57{
58 if (pin < 32)
59 CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
60 else
61 CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
62}
63static inline void pnx833x_gpio_select_output(unsigned int pin)
64{
65 if (pin < 32)
66 SET_REG_BIT(PNX833X_PIO_DIR, pin);
67 else
68 SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
69}
70
71/* Select GPIO or alternate function for a pin */
72static inline void pnx833x_gpio_select_function_io(unsigned int pin)
73{
74 if (pin < 32)
75 CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
76 else
77 CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
78}
79static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
80{
81 if (pin < 32)
82 SET_REG_BIT(PNX833X_PIO_SEL, pin);
83 else
84 SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
85}
86
87/* Read GPIO pin */
88static inline int pnx833x_gpio_read(unsigned int pin)
89{
90 if (pin < 32)
91 return (PNX833X_PIO_IN >> pin) & 1;
92 else
93 return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
94}
95
96/* Write GPIO pin */
97static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
98{
99 if (pin < 32) {
100 if (val)
101 SET_REG_BIT(PNX833X_PIO_OUT, pin);
102 else
103 CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
104 } else {
105 if (val)
106 SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
107 else
108 CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
109 }
110}
111
112/* Configure GPIO interrupt */
113#define GPIO_INT_NONE 0
114#define GPIO_INT_LEVEL_LOW 1
115#define GPIO_INT_LEVEL_HIGH 2
116#define GPIO_INT_EDGE_RISING 3
117#define GPIO_INT_EDGE_FALLING 4
118#define GPIO_INT_EDGE_BOTH 5
119static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
120{
121 switch (when) {
122 case GPIO_INT_LEVEL_LOW:
123 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
124 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
125 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
126 break;
127 case GPIO_INT_LEVEL_HIGH:
128 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
129 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
130 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
131 break;
132 case GPIO_INT_EDGE_RISING:
133 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
134 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
135 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
136 break;
137 case GPIO_INT_EDGE_FALLING:
138 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
139 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
140 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
141 break;
142 case GPIO_INT_EDGE_BOTH:
143 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
144 SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
145 SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
146 break;
147 default:
148 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
149 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
150 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
151 break;
152 }
153}
154
155/* Enable/disable GPIO interrupt */
156static inline void pnx833x_gpio_enable_irq(unsigned int pin)
157{
158 SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
159}
160static inline void pnx833x_gpio_disable_irq(unsigned int pin)
161{
162 CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
163}
164
165/* Clear GPIO interrupt request */
166static inline void pnx833x_gpio_clear_irq(unsigned int pin)
167{
168 SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
169 CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
170}
171
172#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
new file mode 100644
index 000000000000..657f089b1724
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
@@ -0,0 +1,126 @@
1
2/*
3 * irq.h: IRQ mappings for PNX833X.
4 *
5 * Copyright 2008 NXP Semiconductors
6 * Chris Steel <chris.steel@nxp.com>
7 * Daniel Laird <daniel.j.laird@nxp.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
25#define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
26/*
27 * The "IRQ numbers" are completely virtual.
28 *
29 * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
30 * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
31 * numbers 49..64 for (virtual) GPIO interrupts.
32 *
33 * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
34 * connected to PIC, which uses core hardware interrupt 2, and also
35 * a timer interrupt through hardware interrupt 5.
36 * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
37 * numbers 65..80 for (virtual) GPIO interrupts.
38 *
39 */
40#include <irq.h>
41
42#define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
43
44/* Interrupts supported by PIC */
45#define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1)
46#define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2)
47#define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3)
48#define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4)
49#define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5)
50#define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6)
51#define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7)
52#define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8)
53#define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9)
54#define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10)
55#define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11)
56#define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12)
57#define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13)
58#define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13)
59#define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14)
60#define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15)
61#define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16)
62#define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17)
63#define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18)
64#define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19)
65#define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20)
66#define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21)
67#define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22)
68#define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23)
69#define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24)
70#define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25)
71#define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26)
72#define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27)
73#define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28)
74#define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29)
75#define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30)
76#define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31)
77#define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32)
78#define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33)
79#define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34)
80#define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35)
81#define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36)
82
83#if defined(CONFIG_SOC_PNX8335)
84#define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37)
85#define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38)
86#define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39)
87#define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40)
88#define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41)
89#define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42)
90#define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43)
91#define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44)
92#define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45)
93#define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46)
94#define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47)
95#define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48)
96#define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49)
97#define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50)
98#define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51)
99#define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52)
100#define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53)
101#define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54)
102#define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55)
103#define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56)
104#define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57)
105#endif
106
107/* GPIO interrupts */
108#define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0)
109#define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1)
110#define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2)
111#define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3)
112#define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4)
113#define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5)
114#define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6)
115#define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7)
116#define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8)
117#define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9)
118#define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10)
119#define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11)
120#define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12)
121#define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13)
122#define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14)
123#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
124
125#endif
126
diff --git a/arch/mips/include/asm/mach-pnx833x/irq.h b/arch/mips/include/asm/mach-pnx833x/irq.h
new file mode 100644
index 000000000000..745114b1d8d5
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/irq.h
@@ -0,0 +1,53 @@
1/*
2 * irq.h: IRQ mappings for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
24#define __ASM_MIPS_MACH_PNX833X_IRQ_H
25/*
26 * The "IRQ numbers" are completely virtual.
27 *
28 * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
29 * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
30 * numbers 49..64 for (virtual) GPIO interrupts.
31 *
32 * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
33 * connected to PIC, which uses core hardware interrupt 2, and also
34 * a timer interrupt through hardware interrupt 5.
35 * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
36 * numbers 65..80 for (virtual) GPIO interrupts.
37 *
38 */
39#if defined(CONFIG_SOC_PNX8335)
40 #define PNX833X_PIC_NUM_IRQ 58
41#else
42 #define PNX833X_PIC_NUM_IRQ 37
43#endif
44
45#define MIPS_CPU_NUM_IRQ 8
46#define PNX833X_GPIO_NUM_IRQ 16
47
48#define MIPS_CPU_IRQ_BASE 0
49#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
50#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
51#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
52
53#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
new file mode 100644
index 000000000000..100f52870e3c
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
@@ -0,0 +1,202 @@
1/*
2 * pnx833x.h: Register mappings for PNX833X.
3 *
4 * Copyright 2008 NXP Semiconductors
5 * Chris Steel <chris.steel@nxp.com>
6 * Daniel Laird <daniel.j.laird@nxp.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
23#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
24
25/* All regs are accessed in KSEG1 */
26#define PNX833X_BASE (0xa0000000ul + 0x17E00000ul)
27
28#define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs)))
29
30/* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */
31
32/* Read access to multibit fields */
33#define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field)
34#define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field)
35
36/* Use PNX833X_FIELD to extract a field from val */
37#define PNX_FIELD(cpu, val, reg, field) \
38 (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
39 PNX##cpu##_##reg##_##field##_SHIFT)
40#define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field)
41#define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field)
42#define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field)
43
44/* Use PNX833X_REGFIELD to extract a field from a register */
45#define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field)
46#define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field)
47#define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field)
48
49
50#define PNX_WRITEFIELD(cpu, val, reg, field) \
51 (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
52 ((val) << PNX##cpu##_##reg##_##field##_SHIFT))
53#define PNX833X_WRITEFIELD(val, reg, field) \
54 PNX_WRITEFIELD(833X, val, reg, field)
55#define PNX8330_WRITEFIELD(val, reg, field) \
56 PNX_WRITEFIELD(8330, val, reg, field)
57#define PNX8335_WRITEFIELD(val, reg, field) \
58 PNX_WRITEFIELD(8335, val, reg, field)
59
60
61/* Macros to detect CPU type */
62
63#define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC)
64#define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000
65#define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12
66#define PNX8330_CONFIG_MODULE_MAJREV 4
67#define PNX8335_CONFIG_MODULE_MAJREV 5
68#define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
69 PNX8330_CONFIG_MODULE_MAJREV)
70#define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \
71 PNX8335_CONFIG_MODULE_MAJREV)
72
73
74
75#define PNX833X_RESET_CONTROL PNX833X_REG(0x8004)
76#define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014)
77
78#define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs))
79#define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0)
80#define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4)
81#define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */
82#define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3
83#define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq))
84
85#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
86#define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */
87#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */
88#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
89
90#define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020)
91#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f
92#define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0
93
94#define PNX833X_CONFIG_MUX PNX833X_REG(0x7004)
95#define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */
96
97#define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040)
98#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000
99#define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19
100
101#define PNX833X_PIO_IN PNX833X_REG(0xF000)
102#define PNX833X_PIO_OUT PNX833X_REG(0xF004)
103#define PNX833X_PIO_DIR PNX833X_REG(0xF008)
104#define PNX833X_PIO_SEL PNX833X_REG(0xF014)
105#define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020)
106#define PNX833X_PIO_INT_HI PNX833X_REG(0xF024)
107#define PNX833X_PIO_INT_LO PNX833X_REG(0xF028)
108#define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0)
109#define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4)
110#define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8)
111#define PNX833X_PIO_IN2 PNX833X_REG(0xF05C)
112#define PNX833X_PIO_OUT2 PNX833X_REG(0xF060)
113#define PNX833X_PIO_DIR2 PNX833X_REG(0xF064)
114#define PNX833X_PIO_SEL2 PNX833X_REG(0xF068)
115
116#define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000)
117#define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF)
118#define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000)
119#define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF)
120
121#define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000)
122#define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF)
123
124#define PNX833X_CONFIG_USB PNX833X_REG(0x7008)
125
126#define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000)
127#define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF)
128#define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000)
129#define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF)
130
131#define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000)
132#define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF)
133#define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC)
134
135#define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
136#define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16
137#define PNX833X_IDE_MODULE_ID_VALUE 0xA009
138
139
140#define PNX833X_MIU_SEL0 PNX833X_REG(0x2004)
141#define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008)
142#define PNX833X_MIU_SEL1 PNX833X_REG(0x200C)
143#define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010)
144#define PNX833X_MIU_SEL2 PNX833X_REG(0x2014)
145#define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018)
146#define PNX833X_MIU_SEL3 PNX833X_REG(0x201C)
147#define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020)
148
149#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14)
150#define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
151
152#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
153#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7
154
155#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9)
156#define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9
157
158#define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000)
159
160#define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3)
161#define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3
162
163#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
164#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2
165
166#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
167#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1
168
169#define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0)
170#define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0
171
172#define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \
173 (PNX833X_MIU_CONFIG_SPI = \
174 ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \
175 ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \
176 ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \
177 ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT))
178
179#define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000)
180#define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF)
181#define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC)
182
183#define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
184#define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16
185#define PNX8335_IP3902_MODULE_ID_VALUE 0x3902
186
187 /* I/O location(gets remapped)*/
188#define PNX8335_NAND_BASE 0x18000000
189/* I/O location with CLE high */
190#define PNX8335_NAND_CLE_MASK 0x00100000
191/* I/O location with ALE high */
192#define PNX8335_NAND_ALE_MASK 0x00010000
193
194#define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000)
195#define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF)
196#define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC)
197
198#define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000
199#define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16
200#define PNX8335_SATA_MODULE_ID_VALUE 0xA099
201
202#endif
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
new file mode 100644
index 000000000000..82cd1e97bc2e
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx833x/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H
9#define __ASM_MIPS_MACH_PNX833X_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
new file mode 100644
index 000000000000..5e6912fdd0ed
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -0,0 +1,26 @@
1#ifndef __ASM_MACH_TX49XX_MANGLE_PORT_H
2#define __ASM_MACH_TX49XX_MANGLE_PORT_H
3
4#define __swizzle_addr_b(port) (port)
5#define __swizzle_addr_w(port) (port)
6#define __swizzle_addr_l(port) (port)
7#define __swizzle_addr_q(port) (port)
8
9#define ioswabb(a, x) (x)
10#define __mem_ioswabb(a, x) (x)
11#if defined(CONFIG_TOSHIBA_RBTX4939) && \
12 (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \
13 defined(__BIG_ENDIAN)
14#define NEEDS_TXX9_IOSWABW
15extern u16 (*ioswabw)(volatile u16 *a, u16 x);
16extern u16 (*__mem_ioswabw)(volatile u16 *a, u16 x);
17#else
18#define ioswabw(a, x) le16_to_cpu(x)
19#define __mem_ioswabw(a, x) (x)
20#endif
21#define ioswabl(a, x) le32_to_cpu(x)
22#define __mem_ioswabl(a, x) (x)
23#define ioswabq(a, x) le64_to_cpu(x)
24#define __mem_ioswabq(a, x) (x)
25
26#endif /* __ASM_MACH_TX49XX_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 979866000da4..9316324d070d 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -192,6 +192,7 @@
192#define PM_16M 0x01ffe000 192#define PM_16M 0x01ffe000
193#define PM_64M 0x07ffe000 193#define PM_64M 0x07ffe000
194#define PM_256M 0x1fffe000 194#define PM_256M 0x1fffe000
195#define PM_1G 0x7fffe000
195 196
196#endif 197#endif
197 198
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index de6d09ebbd80..e2e09b2cd265 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -98,6 +98,8 @@ search_module_dbetables(unsigned long addr)
98#define MODULE_PROC_FAMILY "R5000 " 98#define MODULE_PROC_FAMILY "R5000 "
99#elif defined CONFIG_CPU_R5432 99#elif defined CONFIG_CPU_R5432
100#define MODULE_PROC_FAMILY "R5432 " 100#define MODULE_PROC_FAMILY "R5432 "
101#elif defined CONFIG_CPU_R5500
102#define MODULE_PROC_FAMILY "R5500 "
101#elif defined CONFIG_CPU_R6000 103#elif defined CONFIG_CPU_R6000
102#define MODULE_PROC_FAMILY "R6000 " 104#define MODULE_PROC_FAMILY "R6000 "
103#elif defined CONFIG_CPU_NEVADA 105#elif defined CONFIG_CPU_NEVADA
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 9c22571b160d..813abd16255d 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -80,25 +80,25 @@ enum pt_watch_style {
80 pt_watch_style_mips64 80 pt_watch_style_mips64
81}; 81};
82struct mips32_watch_regs { 82struct mips32_watch_regs {
83 uint32_t watchlo[8]; 83 unsigned int watchlo[8];
84 /* Lower 16 bits of watchhi. */ 84 /* Lower 16 bits of watchhi. */
85 uint16_t watchhi[8]; 85 unsigned short watchhi[8];
86 /* Valid mask and I R W bits. 86 /* Valid mask and I R W bits.
87 * bit 0 -- 1 if W bit is usable. 87 * bit 0 -- 1 if W bit is usable.
88 * bit 1 -- 1 if R bit is usable. 88 * bit 1 -- 1 if R bit is usable.
89 * bit 2 -- 1 if I bit is usable. 89 * bit 2 -- 1 if I bit is usable.
90 * bits 3 - 11 -- Valid watchhi mask bits. 90 * bits 3 - 11 -- Valid watchhi mask bits.
91 */ 91 */
92 uint16_t watch_masks[8]; 92 unsigned short watch_masks[8];
93 /* The number of valid watch register pairs. */ 93 /* The number of valid watch register pairs. */
94 uint32_t num_valid; 94 unsigned int num_valid;
95} __attribute__((aligned(8))); 95} __attribute__((aligned(8)));
96 96
97struct mips64_watch_regs { 97struct mips64_watch_regs {
98 uint64_t watchlo[8]; 98 unsigned long long watchlo[8];
99 uint16_t watchhi[8]; 99 unsigned short watchhi[8];
100 uint16_t watch_masks[8]; 100 unsigned short watch_masks[8];
101 uint32_t num_valid; 101 unsigned int num_valid;
102} __attribute__((aligned(8))); 102} __attribute__((aligned(8)));
103 103
104struct pt_watch_regs { 104struct pt_watch_regs {
@@ -116,6 +116,7 @@ struct pt_watch_regs {
116 116
117#include <linux/compiler.h> 117#include <linux/compiler.h>
118#include <linux/linkage.h> 118#include <linux/linkage.h>
119#include <linux/types.h>
119#include <asm/isadep.h> 120#include <asm/isadep.h>
120 121
121struct task_struct; 122struct task_struct;
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 4316a3e57678..9cde0090cbf6 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -86,4 +86,9 @@ void txx9_iocled_init(unsigned long baseaddr,
86 int basenum, unsigned int num, int lowactive, 86 int basenum, unsigned int num, int lowactive,
87 const char *color, char **deftriggers); 87 const char *color, char **deftriggers);
88 88
89/* 7SEG LED */
90void txx9_7segled_init(unsigned int num,
91 void (*putc)(unsigned int pos, unsigned char val));
92int txx9_7segled_putc(unsigned int pos, char c);
93
89#endif /* __ASM_TXX9_GENERIC_H */ 94#endif /* __ASM_TXX9_GENERIC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 11:47:43 -0500