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-rw-r--r--arch/mips/include/asm/Kbuild1
-rw-r--r--arch/mips/include/asm/asmmacro.h18
-rw-r--r--arch/mips/include/asm/atomic.h42
-rw-r--r--arch/mips/include/asm/bitops.h64
-rw-r--r--arch/mips/include/asm/checksum.h45
-rw-r--r--arch/mips/include/asm/cmpxchg.h34
-rw-r--r--arch/mips/include/asm/compiler.h24
-rw-r--r--arch/mips/include/asm/cpu-features.h28
-rw-r--r--arch/mips/include/asm/cpu-info.h5
-rw-r--r--arch/mips/include/asm/cpu-type.h7
-rw-r--r--arch/mips/include/asm/cpu.h11
-rw-r--r--arch/mips/include/asm/edac.h4
-rw-r--r--arch/mips/include/asm/elf.h10
-rw-r--r--arch/mips/include/asm/fpu.h3
-rw-r--r--arch/mips/include/asm/futex.h24
-rw-r--r--arch/mips/include/asm/gio_device.h2
-rw-r--r--arch/mips/include/asm/hazards.h9
-rw-r--r--arch/mips/include/asm/irqflags.h7
-rw-r--r--arch/mips/include/asm/local.h5
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h64
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/war.h3
-rw-r--r--arch/mips/include/asm/mach-jz4740/jz4740_nand.h2
-rw-r--r--arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h24
-rw-r--r--arch/mips/include/asm/mips-r2-to-r6-emul.h96
-rw-r--r--arch/mips/include/asm/mipsregs.h4
-rw-r--r--arch/mips/include/asm/mmu.h3
-rw-r--r--arch/mips/include/asm/mmu_context.h9
-rw-r--r--arch/mips/include/asm/module.h4
-rw-r--r--arch/mips/include/asm/octeon/cvmx-cmd-queue.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-rst-defs.h306
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h107
-rw-r--r--arch/mips/include/asm/octeon/octeon.h148
-rw-r--r--arch/mips/include/asm/pci.h2
-rw-r--r--arch/mips/include/asm/pgtable-bits.h83
-rw-r--r--arch/mips/include/asm/pgtable.h46
-rw-r--r--arch/mips/include/asm/processor.h19
-rw-r--r--arch/mips/include/asm/prom.h7
-rw-r--r--arch/mips/include/asm/ptrace.h4
-rw-r--r--arch/mips/include/asm/r4kcache.h150
-rw-r--r--arch/mips/include/asm/sgialib.h8
-rw-r--r--arch/mips/include/asm/siginfo.h29
-rw-r--r--arch/mips/include/asm/spinlock.h55
-rw-r--r--arch/mips/include/asm/spram.h4
-rw-r--r--arch/mips/include/asm/stackframe.h8
-rw-r--r--arch/mips/include/asm/switch_to.h9
-rw-r--r--arch/mips/include/asm/thread_info.h2
46 files changed, 1149 insertions, 392 deletions
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 200efeac4181..526539cbc99f 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -1,4 +1,5 @@
1# MIPS headers 1# MIPS headers
2generic-(CONFIG_GENERIC_CSUM) += checksum.h
2generic-y += cputime.h 3generic-y += cputime.h
3generic-y += current.h 4generic-y += current.h
4generic-y += dma-contiguous.h 5generic-y += dma-contiguous.h
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 6caf8766b80f..0cae4595e985 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -19,7 +19,7 @@
19#include <asm/asmmacro-64.h> 19#include <asm/asmmacro-64.h>
20#endif 20#endif
21 21
22#ifdef CONFIG_CPU_MIPSR2 22#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
23 .macro local_irq_enable reg=t0 23 .macro local_irq_enable reg=t0
24 ei 24 ei
25 irq_enable_hazard 25 irq_enable_hazard
@@ -104,7 +104,8 @@
104 .endm 104 .endm
105 105
106 .macro fpu_save_double thread status tmp 106 .macro fpu_save_double thread status tmp
107#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 107#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
108 defined(CONFIG_CPU_MIPS32_R6)
108 sll \tmp, \status, 5 109 sll \tmp, \status, 5
109 bgez \tmp, 10f 110 bgez \tmp, 10f
110 fpu_save_16odd \thread 111 fpu_save_16odd \thread
@@ -160,7 +161,8 @@
160 .endm 161 .endm
161 162
162 .macro fpu_restore_double thread status tmp 163 .macro fpu_restore_double thread status tmp
163#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 164#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
165 defined(CONFIG_CPU_MIPS32_R6)
164 sll \tmp, \status, 5 166 sll \tmp, \status, 5
165 bgez \tmp, 10f # 16 register mode? 167 bgez \tmp, 10f # 16 register mode?
166 168
@@ -170,16 +172,16 @@
170 fpu_restore_16even \thread \tmp 172 fpu_restore_16even \thread \tmp
171 .endm 173 .endm
172 174
173#ifdef CONFIG_CPU_MIPSR2 175#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
174 .macro _EXT rd, rs, p, s 176 .macro _EXT rd, rs, p, s
175 ext \rd, \rs, \p, \s 177 ext \rd, \rs, \p, \s
176 .endm 178 .endm
177#else /* !CONFIG_CPU_MIPSR2 */ 179#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
178 .macro _EXT rd, rs, p, s 180 .macro _EXT rd, rs, p, s
179 srl \rd, \rs, \p 181 srl \rd, \rs, \p
180 andi \rd, \rd, (1 << \s) - 1 182 andi \rd, \rd, (1 << \s) - 1
181 .endm 183 .endm
182#endif /* !CONFIG_CPU_MIPSR2 */ 184#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
183 185
184/* 186/*
185 * Temporary until all gas have MT ASE support 187 * Temporary until all gas have MT ASE support
@@ -304,7 +306,7 @@
304 .set push 306 .set push
305 .set noat 307 .set noat
306 SET_HARDFLOAT 308 SET_HARDFLOAT
307 add $1, \base, \off 309 addu $1, \base, \off
308 .word LDD_MSA_INSN | (\wd << 6) 310 .word LDD_MSA_INSN | (\wd << 6)
309 .set pop 311 .set pop
310 .endm 312 .endm
@@ -313,7 +315,7 @@
313 .set push 315 .set push
314 .set noat 316 .set noat
315 SET_HARDFLOAT 317 SET_HARDFLOAT
316 add $1, \base, \off 318 addu $1, \base, \off
317 .word STD_MSA_INSN | (\wd << 6) 319 .word STD_MSA_INSN | (\wd << 6)
318 .set pop 320 .set pop
319 .endm 321 .endm
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 857da84cfc92..26d436336f2e 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -54,19 +54,19 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \
54 " sc %0, %1 \n" \ 54 " sc %0, %1 \n" \
55 " beqzl %0, 1b \n" \ 55 " beqzl %0, 1b \n" \
56 " .set mips0 \n" \ 56 " .set mips0 \n" \
57 : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \ 57 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
58 : "Ir" (i)); \ 58 : "Ir" (i)); \
59 } else if (kernel_uses_llsc) { \ 59 } else if (kernel_uses_llsc) { \
60 int temp; \ 60 int temp; \
61 \ 61 \
62 do { \ 62 do { \
63 __asm__ __volatile__( \ 63 __asm__ __volatile__( \
64 " .set arch=r4000 \n" \ 64 " .set "MIPS_ISA_LEVEL" \n" \
65 " ll %0, %1 # atomic_" #op "\n" \ 65 " ll %0, %1 # atomic_" #op "\n" \
66 " " #asm_op " %0, %2 \n" \ 66 " " #asm_op " %0, %2 \n" \
67 " sc %0, %1 \n" \ 67 " sc %0, %1 \n" \
68 " .set mips0 \n" \ 68 " .set mips0 \n" \
69 : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \ 69 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
70 : "Ir" (i)); \ 70 : "Ir" (i)); \
71 } while (unlikely(!temp)); \ 71 } while (unlikely(!temp)); \
72 } else { \ 72 } else { \
@@ -97,20 +97,20 @@ static __inline__ int atomic_##op##_return(int i, atomic_t * v) \
97 " " #asm_op " %0, %1, %3 \n" \ 97 " " #asm_op " %0, %1, %3 \n" \
98 " .set mips0 \n" \ 98 " .set mips0 \n" \
99 : "=&r" (result), "=&r" (temp), \ 99 : "=&r" (result), "=&r" (temp), \
100 "+" GCC_OFF12_ASM() (v->counter) \ 100 "+" GCC_OFF_SMALL_ASM() (v->counter) \
101 : "Ir" (i)); \ 101 : "Ir" (i)); \
102 } else if (kernel_uses_llsc) { \ 102 } else if (kernel_uses_llsc) { \
103 int temp; \ 103 int temp; \
104 \ 104 \
105 do { \ 105 do { \
106 __asm__ __volatile__( \ 106 __asm__ __volatile__( \
107 " .set arch=r4000 \n" \ 107 " .set "MIPS_ISA_LEVEL" \n" \
108 " ll %1, %2 # atomic_" #op "_return \n" \ 108 " ll %1, %2 # atomic_" #op "_return \n" \
109 " " #asm_op " %0, %1, %3 \n" \ 109 " " #asm_op " %0, %1, %3 \n" \
110 " sc %0, %2 \n" \ 110 " sc %0, %2 \n" \
111 " .set mips0 \n" \ 111 " .set mips0 \n" \
112 : "=&r" (result), "=&r" (temp), \ 112 : "=&r" (result), "=&r" (temp), \
113 "+" GCC_OFF12_ASM() (v->counter) \ 113 "+" GCC_OFF_SMALL_ASM() (v->counter) \
114 : "Ir" (i)); \ 114 : "Ir" (i)); \
115 } while (unlikely(!result)); \ 115 } while (unlikely(!result)); \
116 \ 116 \
@@ -171,14 +171,14 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
171 "1: \n" 171 "1: \n"
172 " .set mips0 \n" 172 " .set mips0 \n"
173 : "=&r" (result), "=&r" (temp), 173 : "=&r" (result), "=&r" (temp),
174 "+" GCC_OFF12_ASM() (v->counter) 174 "+" GCC_OFF_SMALL_ASM() (v->counter)
175 : "Ir" (i), GCC_OFF12_ASM() (v->counter) 175 : "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
176 : "memory"); 176 : "memory");
177 } else if (kernel_uses_llsc) { 177 } else if (kernel_uses_llsc) {
178 int temp; 178 int temp;
179 179
180 __asm__ __volatile__( 180 __asm__ __volatile__(
181 " .set arch=r4000 \n" 181 " .set "MIPS_ISA_LEVEL" \n"
182 "1: ll %1, %2 # atomic_sub_if_positive\n" 182 "1: ll %1, %2 # atomic_sub_if_positive\n"
183 " subu %0, %1, %3 \n" 183 " subu %0, %1, %3 \n"
184 " bltz %0, 1f \n" 184 " bltz %0, 1f \n"
@@ -190,7 +190,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
190 "1: \n" 190 "1: \n"
191 " .set mips0 \n" 191 " .set mips0 \n"
192 : "=&r" (result), "=&r" (temp), 192 : "=&r" (result), "=&r" (temp),
193 "+" GCC_OFF12_ASM() (v->counter) 193 "+" GCC_OFF_SMALL_ASM() (v->counter)
194 : "Ir" (i)); 194 : "Ir" (i));
195 } else { 195 } else {
196 unsigned long flags; 196 unsigned long flags;
@@ -333,19 +333,19 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \
333 " scd %0, %1 \n" \ 333 " scd %0, %1 \n" \
334 " beqzl %0, 1b \n" \ 334 " beqzl %0, 1b \n" \
335 " .set mips0 \n" \ 335 " .set mips0 \n" \
336 : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \ 336 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
337 : "Ir" (i)); \ 337 : "Ir" (i)); \
338 } else if (kernel_uses_llsc) { \ 338 } else if (kernel_uses_llsc) { \
339 long temp; \ 339 long temp; \
340 \ 340 \
341 do { \ 341 do { \
342 __asm__ __volatile__( \ 342 __asm__ __volatile__( \
343 " .set arch=r4000 \n" \ 343 " .set "MIPS_ISA_LEVEL" \n" \
344 " lld %0, %1 # atomic64_" #op "\n" \ 344 " lld %0, %1 # atomic64_" #op "\n" \
345 " " #asm_op " %0, %2 \n" \ 345 " " #asm_op " %0, %2 \n" \
346 " scd %0, %1 \n" \ 346 " scd %0, %1 \n" \
347 " .set mips0 \n" \ 347 " .set mips0 \n" \
348 : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \ 348 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
349 : "Ir" (i)); \ 349 : "Ir" (i)); \
350 } while (unlikely(!temp)); \ 350 } while (unlikely(!temp)); \
351 } else { \ 351 } else { \
@@ -376,21 +376,21 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \
376 " " #asm_op " %0, %1, %3 \n" \ 376 " " #asm_op " %0, %1, %3 \n" \
377 " .set mips0 \n" \ 377 " .set mips0 \n" \
378 : "=&r" (result), "=&r" (temp), \ 378 : "=&r" (result), "=&r" (temp), \
379 "+" GCC_OFF12_ASM() (v->counter) \ 379 "+" GCC_OFF_SMALL_ASM() (v->counter) \
380 : "Ir" (i)); \ 380 : "Ir" (i)); \
381 } else if (kernel_uses_llsc) { \ 381 } else if (kernel_uses_llsc) { \
382 long temp; \ 382 long temp; \
383 \ 383 \
384 do { \ 384 do { \
385 __asm__ __volatile__( \ 385 __asm__ __volatile__( \
386 " .set arch=r4000 \n" \ 386 " .set "MIPS_ISA_LEVEL" \n" \
387 " lld %1, %2 # atomic64_" #op "_return\n" \ 387 " lld %1, %2 # atomic64_" #op "_return\n" \
388 " " #asm_op " %0, %1, %3 \n" \ 388 " " #asm_op " %0, %1, %3 \n" \
389 " scd %0, %2 \n" \ 389 " scd %0, %2 \n" \
390 " .set mips0 \n" \ 390 " .set mips0 \n" \
391 : "=&r" (result), "=&r" (temp), \ 391 : "=&r" (result), "=&r" (temp), \
392 "=" GCC_OFF12_ASM() (v->counter) \ 392 "=" GCC_OFF_SMALL_ASM() (v->counter) \
393 : "Ir" (i), GCC_OFF12_ASM() (v->counter) \ 393 : "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) \
394 : "memory"); \ 394 : "memory"); \
395 } while (unlikely(!result)); \ 395 } while (unlikely(!result)); \
396 \ 396 \
@@ -452,14 +452,14 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
452 "1: \n" 452 "1: \n"
453 " .set mips0 \n" 453 " .set mips0 \n"
454 : "=&r" (result), "=&r" (temp), 454 : "=&r" (result), "=&r" (temp),
455 "=" GCC_OFF12_ASM() (v->counter) 455 "=" GCC_OFF_SMALL_ASM() (v->counter)
456 : "Ir" (i), GCC_OFF12_ASM() (v->counter) 456 : "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
457 : "memory"); 457 : "memory");
458 } else if (kernel_uses_llsc) { 458 } else if (kernel_uses_llsc) {
459 long temp; 459 long temp;
460 460
461 __asm__ __volatile__( 461 __asm__ __volatile__(
462 " .set arch=r4000 \n" 462 " .set "MIPS_ISA_LEVEL" \n"
463 "1: lld %1, %2 # atomic64_sub_if_positive\n" 463 "1: lld %1, %2 # atomic64_sub_if_positive\n"
464 " dsubu %0, %1, %3 \n" 464 " dsubu %0, %1, %3 \n"
465 " bltz %0, 1f \n" 465 " bltz %0, 1f \n"
@@ -471,7 +471,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
471 "1: \n" 471 "1: \n"
472 " .set mips0 \n" 472 " .set mips0 \n"
473 : "=&r" (result), "=&r" (temp), 473 : "=&r" (result), "=&r" (temp),
474 "+" GCC_OFF12_ASM() (v->counter) 474 "+" GCC_OFF_SMALL_ASM() (v->counter)
475 : "Ir" (i)); 475 : "Ir" (i));
476 } else { 476 } else {
477 unsigned long flags; 477 unsigned long flags;
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 6663bcca9d0c..9f935f6aa996 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -79,28 +79,28 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
79 " " __SC "%0, %1 \n" 79 " " __SC "%0, %1 \n"
80 " beqzl %0, 1b \n" 80 " beqzl %0, 1b \n"
81 " .set mips0 \n" 81 " .set mips0 \n"
82 : "=&r" (temp), "=" GCC_OFF12_ASM() (*m) 82 : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*m)
83 : "ir" (1UL << bit), GCC_OFF12_ASM() (*m)); 83 : "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m));
84#ifdef CONFIG_CPU_MIPSR2 84#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
85 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { 85 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
86 do { 86 do {
87 __asm__ __volatile__( 87 __asm__ __volatile__(
88 " " __LL "%0, %1 # set_bit \n" 88 " " __LL "%0, %1 # set_bit \n"
89 " " __INS "%0, %3, %2, 1 \n" 89 " " __INS "%0, %3, %2, 1 \n"
90 " " __SC "%0, %1 \n" 90 " " __SC "%0, %1 \n"
91 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m) 91 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
92 : "ir" (bit), "r" (~0)); 92 : "ir" (bit), "r" (~0));
93 } while (unlikely(!temp)); 93 } while (unlikely(!temp));
94#endif /* CONFIG_CPU_MIPSR2 */ 94#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
95 } else if (kernel_uses_llsc) { 95 } else if (kernel_uses_llsc) {
96 do { 96 do {
97 __asm__ __volatile__( 97 __asm__ __volatile__(
98 " .set arch=r4000 \n" 98 " .set "MIPS_ISA_ARCH_LEVEL" \n"
99 " " __LL "%0, %1 # set_bit \n" 99 " " __LL "%0, %1 # set_bit \n"
100 " or %0, %2 \n" 100 " or %0, %2 \n"
101 " " __SC "%0, %1 \n" 101 " " __SC "%0, %1 \n"
102 " .set mips0 \n" 102 " .set mips0 \n"
103 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m) 103 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
104 : "ir" (1UL << bit)); 104 : "ir" (1UL << bit));
105 } while (unlikely(!temp)); 105 } while (unlikely(!temp));
106 } else 106 } else
@@ -131,28 +131,28 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
131 " " __SC "%0, %1 \n" 131 " " __SC "%0, %1 \n"
132 " beqzl %0, 1b \n" 132 " beqzl %0, 1b \n"
133 " .set mips0 \n" 133 " .set mips0 \n"
134 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m) 134 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
135 : "ir" (~(1UL << bit))); 135 : "ir" (~(1UL << bit)));
136#ifdef CONFIG_CPU_MIPSR2 136#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
137 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { 137 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
138 do { 138 do {
139 __asm__ __volatile__( 139 __asm__ __volatile__(
140 " " __LL "%0, %1 # clear_bit \n" 140 " " __LL "%0, %1 # clear_bit \n"
141 " " __INS "%0, $0, %2, 1 \n" 141 " " __INS "%0, $0, %2, 1 \n"
142 " " __SC "%0, %1 \n" 142 " " __SC "%0, %1 \n"
143 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m) 143 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
144 : "ir" (bit)); 144 : "ir" (bit));
145 } while (unlikely(!temp)); 145 } while (unlikely(!temp));
146#endif /* CONFIG_CPU_MIPSR2 */ 146#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
147 } else if (kernel_uses_llsc) { 147 } else if (kernel_uses_llsc) {
148 do { 148 do {
149 __asm__ __volatile__( 149 __asm__ __volatile__(
150 " .set arch=r4000 \n" 150 " .set "MIPS_ISA_ARCH_LEVEL" \n"
151 " " __LL "%0, %1 # clear_bit \n" 151 " " __LL "%0, %1 # clear_bit \n"
152 " and %0, %2 \n" 152 " and %0, %2 \n"
153 " " __SC "%0, %1 \n" 153 " " __SC "%0, %1 \n"
154 " .set mips0 \n" 154 " .set mips0 \n"
155 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m) 155 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
156 : "ir" (~(1UL << bit))); 156 : "ir" (~(1UL << bit)));
157 } while (unlikely(!temp)); 157 } while (unlikely(!temp));
158 } else 158 } else
@@ -197,7 +197,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
197 " " __SC "%0, %1 \n" 197 " " __SC "%0, %1 \n"
198 " beqzl %0, 1b \n" 198 " beqzl %0, 1b \n"
199 " .set mips0 \n" 199 " .set mips0 \n"
200 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m) 200 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
201 : "ir" (1UL << bit)); 201 : "ir" (1UL << bit));
202 } else if (kernel_uses_llsc) { 202 } else if (kernel_uses_llsc) {
203 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 203 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -205,12 +205,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
205 205
206 do { 206 do {
207 __asm__ __volatile__( 207 __asm__ __volatile__(
208 " .set arch=r4000 \n" 208 " .set "MIPS_ISA_ARCH_LEVEL" \n"
209 " " __LL "%0, %1 # change_bit \n" 209 " " __LL "%0, %1 # change_bit \n"
210 " xor %0, %2 \n" 210 " xor %0, %2 \n"
211 " " __SC "%0, %1 \n" 211 " " __SC "%0, %1 \n"
212 " .set mips0 \n" 212 " .set mips0 \n"
213 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m) 213 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
214 : "ir" (1UL << bit)); 214 : "ir" (1UL << bit));
215 } while (unlikely(!temp)); 215 } while (unlikely(!temp));
216 } else 216 } else
@@ -245,7 +245,7 @@ static inline int test_and_set_bit(unsigned long nr,
245 " beqzl %2, 1b \n" 245 " beqzl %2, 1b \n"
246 " and %2, %0, %3 \n" 246 " and %2, %0, %3 \n"
247 " .set mips0 \n" 247 " .set mips0 \n"
248 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res) 248 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
249 : "r" (1UL << bit) 249 : "r" (1UL << bit)
250 : "memory"); 250 : "memory");
251 } else if (kernel_uses_llsc) { 251 } else if (kernel_uses_llsc) {
@@ -254,12 +254,12 @@ static inline int test_and_set_bit(unsigned long nr,
254 254
255 do { 255 do {
256 __asm__ __volatile__( 256 __asm__ __volatile__(
257 " .set arch=r4000 \n" 257 " .set "MIPS_ISA_ARCH_LEVEL" \n"
258 " " __LL "%0, %1 # test_and_set_bit \n" 258 " " __LL "%0, %1 # test_and_set_bit \n"
259 " or %2, %0, %3 \n" 259 " or %2, %0, %3 \n"
260 " " __SC "%2, %1 \n" 260 " " __SC "%2, %1 \n"
261 " .set mips0 \n" 261 " .set mips0 \n"
262 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res) 262 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
263 : "r" (1UL << bit) 263 : "r" (1UL << bit)
264 : "memory"); 264 : "memory");
265 } while (unlikely(!res)); 265 } while (unlikely(!res));
@@ -308,12 +308,12 @@ static inline int test_and_set_bit_lock(unsigned long nr,
308 308
309 do { 309 do {
310 __asm__ __volatile__( 310 __asm__ __volatile__(
311 " .set arch=r4000 \n" 311 " .set "MIPS_ISA_ARCH_LEVEL" \n"
312 " " __LL "%0, %1 # test_and_set_bit \n" 312 " " __LL "%0, %1 # test_and_set_bit \n"
313 " or %2, %0, %3 \n" 313 " or %2, %0, %3 \n"
314 " " __SC "%2, %1 \n" 314 " " __SC "%2, %1 \n"
315 " .set mips0 \n" 315 " .set mips0 \n"
316 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res) 316 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
317 : "r" (1UL << bit) 317 : "r" (1UL << bit)
318 : "memory"); 318 : "memory");
319 } while (unlikely(!res)); 319 } while (unlikely(!res));
@@ -355,10 +355,10 @@ static inline int test_and_clear_bit(unsigned long nr,
355 " beqzl %2, 1b \n" 355 " beqzl %2, 1b \n"
356 " and %2, %0, %3 \n" 356 " and %2, %0, %3 \n"
357 " .set mips0 \n" 357 " .set mips0 \n"
358 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res) 358 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
359 : "r" (1UL << bit) 359 : "r" (1UL << bit)
360 : "memory"); 360 : "memory");
361#ifdef CONFIG_CPU_MIPSR2 361#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
362 } else if (kernel_uses_llsc && __builtin_constant_p(nr)) { 362 } else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
363 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 363 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
364 unsigned long temp; 364 unsigned long temp;
@@ -369,7 +369,7 @@ static inline int test_and_clear_bit(unsigned long nr,
369 " " __EXT "%2, %0, %3, 1 \n" 369 " " __EXT "%2, %0, %3, 1 \n"
370 " " __INS "%0, $0, %3, 1 \n" 370 " " __INS "%0, $0, %3, 1 \n"
371 " " __SC "%0, %1 \n" 371 " " __SC "%0, %1 \n"
372 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res) 372 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
373 : "ir" (bit) 373 : "ir" (bit)
374 : "memory"); 374 : "memory");
375 } while (unlikely(!temp)); 375 } while (unlikely(!temp));
@@ -380,13 +380,13 @@ static inline int test_and_clear_bit(unsigned long nr,
380 380
381 do { 381 do {
382 __asm__ __volatile__( 382 __asm__ __volatile__(
383 " .set arch=r4000 \n" 383 " .set "MIPS_ISA_ARCH_LEVEL" \n"
384 " " __LL "%0, %1 # test_and_clear_bit \n" 384 " " __LL "%0, %1 # test_and_clear_bit \n"
385 " or %2, %0, %3 \n" 385 " or %2, %0, %3 \n"
386 " xor %2, %3 \n" 386 " xor %2, %3 \n"
387 " " __SC "%2, %1 \n" 387 " " __SC "%2, %1 \n"
388 " .set mips0 \n" 388 " .set mips0 \n"
389 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res) 389 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
390 : "r" (1UL << bit) 390 : "r" (1UL << bit)
391 : "memory"); 391 : "memory");
392 } while (unlikely(!res)); 392 } while (unlikely(!res));
@@ -428,7 +428,7 @@ static inline int test_and_change_bit(unsigned long nr,
428 " beqzl %2, 1b \n" 428 " beqzl %2, 1b \n"
429 " and %2, %0, %3 \n" 429 " and %2, %0, %3 \n"
430 " .set mips0 \n" 430 " .set mips0 \n"
431 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res) 431 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
432 : "r" (1UL << bit) 432 : "r" (1UL << bit)
433 : "memory"); 433 : "memory");
434 } else if (kernel_uses_llsc) { 434 } else if (kernel_uses_llsc) {
@@ -437,12 +437,12 @@ static inline int test_and_change_bit(unsigned long nr,
437 437
438 do { 438 do {
439 __asm__ __volatile__( 439 __asm__ __volatile__(
440 " .set arch=r4000 \n" 440 " .set "MIPS_ISA_ARCH_LEVEL" \n"
441 " " __LL "%0, %1 # test_and_change_bit \n" 441 " " __LL "%0, %1 # test_and_change_bit \n"
442 " xor %2, %0, %3 \n" 442 " xor %2, %0, %3 \n"
443 " " __SC "\t%2, %1 \n" 443 " " __SC "\t%2, %1 \n"
444 " .set mips0 \n" 444 " .set mips0 \n"
445 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res) 445 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
446 : "r" (1UL << bit) 446 : "r" (1UL << bit)
447 : "memory"); 447 : "memory");
448 } while (unlikely(!res)); 448 } while (unlikely(!res));
@@ -485,7 +485,7 @@ static inline unsigned long __fls(unsigned long word)
485 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { 485 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
486 __asm__( 486 __asm__(
487 " .set push \n" 487 " .set push \n"
488 " .set mips32 \n" 488 " .set "MIPS_ISA_LEVEL" \n"
489 " clz %0, %1 \n" 489 " clz %0, %1 \n"
490 " .set pop \n" 490 " .set pop \n"
491 : "=r" (num) 491 : "=r" (num)
@@ -498,7 +498,7 @@ static inline unsigned long __fls(unsigned long word)
498 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) { 498 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
499 __asm__( 499 __asm__(
500 " .set push \n" 500 " .set push \n"
501 " .set mips64 \n" 501 " .set "MIPS_ISA_LEVEL" \n"
502 " dclz %0, %1 \n" 502 " dclz %0, %1 \n"
503 " .set pop \n" 503 " .set pop \n"
504 : "=r" (num) 504 : "=r" (num)
@@ -562,7 +562,7 @@ static inline int fls(int x)
562 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { 562 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
563 __asm__( 563 __asm__(
564 " .set push \n" 564 " .set push \n"
565 " .set mips32 \n" 565 " .set "MIPS_ISA_LEVEL" \n"
566 " clz %0, %1 \n" 566 " clz %0, %1 \n"
567 " .set pop \n" 567 " .set pop \n"
568 : "=r" (x) 568 : "=r" (x)
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index 3418c51e1151..5c585c5c1c3e 100644
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -12,6 +12,10 @@
12#ifndef _ASM_CHECKSUM_H 12#ifndef _ASM_CHECKSUM_H
13#define _ASM_CHECKSUM_H 13#define _ASM_CHECKSUM_H
14 14
15#ifdef CONFIG_GENERIC_CSUM
16#include <asm-generic/checksum.h>
17#else
18
15#include <linux/in6.h> 19#include <linux/in6.h>
16 20
17#include <asm/uaccess.h> 21#include <asm/uaccess.h>
@@ -99,27 +103,23 @@ __wsum csum_and_copy_to_user(const void *src, void __user *dst, int len,
99 */ 103 */
100__wsum csum_partial_copy_nocheck(const void *src, void *dst, 104__wsum csum_partial_copy_nocheck(const void *src, void *dst,
101 int len, __wsum sum); 105 int len, __wsum sum);
106#define csum_partial_copy_nocheck csum_partial_copy_nocheck
102 107
103/* 108/*
104 * Fold a partial checksum without adding pseudo headers 109 * Fold a partial checksum without adding pseudo headers
105 */ 110 */
106static inline __sum16 csum_fold(__wsum sum) 111static inline __sum16 csum_fold(__wsum csum)
107{ 112{
108 __asm__( 113 u32 sum = (__force u32)csum;;
109 " .set push # csum_fold\n"
110 " .set noat \n"
111 " sll $1, %0, 16 \n"
112 " addu %0, $1 \n"
113 " sltu $1, %0, $1 \n"
114 " srl %0, %0, 16 \n"
115 " addu %0, $1 \n"
116 " xori %0, 0xffff \n"
117 " .set pop"
118 : "=r" (sum)
119 : "0" (sum));
120 114
121 return (__force __sum16)sum; 115 sum += (sum << 16);
116 csum = (sum < csum);
117 sum >>= 16;
118 sum += csum;
119
120 return (__force __sum16)~sum;
122} 121}
122#define csum_fold csum_fold
123 123
124/* 124/*
125 * This is a version of ip_compute_csum() optimized for IP headers, 125 * This is a version of ip_compute_csum() optimized for IP headers,
@@ -158,6 +158,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
158 158
159 return csum_fold(csum); 159 return csum_fold(csum);
160} 160}
161#define ip_fast_csum ip_fast_csum
161 162
162static inline __wsum csum_tcpudp_nofold(__be32 saddr, 163static inline __wsum csum_tcpudp_nofold(__be32 saddr,
163 __be32 daddr, unsigned short len, unsigned short proto, 164 __be32 daddr, unsigned short len, unsigned short proto,
@@ -200,18 +201,7 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr,
200 201
201 return sum; 202 return sum;
202} 203}
203 204#define csum_tcpudp_nofold csum_tcpudp_nofold
204/*
205 * computes the checksum of the TCP/UDP pseudo-header
206 * returns a 16-bit checksum, already complemented
207 */
208static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
209 unsigned short len,
210 unsigned short proto,
211 __wsum sum)
212{
213 return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
214}
215 205
216/* 206/*
217 * this routine is used for miscellaneous IP-like checksums, mainly 207 * this routine is used for miscellaneous IP-like checksums, mainly
@@ -287,4 +277,7 @@ static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
287 return csum_fold(sum); 277 return csum_fold(sum);
288} 278}
289 279
280#include <asm-generic/checksum.h>
281#endif /* CONFIG_GENERIC_CSUM */
282
290#endif /* _ASM_CHECKSUM_H */ 283#endif /* _ASM_CHECKSUM_H */
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 28b1edf19501..d0a2a68ca600 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -31,24 +31,24 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
31 " sc %2, %1 \n" 31 " sc %2, %1 \n"
32 " beqzl %2, 1b \n" 32 " beqzl %2, 1b \n"
33 " .set mips0 \n" 33 " .set mips0 \n"
34 : "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy) 34 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
35 : GCC_OFF12_ASM() (*m), "Jr" (val) 35 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
36 : "memory"); 36 : "memory");
37 } else if (kernel_uses_llsc) { 37 } else if (kernel_uses_llsc) {
38 unsigned long dummy; 38 unsigned long dummy;
39 39
40 do { 40 do {
41 __asm__ __volatile__( 41 __asm__ __volatile__(
42 " .set arch=r4000 \n" 42 " .set "MIPS_ISA_ARCH_LEVEL" \n"
43 " ll %0, %3 # xchg_u32 \n" 43 " ll %0, %3 # xchg_u32 \n"
44 " .set mips0 \n" 44 " .set mips0 \n"
45 " move %2, %z4 \n" 45 " move %2, %z4 \n"
46 " .set arch=r4000 \n" 46 " .set "MIPS_ISA_ARCH_LEVEL" \n"
47 " sc %2, %1 \n" 47 " sc %2, %1 \n"
48 " .set mips0 \n" 48 " .set mips0 \n"
49 : "=&r" (retval), "=" GCC_OFF12_ASM() (*m), 49 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
50 "=&r" (dummy) 50 "=&r" (dummy)
51 : GCC_OFF12_ASM() (*m), "Jr" (val) 51 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
52 : "memory"); 52 : "memory");
53 } while (unlikely(!dummy)); 53 } while (unlikely(!dummy));
54 } else { 54 } else {
@@ -82,22 +82,22 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
82 " scd %2, %1 \n" 82 " scd %2, %1 \n"
83 " beqzl %2, 1b \n" 83 " beqzl %2, 1b \n"
84 " .set mips0 \n" 84 " .set mips0 \n"
85 : "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy) 85 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)
86 : GCC_OFF12_ASM() (*m), "Jr" (val) 86 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
87 : "memory"); 87 : "memory");
88 } else if (kernel_uses_llsc) { 88 } else if (kernel_uses_llsc) {
89 unsigned long dummy; 89 unsigned long dummy;
90 90
91 do { 91 do {
92 __asm__ __volatile__( 92 __asm__ __volatile__(
93 " .set arch=r4000 \n" 93 " .set "MIPS_ISA_ARCH_LEVEL" \n"
94 " lld %0, %3 # xchg_u64 \n" 94 " lld %0, %3 # xchg_u64 \n"
95 " move %2, %z4 \n" 95 " move %2, %z4 \n"
96 " scd %2, %1 \n" 96 " scd %2, %1 \n"
97 " .set mips0 \n" 97 " .set mips0 \n"
98 : "=&r" (retval), "=" GCC_OFF12_ASM() (*m), 98 : "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),
99 "=&r" (dummy) 99 "=&r" (dummy)
100 : GCC_OFF12_ASM() (*m), "Jr" (val) 100 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val)
101 : "memory"); 101 : "memory");
102 } while (unlikely(!dummy)); 102 } while (unlikely(!dummy));
103 } else { 103 } else {
@@ -158,25 +158,25 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
158 " beqzl $1, 1b \n" \ 158 " beqzl $1, 1b \n" \
159 "2: \n" \ 159 "2: \n" \
160 " .set pop \n" \ 160 " .set pop \n" \
161 : "=&r" (__ret), "=" GCC_OFF12_ASM() (*m) \ 161 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
162 : GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new) \ 162 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
163 : "memory"); \ 163 : "memory"); \
164 } else if (kernel_uses_llsc) { \ 164 } else if (kernel_uses_llsc) { \
165 __asm__ __volatile__( \ 165 __asm__ __volatile__( \
166 " .set push \n" \ 166 " .set push \n" \
167 " .set noat \n" \ 167 " .set noat \n" \
168 " .set arch=r4000 \n" \ 168 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
169 "1: " ld " %0, %2 # __cmpxchg_asm \n" \ 169 "1: " ld " %0, %2 # __cmpxchg_asm \n" \
170 " bne %0, %z3, 2f \n" \ 170 " bne %0, %z3, 2f \n" \
171 " .set mips0 \n" \ 171 " .set mips0 \n" \
172 " move $1, %z4 \n" \ 172 " move $1, %z4 \n" \
173 " .set arch=r4000 \n" \ 173 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
174 " " st " $1, %1 \n" \ 174 " " st " $1, %1 \n" \
175 " beqz $1, 1b \n" \ 175 " beqz $1, 1b \n" \
176 " .set pop \n" \ 176 " .set pop \n" \
177 "2: \n" \ 177 "2: \n" \
178 : "=&r" (__ret), "=" GCC_OFF12_ASM() (*m) \ 178 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
179 : GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new) \ 179 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
180 : "memory"); \ 180 : "memory"); \
181 } else { \ 181 } else { \
182 unsigned long __flags; \ 182 unsigned long __flags; \
diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h
index c73815e0123a..e081a265f422 100644
--- a/arch/mips/include/asm/compiler.h
+++ b/arch/mips/include/asm/compiler.h
@@ -16,12 +16,30 @@
16#define GCC_REG_ACCUM "accum" 16#define GCC_REG_ACCUM "accum"
17#endif 17#endif
18 18
19#ifdef CONFIG_CPU_MIPSR6
20/* All MIPS R6 toolchains support the ZC constrain */
21#define GCC_OFF_SMALL_ASM() "ZC"
22#else
19#ifndef CONFIG_CPU_MICROMIPS 23#ifndef CONFIG_CPU_MICROMIPS
20#define GCC_OFF12_ASM() "R" 24#define GCC_OFF_SMALL_ASM() "R"
21#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9) 25#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
22#define GCC_OFF12_ASM() "ZC" 26#define GCC_OFF_SMALL_ASM() "ZC"
23#else 27#else
24#error "microMIPS compilation unsupported with GCC older than 4.9" 28#error "microMIPS compilation unsupported with GCC older than 4.9"
25#endif 29#endif /* CONFIG_CPU_MICROMIPS */
30#endif /* CONFIG_CPU_MIPSR6 */
31
32#ifdef CONFIG_CPU_MIPSR6
33#define MIPS_ISA_LEVEL "mips64r6"
34#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
35#define MIPS_ISA_LEVEL_RAW mips64r6
36#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
37#else
38/* MIPS64 is a superset of MIPS32 */
39#define MIPS_ISA_LEVEL "mips64r2"
40#define MIPS_ISA_ARCH_LEVEL "arch=r4000"
41#define MIPS_ISA_LEVEL_RAW mips64r2
42#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
43#endif /* CONFIG_CPU_MIPSR6 */
26 44
27#endif /* _ASM_COMPILER_H */ 45#endif /* _ASM_COMPILER_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 2897cfafcaf0..0d8208de9a3f 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -38,6 +38,9 @@
38#ifndef cpu_has_maar 38#ifndef cpu_has_maar
39#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR) 39#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
40#endif 40#endif
41#ifndef cpu_has_rw_llb
42#define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
43#endif
41 44
42/* 45/*
43 * For the moment we don't consider R6000 and R8000 so we can assume that 46 * For the moment we don't consider R6000 and R8000 so we can assume that
@@ -171,6 +174,9 @@
171#endif 174#endif
172#endif 175#endif
173 176
177#ifndef cpu_has_mips_1
178# define cpu_has_mips_1 (!cpu_has_mips_r6)
179#endif
174#ifndef cpu_has_mips_2 180#ifndef cpu_has_mips_2
175# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 181# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
176#endif 182#endif
@@ -189,12 +195,18 @@
189#ifndef cpu_has_mips32r2 195#ifndef cpu_has_mips32r2
190# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 196# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
191#endif 197#endif
198#ifndef cpu_has_mips32r6
199# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
200#endif
192#ifndef cpu_has_mips64r1 201#ifndef cpu_has_mips64r1
193# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 202# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
194#endif 203#endif
195#ifndef cpu_has_mips64r2 204#ifndef cpu_has_mips64r2
196# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 205# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
197#endif 206#endif
207#ifndef cpu_has_mips64r6
208# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
209#endif
198 210
199/* 211/*
200 * Shortcuts ... 212 * Shortcuts ...
@@ -208,17 +220,23 @@
208#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 220#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
209#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 221#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
210 222
211#define cpu_has_mips_4_5_r2 (cpu_has_mips_4_5 | cpu_has_mips_r2) 223#define cpu_has_mips_4_5_r2_r6 (cpu_has_mips_4_5 | cpu_has_mips_r2 | \
224 cpu_has_mips_r6)
212 225
213#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) 226#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
214#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 227#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
215#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 228#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
216#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 229#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
230#define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
217#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 231#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
218 cpu_has_mips64r1 | cpu_has_mips64r2) 232 cpu_has_mips32r6 | cpu_has_mips64r1 | \
233 cpu_has_mips64r2 | cpu_has_mips64r6)
234
235/* MIPSR2 and MIPSR6 have a lot of similarities */
236#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
219 237
220#ifndef cpu_has_mips_r2_exec_hazard 238#ifndef cpu_has_mips_r2_exec_hazard
221#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 239#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6)
222#endif 240#endif
223 241
224/* 242/*
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index a6c9ccb33c5c..c3f4f2d2e108 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -84,6 +84,11 @@ struct cpuinfo_mips {
84 * (shifted by _CACHE_SHIFT) 84 * (shifted by _CACHE_SHIFT)
85 */ 85 */
86 unsigned int writecombine; 86 unsigned int writecombine;
87 /*
88 * Simple counter to prevent enabling HTW in nested
89 * htw_start/htw_stop calls
90 */
91 unsigned int htw_seq;
87} __attribute__((aligned(SMP_CACHE_BYTES))); 92} __attribute__((aligned(SMP_CACHE_BYTES)));
88 93
89extern struct cpuinfo_mips cpu_data[]; 94extern struct cpuinfo_mips cpu_data[];
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index b4e2bd87df50..8245875f8b33 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -54,6 +54,13 @@ static inline int __pure __get_cpu_type(const int cpu_type)
54 case CPU_M5150: 54 case CPU_M5150:
55#endif 55#endif
56 56
57#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
58 defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \
59 defined(CONFIG_SYS_HAS_CPU_MIPS64_R2) || \
60 defined(CONFIG_SYS_HAS_CPU_MIPS64_R6)
61 case CPU_QEMU_GENERIC:
62#endif
63
57#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 64#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
58 case CPU_5KC: 65 case CPU_5KC:
59 case CPU_5KE: 66 case CPU_5KE:
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 33866fce4d63..15687234d70a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -93,6 +93,7 @@
93 * These are the PRID's for when 23:16 == PRID_COMP_MIPS 93 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
94 */ 94 */
95 95
96#define PRID_IMP_QEMU_GENERIC 0x0000
96#define PRID_IMP_4KC 0x8000 97#define PRID_IMP_4KC 0x8000
97#define PRID_IMP_5KC 0x8100 98#define PRID_IMP_5KC 0x8100
98#define PRID_IMP_20KC 0x8200 99#define PRID_IMP_20KC 0x8200
@@ -312,6 +313,8 @@ enum cpu_type_enum {
312 CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, 313 CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
313 CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, 314 CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
314 315
316 CPU_QEMU_GENERIC,
317
315 CPU_LAST 318 CPU_LAST
316}; 319};
317 320
@@ -329,11 +332,14 @@ enum cpu_type_enum {
329#define MIPS_CPU_ISA_M32R2 0x00000020 332#define MIPS_CPU_ISA_M32R2 0x00000020
330#define MIPS_CPU_ISA_M64R1 0x00000040 333#define MIPS_CPU_ISA_M64R1 0x00000040
331#define MIPS_CPU_ISA_M64R2 0x00000080 334#define MIPS_CPU_ISA_M64R2 0x00000080
335#define MIPS_CPU_ISA_M32R6 0x00000100
336#define MIPS_CPU_ISA_M64R6 0x00000200
332 337
333#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ 338#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
334 MIPS_CPU_ISA_M32R2) 339 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
335#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 340#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
336 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 341 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
342 MIPS_CPU_ISA_M64R6)
337 343
338/* 344/*
339 * CPU Option encodings 345 * CPU Option encodings
@@ -370,6 +376,7 @@ enum cpu_type_enum {
370#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ 376#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
371#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */ 377#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
372#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */ 378#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
379#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */
373 380
374/* 381/*
375 * CPU ASE encodings 382 * CPU ASE encodings
diff --git a/arch/mips/include/asm/edac.h b/arch/mips/include/asm/edac.h
index ae6fedcb0060..94105d3f58f4 100644
--- a/arch/mips/include/asm/edac.h
+++ b/arch/mips/include/asm/edac.h
@@ -26,8 +26,8 @@ static inline void atomic_scrub(void *va, u32 size)
26 " sc %0, %1 \n" 26 " sc %0, %1 \n"
27 " beqz %0, 1b \n" 27 " beqz %0, 1b \n"
28 " .set mips0 \n" 28 " .set mips0 \n"
29 : "=&r" (temp), "=" GCC_OFF12_ASM() (*virt_addr) 29 : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*virt_addr)
30 : GCC_OFF12_ASM() (*virt_addr)); 30 : GCC_OFF_SMALL_ASM() (*virt_addr));
31 31
32 virt_addr++; 32 virt_addr++;
33 } 33 }
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index eb4d95de619c..535f196ffe02 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -417,13 +417,15 @@ extern unsigned long arch_randomize_brk(struct mm_struct *mm);
417struct arch_elf_state { 417struct arch_elf_state {
418 int fp_abi; 418 int fp_abi;
419 int interp_fp_abi; 419 int interp_fp_abi;
420 int overall_abi; 420 int overall_fp_mode;
421}; 421};
422 422
423#define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (kernel internal) */
424
423#define INIT_ARCH_ELF_STATE { \ 425#define INIT_ARCH_ELF_STATE { \
424 .fp_abi = -1, \ 426 .fp_abi = MIPS_ABI_FP_UNKNOWN, \
425 .interp_fp_abi = -1, \ 427 .interp_fp_abi = MIPS_ABI_FP_UNKNOWN, \
426 .overall_abi = -1, \ 428 .overall_fp_mode = -1, \
427} 429}
428 430
429extern int arch_elf_pt_proc(void *ehdr, void *phdr, struct file *elf, 431extern int arch_elf_pt_proc(void *ehdr, void *phdr, struct file *elf,
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index affebb78f5d6..dd083e999b08 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -68,7 +68,8 @@ static inline int __enable_fpu(enum fpu_mode mode)
68 goto fr_common; 68 goto fr_common;
69 69
70 case FPU_64BIT: 70 case FPU_64BIT:
71#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT)) 71#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) \
72 || defined(CONFIG_64BIT))
72 /* we only have a 32-bit FPU */ 73 /* we only have a 32-bit FPU */
73 return SIGFPE; 74 return SIGFPE;
74#endif 75#endif
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index ef9987a61d88..1de190bdfb9c 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -45,19 +45,19 @@
45 " "__UA_ADDR "\t2b, 4b \n" \ 45 " "__UA_ADDR "\t2b, 4b \n" \
46 " .previous \n" \ 46 " .previous \n" \
47 : "=r" (ret), "=&r" (oldval), \ 47 : "=r" (ret), "=&r" (oldval), \
48 "=" GCC_OFF12_ASM() (*uaddr) \ 48 "=" GCC_OFF_SMALL_ASM() (*uaddr) \
49 : "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \ 49 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
50 "i" (-EFAULT) \ 50 "i" (-EFAULT) \
51 : "memory"); \ 51 : "memory"); \
52 } else if (cpu_has_llsc) { \ 52 } else if (cpu_has_llsc) { \
53 __asm__ __volatile__( \ 53 __asm__ __volatile__( \
54 " .set push \n" \ 54 " .set push \n" \
55 " .set noat \n" \ 55 " .set noat \n" \
56 " .set arch=r4000 \n" \ 56 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
57 "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \ 57 "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
58 " .set mips0 \n" \ 58 " .set mips0 \n" \
59 " " insn " \n" \ 59 " " insn " \n" \
60 " .set arch=r4000 \n" \ 60 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
61 "2: "user_sc("$1", "%2")" \n" \ 61 "2: "user_sc("$1", "%2")" \n" \
62 " beqz $1, 1b \n" \ 62 " beqz $1, 1b \n" \
63 __WEAK_LLSC_MB \ 63 __WEAK_LLSC_MB \
@@ -74,8 +74,8 @@
74 " "__UA_ADDR "\t2b, 4b \n" \ 74 " "__UA_ADDR "\t2b, 4b \n" \
75 " .previous \n" \ 75 " .previous \n" \
76 : "=r" (ret), "=&r" (oldval), \ 76 : "=r" (ret), "=&r" (oldval), \
77 "=" GCC_OFF12_ASM() (*uaddr) \ 77 "=" GCC_OFF_SMALL_ASM() (*uaddr) \
78 : "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \ 78 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
79 "i" (-EFAULT) \ 79 "i" (-EFAULT) \
80 : "memory"); \ 80 : "memory"); \
81 } else \ 81 } else \
@@ -174,8 +174,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
174 " "__UA_ADDR "\t1b, 4b \n" 174 " "__UA_ADDR "\t1b, 4b \n"
175 " "__UA_ADDR "\t2b, 4b \n" 175 " "__UA_ADDR "\t2b, 4b \n"
176 " .previous \n" 176 " .previous \n"
177 : "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr) 177 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
178 : GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval), 178 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
179 "i" (-EFAULT) 179 "i" (-EFAULT)
180 : "memory"); 180 : "memory");
181 } else if (cpu_has_llsc) { 181 } else if (cpu_has_llsc) {
@@ -183,12 +183,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
183 "# futex_atomic_cmpxchg_inatomic \n" 183 "# futex_atomic_cmpxchg_inatomic \n"
184 " .set push \n" 184 " .set push \n"
185 " .set noat \n" 185 " .set noat \n"
186 " .set arch=r4000 \n" 186 " .set "MIPS_ISA_ARCH_LEVEL" \n"
187 "1: "user_ll("%1", "%3")" \n" 187 "1: "user_ll("%1", "%3")" \n"
188 " bne %1, %z4, 3f \n" 188 " bne %1, %z4, 3f \n"
189 " .set mips0 \n" 189 " .set mips0 \n"
190 " move $1, %z5 \n" 190 " move $1, %z5 \n"
191 " .set arch=r4000 \n" 191 " .set "MIPS_ISA_ARCH_LEVEL" \n"
192 "2: "user_sc("$1", "%2")" \n" 192 "2: "user_sc("$1", "%2")" \n"
193 " beqz $1, 1b \n" 193 " beqz $1, 1b \n"
194 __WEAK_LLSC_MB 194 __WEAK_LLSC_MB
@@ -203,8 +203,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
203 " "__UA_ADDR "\t1b, 4b \n" 203 " "__UA_ADDR "\t1b, 4b \n"
204 " "__UA_ADDR "\t2b, 4b \n" 204 " "__UA_ADDR "\t2b, 4b \n"
205 " .previous \n" 205 " .previous \n"
206 : "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr) 206 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
207 : GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval), 207 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
208 "i" (-EFAULT) 208 "i" (-EFAULT)
209 : "memory"); 209 : "memory");
210 } else 210 } else
diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h
index 4be1a57cdbb0..71a986e9b694 100644
--- a/arch/mips/include/asm/gio_device.h
+++ b/arch/mips/include/asm/gio_device.h
@@ -25,8 +25,6 @@ struct gio_driver {
25 25
26 int (*probe)(struct gio_device *, const struct gio_device_id *); 26 int (*probe)(struct gio_device *, const struct gio_device_id *);
27 void (*remove)(struct gio_device *); 27 void (*remove)(struct gio_device *);
28 int (*suspend)(struct gio_device *, pm_message_t);
29 int (*resume)(struct gio_device *);
30 void (*shutdown)(struct gio_device *); 28 void (*shutdown)(struct gio_device *);
31 29
32 struct device_driver driver; 30 struct device_driver driver;
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index e3ee92d4dbe7..4087b47ad1cb 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -11,6 +11,7 @@
11#define _ASM_HAZARDS_H 11#define _ASM_HAZARDS_H
12 12
13#include <linux/stringify.h> 13#include <linux/stringify.h>
14#include <asm/compiler.h>
14 15
15#define ___ssnop \ 16#define ___ssnop \
16 sll $0, $0, 1 17 sll $0, $0, 1
@@ -21,7 +22,7 @@
21/* 22/*
22 * TLB hazards 23 * TLB hazards
23 */ 24 */
24#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON) 25#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
25 26
26/* 27/*
27 * MIPSR2 defines ehb for hazard avoidance 28 * MIPSR2 defines ehb for hazard avoidance
@@ -58,7 +59,7 @@ do { \
58 unsigned long tmp; \ 59 unsigned long tmp; \
59 \ 60 \
60 __asm__ __volatile__( \ 61 __asm__ __volatile__( \
61 " .set mips64r2 \n" \ 62 " .set "MIPS_ISA_LEVEL" \n" \
62 " dla %0, 1f \n" \ 63 " dla %0, 1f \n" \
63 " jr.hb %0 \n" \ 64 " jr.hb %0 \n" \
64 " .set mips0 \n" \ 65 " .set mips0 \n" \
@@ -132,7 +133,7 @@ do { \
132 133
133#define instruction_hazard() \ 134#define instruction_hazard() \
134do { \ 135do { \
135 if (cpu_has_mips_r2) \ 136 if (cpu_has_mips_r2_r6) \
136 __instruction_hazard(); \ 137 __instruction_hazard(); \
137} while (0) 138} while (0)
138 139
@@ -240,7 +241,7 @@ do { \
240 241
241#define __disable_fpu_hazard 242#define __disable_fpu_hazard
242 243
243#elif defined(CONFIG_CPU_MIPSR2) 244#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
244 245
245#define __enable_fpu_hazard \ 246#define __enable_fpu_hazard \
246 ___ehb 247 ___ehb
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 0fa5fdcd1f01..d60cc68fa31e 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -15,9 +15,10 @@
15 15
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <linux/stringify.h> 17#include <linux/stringify.h>
18#include <asm/compiler.h>
18#include <asm/hazards.h> 19#include <asm/hazards.h>
19 20
20#ifdef CONFIG_CPU_MIPSR2 21#if defined(CONFIG_CPU_MIPSR2) || defined (CONFIG_CPU_MIPSR6)
21 22
22static inline void arch_local_irq_disable(void) 23static inline void arch_local_irq_disable(void)
23{ 24{
@@ -118,7 +119,7 @@ void arch_local_irq_disable(void);
118unsigned long arch_local_irq_save(void); 119unsigned long arch_local_irq_save(void);
119void arch_local_irq_restore(unsigned long flags); 120void arch_local_irq_restore(unsigned long flags);
120void __arch_local_irq_restore(unsigned long flags); 121void __arch_local_irq_restore(unsigned long flags);
121#endif /* CONFIG_CPU_MIPSR2 */ 122#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
122 123
123static inline void arch_local_irq_enable(void) 124static inline void arch_local_irq_enable(void)
124{ 125{
@@ -126,7 +127,7 @@ static inline void arch_local_irq_enable(void)
126 " .set push \n" 127 " .set push \n"
127 " .set reorder \n" 128 " .set reorder \n"
128 " .set noat \n" 129 " .set noat \n"
129#if defined(CONFIG_CPU_MIPSR2) 130#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
130 " ei \n" 131 " ei \n"
131#else 132#else
132 " mfc0 $1,$12 \n" 133 " mfc0 $1,$12 \n"
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index 46dfc3c1fd49..8feaed62a2ab 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -5,6 +5,7 @@
5#include <linux/bitops.h> 5#include <linux/bitops.h>
6#include <linux/atomic.h> 6#include <linux/atomic.h>
7#include <asm/cmpxchg.h> 7#include <asm/cmpxchg.h>
8#include <asm/compiler.h>
8#include <asm/war.h> 9#include <asm/war.h>
9 10
10typedef struct 11typedef struct
@@ -47,7 +48,7 @@ static __inline__ long local_add_return(long i, local_t * l)
47 unsigned long temp; 48 unsigned long temp;
48 49
49 __asm__ __volatile__( 50 __asm__ __volatile__(
50 " .set arch=r4000 \n" 51 " .set "MIPS_ISA_ARCH_LEVEL" \n"
51 "1:" __LL "%1, %2 # local_add_return \n" 52 "1:" __LL "%1, %2 # local_add_return \n"
52 " addu %0, %1, %3 \n" 53 " addu %0, %1, %3 \n"
53 __SC "%0, %2 \n" 54 __SC "%0, %2 \n"
@@ -92,7 +93,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
92 unsigned long temp; 93 unsigned long temp;
93 94
94 __asm__ __volatile__( 95 __asm__ __volatile__(
95 " .set arch=r4000 \n" 96 " .set "MIPS_ISA_ARCH_LEVEL" \n"
96 "1:" __LL "%1, %2 # local_sub_return \n" 97 "1:" __LL "%1, %2 # local_sub_return \n"
97 " subu %0, %1, %3 \n" 98 " subu %0, %1, %3 \n"
98 __SC "%0, %2 \n" 99 __SC "%0, %2 \n"
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 1668ee57acb9..cf92fe733995 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -8,11 +8,10 @@
8#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H 8#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
9#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H 9#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
10 10
11
12#define CP0_CYCLE_COUNTER $9, 6
13#define CP0_CVMCTL_REG $9, 7 11#define CP0_CVMCTL_REG $9, 7
14#define CP0_CVMMEMCTL_REG $11,7 12#define CP0_CVMMEMCTL_REG $11,7
15#define CP0_PRID_REG $15, 0 13#define CP0_PRID_REG $15, 0
14#define CP0_DCACHE_ERR_REG $27, 1
16#define CP0_PRID_OCTEON_PASS1 0x000d0000 15#define CP0_PRID_OCTEON_PASS1 0x000d0000
17#define CP0_PRID_OCTEON_CN30XX 0x000d0200 16#define CP0_PRID_OCTEON_CN30XX 0x000d0200
18 17
@@ -38,36 +37,55 @@
38 # Needed for octeon specific memcpy 37 # Needed for octeon specific memcpy
39 or v0, v0, 0x5001 38 or v0, v0, 0x5001
40 xor v0, v0, 0x1001 39 xor v0, v0, 0x1001
41 # Read the processor ID register
42 mfc0 v1, CP0_PRID_REG
43 # Disable instruction prefetching (Octeon Pass1 errata)
44 or v0, v0, 0x2000
45 # Skip reenable of prefetching for Octeon Pass1
46 beq v1, CP0_PRID_OCTEON_PASS1, skip
47 nop
48 # Reenable instruction prefetching, not on Pass1
49 xor v0, v0, 0x2000
50 # Strip off pass number off of processor id
51 srl v1, 8
52 sll v1, 8
53 # CN30XX needs some extra stuff turned off for better performance
54 bne v1, CP0_PRID_OCTEON_CN30XX, skip
55 nop
56 # CN30XX Use random Icache replacement
57 or v0, v0, 0x400
58 # CN30XX Disable instruction prefetching
59 or v0, v0, 0x2000
60skip:
61 # First clear off CvmCtl[IPPCI] bit and move the performance 40 # First clear off CvmCtl[IPPCI] bit and move the performance
62 # counters interrupt to IRQ 6 41 # counters interrupt to IRQ 6
63 li v1, ~(7 << 7) 42 dli v1, ~(7 << 7)
64 and v0, v0, v1 43 and v0, v0, v1
65 ori v0, v0, (6 << 7) 44 ori v0, v0, (6 << 7)
45
46 mfc0 v1, CP0_PRID_REG
47 and t1, v1, 0xfff8
48 xor t1, t1, 0x9000 # 63-P1
49 beqz t1, 4f
50 and t1, v1, 0xfff8
51 xor t1, t1, 0x9008 # 63-P2
52 beqz t1, 4f
53 and t1, v1, 0xfff8
54 xor t1, t1, 0x9100 # 68-P1
55 beqz t1, 4f
56 and t1, v1, 0xff00
57 xor t1, t1, 0x9200 # 66-PX
58 bnez t1, 5f # Skip WAR for others.
59 and t1, v1, 0x00ff
60 slti t1, t1, 2 # 66-P1.2 and later good.
61 beqz t1, 5f
62
634: # core-16057 work around
64 or v0, v0, 0x2000 # Set IPREF bit.
65
665: # No core-16057 work around
66 # Write the cavium control register 67 # Write the cavium control register
67 dmtc0 v0, CP0_CVMCTL_REG 68 dmtc0 v0, CP0_CVMCTL_REG
68 sync 69 sync
69 # Flush dcache after config change 70 # Flush dcache after config change
70 cache 9, 0($0) 71 cache 9, 0($0)
72 # Zero all of CVMSEG to make sure parity is correct
73 dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
74 dsll v0, 7
75 beqz v0, 2f
761: dsubu v0, 8
77 sd $0, -32768(v0)
78 bnez v0, 1b
792:
80 mfc0 v0, CP0_PRID_REG
81 bbit0 v0, 15, 1f
82 # OCTEON II or better have bit 15 set. Clear the error bits.
83 and t1, v0, 0xff00
84 dli v0, 0x9500
85 bge t1, v0, 1f # OCTEON III has no DCACHE_ERR_REG COP0
86 dli v0, 0x27
87 dmtc0 v0, CP0_DCACHE_ERR_REG
881:
71 # Get my core id 89 # Get my core id
72 rdhwr v0, $0 90 rdhwr v0, $0
73 # Jump the master to kernel_entry 91 # Jump the master to kernel_entry
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index eb72b35cf04b..35c80be92207 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -22,4 +22,7 @@
22#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
24 24
25#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
26 OCTEON_IS_MODEL(OCTEON_CN6XXX)
27
25#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */ 28#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
index 986982db7c38..79cff26d8b36 100644
--- a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -27,8 +27,6 @@ struct jz_nand_platform_data {
27 27
28 struct nand_ecclayout *ecc_layout; 28 struct nand_ecclayout *ecc_layout;
29 29
30 unsigned int busy_gpio;
31
32 unsigned char banks[JZ_NAND_NUM_BANKS]; 30 unsigned char banks[JZ_NAND_NUM_BANKS];
33 31
34 void (*ident_callback)(struct platform_device *, struct nand_chip *, 32 void (*ident_callback)(struct platform_device *, struct nand_chip *,
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
index 2e54b4bff5cf..90dbe43c8d27 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
@@ -85,8 +85,8 @@ static inline void set_value_reg32(volatile u32 *const addr,
85 " "__beqz"%0, 1b \n" 85 " "__beqz"%0, 1b \n"
86 " nop \n" 86 " nop \n"
87 " .set pop \n" 87 " .set pop \n"
88 : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr) 88 : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
89 : "ir" (~mask), "ir" (value), GCC_OFF12_ASM() (*addr)); 89 : "ir" (~mask), "ir" (value), GCC_OFF_SMALL_ASM() (*addr));
90} 90}
91 91
92/* 92/*
@@ -106,8 +106,8 @@ static inline void set_reg32(volatile u32 *const addr,
106 " "__beqz"%0, 1b \n" 106 " "__beqz"%0, 1b \n"
107 " nop \n" 107 " nop \n"
108 " .set pop \n" 108 " .set pop \n"
109 : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr) 109 : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
110 : "ir" (mask), GCC_OFF12_ASM() (*addr)); 110 : "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
111} 111}
112 112
113/* 113/*
@@ -127,8 +127,8 @@ static inline void clear_reg32(volatile u32 *const addr,
127 " "__beqz"%0, 1b \n" 127 " "__beqz"%0, 1b \n"
128 " nop \n" 128 " nop \n"
129 " .set pop \n" 129 " .set pop \n"
130 : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr) 130 : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
131 : "ir" (~mask), GCC_OFF12_ASM() (*addr)); 131 : "ir" (~mask), GCC_OFF_SMALL_ASM() (*addr));
132} 132}
133 133
134/* 134/*
@@ -148,8 +148,8 @@ static inline void toggle_reg32(volatile u32 *const addr,
148 " "__beqz"%0, 1b \n" 148 " "__beqz"%0, 1b \n"
149 " nop \n" 149 " nop \n"
150 " .set pop \n" 150 " .set pop \n"
151 : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr) 151 : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*addr)
152 : "ir" (mask), GCC_OFF12_ASM() (*addr)); 152 : "ir" (mask), GCC_OFF_SMALL_ASM() (*addr));
153} 153}
154 154
155/* 155/*
@@ -220,8 +220,8 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
220 " .set arch=r4000 \n" \ 220 " .set arch=r4000 \n" \
221 "1: ll %0, %1 #custom_read_reg32 \n" \ 221 "1: ll %0, %1 #custom_read_reg32 \n" \
222 " .set pop \n" \ 222 " .set pop \n" \
223 : "=r" (tmp), "=" GCC_OFF12_ASM() (*address) \ 223 : "=r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
224 : GCC_OFF12_ASM() (*address)) 224 : GCC_OFF_SMALL_ASM() (*address))
225 225
226#define custom_write_reg32(address, tmp) \ 226#define custom_write_reg32(address, tmp) \
227 __asm__ __volatile__( \ 227 __asm__ __volatile__( \
@@ -231,7 +231,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
231 " "__beqz"%0, 1b \n" \ 231 " "__beqz"%0, 1b \n" \
232 " nop \n" \ 232 " nop \n" \
233 " .set pop \n" \ 233 " .set pop \n" \
234 : "=&r" (tmp), "=" GCC_OFF12_ASM() (*address) \ 234 : "=&r" (tmp), "=" GCC_OFF_SMALL_ASM() (*address) \
235 : "0" (tmp), GCC_OFF12_ASM() (*address)) 235 : "0" (tmp), GCC_OFF_SMALL_ASM() (*address))
236 236
237#endif /* __ASM_REGOPS_H__ */ 237#endif /* __ASM_REGOPS_H__ */
diff --git a/arch/mips/include/asm/mips-r2-to-r6-emul.h b/arch/mips/include/asm/mips-r2-to-r6-emul.h
new file mode 100644
index 000000000000..60570f2c3ba2
--- /dev/null
+++ b/arch/mips/include/asm/mips-r2-to-r6-emul.h
@@ -0,0 +1,96 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2014 Imagination Technologies Ltd.
7 * Author: Markos Chandras <markos.chandras@imgtec.com>
8 */
9
10#ifndef __ASM_MIPS_R2_TO_R6_EMUL_H
11#define __ASM_MIPS_R2_TO_R6_EMUL_H
12
13struct mips_r2_emulator_stats {
14 u64 movs;
15 u64 hilo;
16 u64 muls;
17 u64 divs;
18 u64 dsps;
19 u64 bops;
20 u64 traps;
21 u64 fpus;
22 u64 loads;
23 u64 stores;
24 u64 llsc;
25 u64 dsemul;
26};
27
28struct mips_r2br_emulator_stats {
29 u64 jrs;
30 u64 bltzl;
31 u64 bgezl;
32 u64 bltzll;
33 u64 bgezll;
34 u64 bltzall;
35 u64 bgezall;
36 u64 bltzal;
37 u64 bgezal;
38 u64 beql;
39 u64 bnel;
40 u64 blezl;
41 u64 bgtzl;
42};
43
44#ifdef CONFIG_DEBUG_FS
45
46#define MIPS_R2_STATS(M) \
47do { \
48 u32 nir; \
49 int err; \
50 \
51 preempt_disable(); \
52 __this_cpu_inc(mipsr2emustats.M); \
53 err = __get_user(nir, (u32 __user *)regs->cp0_epc); \
54 if (!err) { \
55 if (nir == BREAK_MATH) \
56 __this_cpu_inc(mipsr2bdemustats.M); \
57 } \
58 preempt_enable(); \
59} while (0)
60
61#define MIPS_R2BR_STATS(M) \
62do { \
63 preempt_disable(); \
64 __this_cpu_inc(mipsr2bremustats.M); \
65 preempt_enable(); \
66} while (0)
67
68#else
69
70#define MIPS_R2_STATS(M) do { } while (0)
71#define MIPS_R2BR_STATS(M) do { } while (0)
72
73#endif /* CONFIG_DEBUG_FS */
74
75struct r2_decoder_table {
76 u32 mask;
77 u32 code;
78 int (*func)(struct pt_regs *regs, u32 inst);
79};
80
81
82extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
83 const char *str);
84
85#ifndef CONFIG_MIPSR2_TO_R6_EMULATOR
86static int mipsr2_emulation;
87static __maybe_unused int mipsr2_decoder(struct pt_regs *regs, u32 inst) { return 0; };
88#else
89/* MIPS R2 Emulator ON/OFF */
90extern int mipsr2_emulation;
91extern int mipsr2_decoder(struct pt_regs *regs, u32 inst);
92#endif /* CONFIG_MIPSR2_TO_R6_EMULATOR */
93
94#define NO_R6EMU (cpu_has_mips_r6 && !mipsr2_emulation)
95
96#endif /* __ASM_MIPS_R2_TO_R6_EMUL_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 5b720d8c2745..fef004434096 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,7 @@
653#define MIPS_CONF5_NF (_ULCAST_(1) << 0) 653#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
654#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 654#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
655#define MIPS_CONF5_MRP (_ULCAST_(1) << 3) 655#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
656#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
656#define MIPS_CONF5_MVH (_ULCAST_(1) << 5) 657#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
657#define MIPS_CONF5_FRE (_ULCAST_(1) << 8) 658#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
658#define MIPS_CONF5_UFE (_ULCAST_(1) << 9) 659#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
@@ -1127,6 +1128,8 @@ do { \
1127#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1128#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1128#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1129#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1129 1130
1131#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1132#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1130#define read_c0_maar() __read_ulong_c0_register($17, 1) 1133#define read_c0_maar() __read_ulong_c0_register($17, 1)
1131#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) 1134#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1132#define read_c0_maari() __read_32bit_c0_register($17, 2) 1135#define read_c0_maari() __read_32bit_c0_register($17, 2)
@@ -1909,6 +1912,7 @@ __BUILD_SET_C0(config5)
1909__BUILD_SET_C0(intcontrol) 1912__BUILD_SET_C0(intcontrol)
1910__BUILD_SET_C0(intctl) 1913__BUILD_SET_C0(intctl)
1911__BUILD_SET_C0(srsmap) 1914__BUILD_SET_C0(srsmap)
1915__BUILD_SET_C0(pagegrain)
1912__BUILD_SET_C0(brcm_config_0) 1916__BUILD_SET_C0(brcm_config_0)
1913__BUILD_SET_C0(brcm_bus_pll) 1917__BUILD_SET_C0(brcm_bus_pll)
1914__BUILD_SET_C0(brcm_reset) 1918__BUILD_SET_C0(brcm_reset)
diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h
index c436138945a8..1afa1f986df8 100644
--- a/arch/mips/include/asm/mmu.h
+++ b/arch/mips/include/asm/mmu.h
@@ -1,9 +1,12 @@
1#ifndef __ASM_MMU_H 1#ifndef __ASM_MMU_H
2#define __ASM_MMU_H 2#define __ASM_MMU_H
3 3
4#include <linux/atomic.h>
5
4typedef struct { 6typedef struct {
5 unsigned long asid[NR_CPUS]; 7 unsigned long asid[NR_CPUS];
6 void *vdso; 8 void *vdso;
9 atomic_t fp_mode_switching;
7} mm_context_t; 10} mm_context_t;
8 11
9#endif /* __ASM_MMU_H */ 12#endif /* __ASM_MMU_H */
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 2f82568a3ee4..45914b59824c 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -25,7 +25,6 @@ do { \
25 if (cpu_has_htw) { \ 25 if (cpu_has_htw) { \
26 write_c0_pwbase(pgd); \ 26 write_c0_pwbase(pgd); \
27 back_to_back_c0_hazard(); \ 27 back_to_back_c0_hazard(); \
28 htw_reset(); \
29 } \ 28 } \
30} while (0) 29} while (0)
31 30
@@ -132,6 +131,8 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
132 for_each_possible_cpu(i) 131 for_each_possible_cpu(i)
133 cpu_context(i, mm) = 0; 132 cpu_context(i, mm) = 0;
134 133
134 atomic_set(&mm->context.fp_mode_switching, 0);
135
135 return 0; 136 return 0;
136} 137}
137 138
@@ -142,6 +143,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
142 unsigned long flags; 143 unsigned long flags;
143 local_irq_save(flags); 144 local_irq_save(flags);
144 145
146 htw_stop();
145 /* Check if our ASID is of an older version and thus invalid */ 147 /* Check if our ASID is of an older version and thus invalid */
146 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 148 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
147 get_new_mmu_context(next, cpu); 149 get_new_mmu_context(next, cpu);
@@ -154,6 +156,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
154 */ 156 */
155 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 157 cpumask_clear_cpu(cpu, mm_cpumask(prev));
156 cpumask_set_cpu(cpu, mm_cpumask(next)); 158 cpumask_set_cpu(cpu, mm_cpumask(next));
159 htw_start();
157 160
158 local_irq_restore(flags); 161 local_irq_restore(flags);
159} 162}
@@ -180,6 +183,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
180 183
181 local_irq_save(flags); 184 local_irq_save(flags);
182 185
186 htw_stop();
183 /* Unconditionally get a new ASID. */ 187 /* Unconditionally get a new ASID. */
184 get_new_mmu_context(next, cpu); 188 get_new_mmu_context(next, cpu);
185 189
@@ -189,6 +193,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
189 /* mark mmu ownership change */ 193 /* mark mmu ownership change */
190 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 194 cpumask_clear_cpu(cpu, mm_cpumask(prev));
191 cpumask_set_cpu(cpu, mm_cpumask(next)); 195 cpumask_set_cpu(cpu, mm_cpumask(next));
196 htw_start();
192 197
193 local_irq_restore(flags); 198 local_irq_restore(flags);
194} 199}
@@ -203,6 +208,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
203 unsigned long flags; 208 unsigned long flags;
204 209
205 local_irq_save(flags); 210 local_irq_save(flags);
211 htw_stop();
206 212
207 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 213 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
208 get_new_mmu_context(mm, cpu); 214 get_new_mmu_context(mm, cpu);
@@ -211,6 +217,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
211 /* will get a new context next time */ 217 /* will get a new context next time */
212 cpu_context(cpu, mm) = 0; 218 cpu_context(cpu, mm) = 0;
213 } 219 }
220 htw_start();
214 local_irq_restore(flags); 221 local_irq_restore(flags);
215} 222}
216 223
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 800fe578dc99..0aaf9a01ea50 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -88,10 +88,14 @@ search_module_dbetables(unsigned long addr)
88#define MODULE_PROC_FAMILY "MIPS32_R1 " 88#define MODULE_PROC_FAMILY "MIPS32_R1 "
89#elif defined CONFIG_CPU_MIPS32_R2 89#elif defined CONFIG_CPU_MIPS32_R2
90#define MODULE_PROC_FAMILY "MIPS32_R2 " 90#define MODULE_PROC_FAMILY "MIPS32_R2 "
91#elif defined CONFIG_CPU_MIPS32_R6
92#define MODULE_PROC_FAMILY "MIPS32_R6 "
91#elif defined CONFIG_CPU_MIPS64_R1 93#elif defined CONFIG_CPU_MIPS64_R1
92#define MODULE_PROC_FAMILY "MIPS64_R1 " 94#define MODULE_PROC_FAMILY "MIPS64_R1 "
93#elif defined CONFIG_CPU_MIPS64_R2 95#elif defined CONFIG_CPU_MIPS64_R2
94#define MODULE_PROC_FAMILY "MIPS64_R2 " 96#define MODULE_PROC_FAMILY "MIPS64_R2 "
97#elif defined CONFIG_CPU_MIPS64_R6
98#define MODULE_PROC_FAMILY "MIPS64_R6 "
95#elif defined CONFIG_CPU_R3000 99#elif defined CONFIG_CPU_R3000
96#define MODULE_PROC_FAMILY "R3000 " 100#define MODULE_PROC_FAMILY "R3000 "
97#elif defined CONFIG_CPU_TX39XX 101#elif defined CONFIG_CPU_TX39XX
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
index 75739c83f07e..8d05d9069823 100644
--- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -275,7 +275,7 @@ static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
275 " lbu %[ticket], %[now_serving]\n" 275 " lbu %[ticket], %[now_serving]\n"
276 "4:\n" 276 "4:\n"
277 ".set pop\n" : 277 ".set pop\n" :
278 [ticket_ptr] "=" GCC_OFF12_ASM()(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), 278 [ticket_ptr] "=" GCC_OFF_SMALL_ASM()(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
279 [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp), 279 [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
280 [my_ticket] "=r"(my_ticket) 280 [my_ticket] "=r"(my_ticket)
281 ); 281 );
diff --git a/arch/mips/include/asm/octeon/cvmx-rst-defs.h b/arch/mips/include/asm/octeon/cvmx-rst-defs.h
new file mode 100644
index 000000000000..0c9c3e74d4ae
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-rst-defs.h
@@ -0,0 +1,306 @@
1/***********************license start***************
2 * Author: Cavium Inc.
3 *
4 * Contact: support@cavium.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2014 Cavium Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Inc. for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_RST_DEFS_H__
29#define __CVMX_RST_DEFS_H__
30
31#define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
32#define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
33#define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
34#define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
35#define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
36#define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
37#define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
38#define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
39#define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
40#define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
41#define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
42#define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
43
44union cvmx_rst_boot {
45 uint64_t u64;
46 struct cvmx_rst_boot_s {
47#ifdef __BIG_ENDIAN_BITFIELD
48 uint64_t chipkill:1;
49 uint64_t jtcsrdis:1;
50 uint64_t ejtagdis:1;
51 uint64_t romen:1;
52 uint64_t ckill_ppdis:1;
53 uint64_t jt_tstmode:1;
54 uint64_t vrm_err:1;
55 uint64_t reserved_37_56:20;
56 uint64_t c_mul:7;
57 uint64_t pnr_mul:6;
58 uint64_t reserved_21_23:3;
59 uint64_t lboot_oci:3;
60 uint64_t lboot_ext:6;
61 uint64_t lboot:10;
62 uint64_t rboot:1;
63 uint64_t rboot_pin:1;
64#else
65 uint64_t rboot_pin:1;
66 uint64_t rboot:1;
67 uint64_t lboot:10;
68 uint64_t lboot_ext:6;
69 uint64_t lboot_oci:3;
70 uint64_t reserved_21_23:3;
71 uint64_t pnr_mul:6;
72 uint64_t c_mul:7;
73 uint64_t reserved_37_56:20;
74 uint64_t vrm_err:1;
75 uint64_t jt_tstmode:1;
76 uint64_t ckill_ppdis:1;
77 uint64_t romen:1;
78 uint64_t ejtagdis:1;
79 uint64_t jtcsrdis:1;
80 uint64_t chipkill:1;
81#endif
82 } s;
83 struct cvmx_rst_boot_s cn70xx;
84 struct cvmx_rst_boot_s cn70xxp1;
85 struct cvmx_rst_boot_s cn78xx;
86};
87
88union cvmx_rst_cfg {
89 uint64_t u64;
90 struct cvmx_rst_cfg_s {
91#ifdef __BIG_ENDIAN_BITFIELD
92 uint64_t bist_delay:58;
93 uint64_t reserved_3_5:3;
94 uint64_t cntl_clr_bist:1;
95 uint64_t warm_clr_bist:1;
96 uint64_t soft_clr_bist:1;
97#else
98 uint64_t soft_clr_bist:1;
99 uint64_t warm_clr_bist:1;
100 uint64_t cntl_clr_bist:1;
101 uint64_t reserved_3_5:3;
102 uint64_t bist_delay:58;
103#endif
104 } s;
105 struct cvmx_rst_cfg_s cn70xx;
106 struct cvmx_rst_cfg_s cn70xxp1;
107 struct cvmx_rst_cfg_s cn78xx;
108};
109
110union cvmx_rst_ckill {
111 uint64_t u64;
112 struct cvmx_rst_ckill_s {
113#ifdef __BIG_ENDIAN_BITFIELD
114 uint64_t reserved_47_63:17;
115 uint64_t timer:47;
116#else
117 uint64_t timer:47;
118 uint64_t reserved_47_63:17;
119#endif
120 } s;
121 struct cvmx_rst_ckill_s cn70xx;
122 struct cvmx_rst_ckill_s cn70xxp1;
123 struct cvmx_rst_ckill_s cn78xx;
124};
125
126union cvmx_rst_ctlx {
127 uint64_t u64;
128 struct cvmx_rst_ctlx_s {
129#ifdef __BIG_ENDIAN_BITFIELD
130 uint64_t reserved_10_63:54;
131 uint64_t prst_link:1;
132 uint64_t rst_done:1;
133 uint64_t rst_link:1;
134 uint64_t host_mode:1;
135 uint64_t reserved_4_5:2;
136 uint64_t rst_drv:1;
137 uint64_t rst_rcv:1;
138 uint64_t rst_chip:1;
139 uint64_t rst_val:1;
140#else
141 uint64_t rst_val:1;
142 uint64_t rst_chip:1;
143 uint64_t rst_rcv:1;
144 uint64_t rst_drv:1;
145 uint64_t reserved_4_5:2;
146 uint64_t host_mode:1;
147 uint64_t rst_link:1;
148 uint64_t rst_done:1;
149 uint64_t prst_link:1;
150 uint64_t reserved_10_63:54;
151#endif
152 } s;
153 struct cvmx_rst_ctlx_s cn70xx;
154 struct cvmx_rst_ctlx_s cn70xxp1;
155 struct cvmx_rst_ctlx_s cn78xx;
156};
157
158union cvmx_rst_delay {
159 uint64_t u64;
160 struct cvmx_rst_delay_s {
161#ifdef __BIG_ENDIAN_BITFIELD
162 uint64_t reserved_32_63:32;
163 uint64_t warm_rst_dly:16;
164 uint64_t soft_rst_dly:16;
165#else
166 uint64_t soft_rst_dly:16;
167 uint64_t warm_rst_dly:16;
168 uint64_t reserved_32_63:32;
169#endif
170 } s;
171 struct cvmx_rst_delay_s cn70xx;
172 struct cvmx_rst_delay_s cn70xxp1;
173 struct cvmx_rst_delay_s cn78xx;
174};
175
176union cvmx_rst_eco {
177 uint64_t u64;
178 struct cvmx_rst_eco_s {
179#ifdef __BIG_ENDIAN_BITFIELD
180 uint64_t reserved_32_63:32;
181 uint64_t eco_rw:32;
182#else
183 uint64_t eco_rw:32;
184 uint64_t reserved_32_63:32;
185#endif
186 } s;
187 struct cvmx_rst_eco_s cn78xx;
188};
189
190union cvmx_rst_int {
191 uint64_t u64;
192 struct cvmx_rst_int_s {
193#ifdef __BIG_ENDIAN_BITFIELD
194 uint64_t reserved_12_63:52;
195 uint64_t perst:4;
196 uint64_t reserved_4_7:4;
197 uint64_t rst_link:4;
198#else
199 uint64_t rst_link:4;
200 uint64_t reserved_4_7:4;
201 uint64_t perst:4;
202 uint64_t reserved_12_63:52;
203#endif
204 } s;
205 struct cvmx_rst_int_cn70xx {
206#ifdef __BIG_ENDIAN_BITFIELD
207 uint64_t reserved_11_63:53;
208 uint64_t perst:3;
209 uint64_t reserved_3_7:5;
210 uint64_t rst_link:3;
211#else
212 uint64_t rst_link:3;
213 uint64_t reserved_3_7:5;
214 uint64_t perst:3;
215 uint64_t reserved_11_63:53;
216#endif
217 } cn70xx;
218 struct cvmx_rst_int_cn70xx cn70xxp1;
219 struct cvmx_rst_int_s cn78xx;
220};
221
222union cvmx_rst_ocx {
223 uint64_t u64;
224 struct cvmx_rst_ocx_s {
225#ifdef __BIG_ENDIAN_BITFIELD
226 uint64_t reserved_3_63:61;
227 uint64_t rst_link:3;
228#else
229 uint64_t rst_link:3;
230 uint64_t reserved_3_63:61;
231#endif
232 } s;
233 struct cvmx_rst_ocx_s cn78xx;
234};
235
236union cvmx_rst_power_dbg {
237 uint64_t u64;
238 struct cvmx_rst_power_dbg_s {
239#ifdef __BIG_ENDIAN_BITFIELD
240 uint64_t reserved_3_63:61;
241 uint64_t str:3;
242#else
243 uint64_t str:3;
244 uint64_t reserved_3_63:61;
245#endif
246 } s;
247 struct cvmx_rst_power_dbg_s cn78xx;
248};
249
250union cvmx_rst_pp_power {
251 uint64_t u64;
252 struct cvmx_rst_pp_power_s {
253#ifdef __BIG_ENDIAN_BITFIELD
254 uint64_t reserved_48_63:16;
255 uint64_t gate:48;
256#else
257 uint64_t gate:48;
258 uint64_t reserved_48_63:16;
259#endif
260 } s;
261 struct cvmx_rst_pp_power_cn70xx {
262#ifdef __BIG_ENDIAN_BITFIELD
263 uint64_t reserved_4_63:60;
264 uint64_t gate:4;
265#else
266 uint64_t gate:4;
267 uint64_t reserved_4_63:60;
268#endif
269 } cn70xx;
270 struct cvmx_rst_pp_power_cn70xx cn70xxp1;
271 struct cvmx_rst_pp_power_s cn78xx;
272};
273
274union cvmx_rst_soft_prstx {
275 uint64_t u64;
276 struct cvmx_rst_soft_prstx_s {
277#ifdef __BIG_ENDIAN_BITFIELD
278 uint64_t reserved_1_63:63;
279 uint64_t soft_prst:1;
280#else
281 uint64_t soft_prst:1;
282 uint64_t reserved_1_63:63;
283#endif
284 } s;
285 struct cvmx_rst_soft_prstx_s cn70xx;
286 struct cvmx_rst_soft_prstx_s cn70xxp1;
287 struct cvmx_rst_soft_prstx_s cn78xx;
288};
289
290union cvmx_rst_soft_rst {
291 uint64_t u64;
292 struct cvmx_rst_soft_rst_s {
293#ifdef __BIG_ENDIAN_BITFIELD
294 uint64_t reserved_1_63:63;
295 uint64_t soft_rst:1;
296#else
297 uint64_t soft_rst:1;
298 uint64_t reserved_1_63:63;
299#endif
300 } s;
301 struct cvmx_rst_soft_rst_s cn70xx;
302 struct cvmx_rst_soft_rst_s cn70xxp1;
303 struct cvmx_rst_soft_rst_s cn78xx;
304};
305
306#endif
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index e8a1c2fd52cd..92b377e36dac 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -45,6 +45,7 @@
45 */ 45 */
46 46
47#define OCTEON_FAMILY_MASK 0x00ffff00 47#define OCTEON_FAMILY_MASK 0x00ffff00
48#define OCTEON_PRID_MASK 0x00ffffff
48 49
49/* Flag bits in top byte */ 50/* Flag bits in top byte */
50/* Ignores revision in model checks */ 51/* Ignores revision in model checks */
@@ -63,11 +64,52 @@
63#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 64#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000
64/* Match all cnf7XXX Octeon models. */ 65/* Match all cnf7XXX Octeon models. */
65#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000 66#define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000
67/* Match all cn7XXX Octeon models. */
68#define OM_MATCH_7XXX_FAMILY_MODELS 0x10000000
69#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \
70 OM_MATCH_6XXX_FAMILY_MODELS | \
71 OM_MATCH_F7XXX_FAMILY_MODELS | \
72 OM_MATCH_7XXX_FAMILY_MODELS)
73/*
74 * CN7XXX models with new revision encoding
75 */
76
77#define OCTEON_CN73XX_PASS1_0 0x000d9700
78#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION)
79#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \
80 OM_IGNORE_MINOR_REVISION)
81
82#define OCTEON_CN70XX_PASS1_0 0x000d9600
83#define OCTEON_CN70XX_PASS1_1 0x000d9601
84#define OCTEON_CN70XX_PASS1_2 0x000d9602
85
86#define OCTEON_CN70XX_PASS2_0 0x000d9608
87
88#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION)
89#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \
90 OM_IGNORE_MINOR_REVISION)
91#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \
92 OM_IGNORE_MINOR_REVISION)
93
94#define OCTEON_CN71XX OCTEON_CN70XX
95
96#define OCTEON_CN78XX_PASS1_0 0x000d9500
97#define OCTEON_CN78XX_PASS1_1 0x000d9501
98#define OCTEON_CN78XX_PASS2_0 0x000d9508
99
100#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION)
101#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \
102 OM_IGNORE_MINOR_REVISION)
103#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \
104 OM_IGNORE_MINOR_REVISION)
105
106#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL)
66 107
67/* 108/*
68 * CNF7XXX models with new revision encoding 109 * CNF7XXX models with new revision encoding
69 */ 110 */
70#define OCTEON_CNF71XX_PASS1_0 0x000d9400 111#define OCTEON_CNF71XX_PASS1_0 0x000d9400
112#define OCTEON_CNF71XX_PASS1_1 0x000d9401
71 113
72#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION) 114#define OCTEON_CNF71XX (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION)
73#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) 115#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
@@ -79,6 +121,8 @@
79#define OCTEON_CN68XX_PASS1_1 0x000d9101 121#define OCTEON_CN68XX_PASS1_1 0x000d9101
80#define OCTEON_CN68XX_PASS1_2 0x000d9102 122#define OCTEON_CN68XX_PASS1_2 0x000d9102
81#define OCTEON_CN68XX_PASS2_0 0x000d9108 123#define OCTEON_CN68XX_PASS2_0 0x000d9108
124#define OCTEON_CN68XX_PASS2_1 0x000d9109
125#define OCTEON_CN68XX_PASS2_2 0x000d910a
82 126
83#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION) 127#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
84#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) 128#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
@@ -104,11 +148,18 @@
104#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) 148#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
105#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) 149#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
106 150
151/* CN62XX is same as CN63XX with 1 MB cache */
152#define OCTEON_CN62XX OCTEON_CN63XX
153
107#define OCTEON_CN61XX_PASS1_0 0x000d9300 154#define OCTEON_CN61XX_PASS1_0 0x000d9300
155#define OCTEON_CN61XX_PASS1_1 0x000d9301
108 156
109#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION) 157#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
110#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) 158#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
111 159
160/* CN60XX is same as CN61XX with 512 KB cache */
161#define OCTEON_CN60XX OCTEON_CN61XX
162
112/* 163/*
113 * CN5XXX models with new revision encoding 164 * CN5XXX models with new revision encoding
114 */ 165 */
@@ -120,7 +171,7 @@
120#define OCTEON_CN58XX_PASS2_2 0x000d030a 171#define OCTEON_CN58XX_PASS2_2 0x000d030a
121#define OCTEON_CN58XX_PASS2_3 0x000d030b 172#define OCTEON_CN58XX_PASS2_3 0x000d030b
122 173
123#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) 174#define OCTEON_CN58XX (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_REVISION)
124#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) 175#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
125#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) 176#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
126#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X 177#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
@@ -217,12 +268,10 @@
217#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) 268#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
218#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) 269#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
219#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) 270#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
220 271#define OCTEON_CNF7XXX (OCTEON_CNF71XX_PASS1_0 | \
221/* These are used to cover entire families of OCTEON processors */ 272 OM_MATCH_F7XXX_FAMILY_MODELS)
222#define OCTEON_FAM_1 (OCTEON_CN3XXX) 273#define OCTEON_CN7XXX (OCTEON_CN78XX_PASS1_0 | \
223#define OCTEON_FAM_PLUS (OCTEON_CN5XXX) 274 OM_MATCH_7XXX_FAMILY_MODELS)
224#define OCTEON_FAM_1_PLUS (OCTEON_FAM_PLUS | OM_MATCH_PREVIOUS_MODELS)
225#define OCTEON_FAM_2 (OCTEON_CN6XXX)
226 275
227/* The revision byte (low byte) has two different encodings. 276/* The revision byte (low byte) has two different encodings.
228 * CN3XXX: 277 * CN3XXX:
@@ -232,7 +281,7 @@
232 * <4>: alternate package 281 * <4>: alternate package
233 * <3:0>: revision 282 * <3:0>: revision
234 * 283 *
235 * CN5XXX: 284 * CN5XXX and older models:
236 * 285 *
237 * bits 286 * bits
238 * <7>: reserved (0) 287 * <7>: reserved (0)
@@ -251,17 +300,21 @@
251/* CN5XXX and later use different layout of bits in the revision ID field */ 300/* CN5XXX and later use different layout of bits in the revision ID field */
252#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK 301#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
253#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f 302#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
254#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 303#define OCTEON_58XX_MODEL_MASK 0x00ffff40
255#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK) 304#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
256#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8) 305#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00ffff38)
257#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 306#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0
258 307
259/* forward declarations */
260static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); 308static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
261static inline uint64_t cvmx_read_csr(uint64_t csr_addr); 309static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
262 310
263#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z))) 311#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
264 312
313/*
314 * __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)
315 * returns true if chip_model is identical or belong to the OCTEON
316 * model group specified in arg_model.
317 */
265/* NOTE: This for internal use only! */ 318/* NOTE: This for internal use only! */
266#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \ 319#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \
267((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \ 320((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \
@@ -286,11 +339,18 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
286 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \ 339 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
287 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \ 340 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
288 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \ 341 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
289 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \ 342 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
290 ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \ 343 ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
291 && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \ 344 && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN58XX_PASS1_0) \
345 && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN63XX_PASS1_0)) || \
292 ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \ 346 ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
293 && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \ 347 && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN63XX_PASS1_0) \
348 && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CNF71XX_PASS1_0)) || \
349 ((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \
350 && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CNF71XX_PASS1_0) \
351 && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN78XX_PASS1_0)) || \
352 ((((arg_model) & (OM_MATCH_7XXX_FAMILY_MODELS)) == OM_MATCH_7XXX_FAMILY_MODELS) \
353 && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN78XX_PASS1_0)) || \
294 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \ 354 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
295 && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \ 355 && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
296 ))) 356 )))
@@ -300,14 +360,6 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
300{ 360{
301 uint32_t cpuid = cvmx_get_proc_id(); 361 uint32_t cpuid = cvmx_get_proc_id();
302 362
303 /*
304 * Check for special case of mismarked 3005 samples. We only
305 * need to check if the sub model isn't being ignored
306 */
307 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
308 if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
309 cpuid |= 0x10;
310 }
311 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid); 363 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
312} 364}
313 365
@@ -326,10 +378,21 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
326#define OCTEON_IS_COMMON_BINARY() 1 378#define OCTEON_IS_COMMON_BINARY() 1
327#undef OCTEON_MODEL 379#undef OCTEON_MODEL
328 380
381#define OCTEON_IS_OCTEON1() OCTEON_IS_MODEL(OCTEON_CN3XXX)
382#define OCTEON_IS_OCTEONPLUS() OCTEON_IS_MODEL(OCTEON_CN5XXX)
383#define OCTEON_IS_OCTEON2() \
384 (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
385
386#define OCTEON_IS_OCTEON3() OCTEON_IS_MODEL(OCTEON_CN7XXX)
387
388#define OCTEON_IS_OCTEON1PLUS() (OCTEON_IS_OCTEON1() || OCTEON_IS_OCTEONPLUS())
389
329const char *__init octeon_model_get_string(uint32_t chip_id); 390const char *__init octeon_model_get_string(uint32_t chip_id);
330 391
331/* 392/*
332 * Return the octeon family, i.e., ProcessorID of the PrID register. 393 * Return the octeon family, i.e., ProcessorID of the PrID register.
394 *
395 * @return the octeon family on success, ((unint32_t)-1) on error.
333 */ 396 */
334static inline uint32_t cvmx_get_octeon_family(void) 397static inline uint32_t cvmx_get_octeon_family(void)
335{ 398{
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 6dfefd2d5cdf..041596570856 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -9,6 +9,7 @@
9#define __ASM_OCTEON_OCTEON_H 9#define __ASM_OCTEON_OCTEON_H
10 10
11#include <asm/octeon/cvmx.h> 11#include <asm/octeon/cvmx.h>
12#include <asm/bitfield.h>
12 13
13extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size, 14extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
14 uint64_t alignment, 15 uint64_t alignment,
@@ -53,6 +54,7 @@ extern void octeon_io_clk_delay(unsigned long);
53#define OCTOEN_SERIAL_LEN 20 54#define OCTOEN_SERIAL_LEN 20
54 55
55struct octeon_boot_descriptor { 56struct octeon_boot_descriptor {
57#ifdef __BIG_ENDIAN_BITFIELD
56 /* Start of block referenced by assembly code - do not change! */ 58 /* Start of block referenced by assembly code - do not change! */
57 uint32_t desc_version; 59 uint32_t desc_version;
58 uint32_t desc_size; 60 uint32_t desc_size;
@@ -104,77 +106,149 @@ struct octeon_boot_descriptor {
104 uint8_t mac_addr_base[6]; 106 uint8_t mac_addr_base[6];
105 uint8_t mac_addr_count; 107 uint8_t mac_addr_count;
106 uint64_t cvmx_desc_vaddr; 108 uint64_t cvmx_desc_vaddr;
109#else
110 uint32_t desc_size;
111 uint32_t desc_version;
112 uint64_t stack_top;
113 uint64_t heap_base;
114 uint64_t heap_end;
115 /* Only used by bootloader */
116 uint64_t entry_point;
117 uint64_t desc_vaddr;
118 /* End of This block referenced by assembly code - do not change! */
119 uint32_t stack_size;
120 uint32_t exception_base_addr;
121 uint32_t argc;
122 uint32_t heap_size;
123 /*
124 * Argc count for application.
125 * Warning low bit scrambled in little-endian.
126 */
127 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
128
129#define BOOT_FLAG_INIT_CORE (1 << 0)
130#define OCTEON_BL_FLAG_DEBUG (1 << 1)
131#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
132 /* If set, use uart1 for console */
133#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
134 /* If set, use PCI console */
135#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
136 /* Call exit on break on serial port */
137#define OCTEON_BL_FLAG_BREAK (1 << 5)
138
139 uint32_t core_mask;
140 uint32_t flags;
141 /* physical address of free memory descriptor block. */
142 uint32_t phy_mem_desc_addr;
143 /* DRAM size in megabyes. */
144 uint32_t dram_size;
145 /* CPU clock speed, in hz. */
146 uint32_t eclock_hz;
147 /* used to pass flags from app to debugger. */
148 uint32_t debugger_flags_base_addr;
149 /* SPI4 clock in hz. */
150 uint32_t spi_clock_hz;
151 /* DRAM clock speed, in hz. */
152 uint32_t dclock_hz;
153 uint8_t chip_rev_minor;
154 uint8_t chip_rev_major;
155 uint16_t chip_type;
156 uint8_t board_rev_minor;
157 uint8_t board_rev_major;
158 uint16_t board_type;
159
160 uint64_t unused1[4]; /* Not even filled in by bootloader. */
161
162 uint64_t cvmx_desc_vaddr;
163#endif
107}; 164};
108 165
109union octeon_cvmemctl { 166union octeon_cvmemctl {
110 uint64_t u64; 167 uint64_t u64;
111 struct { 168 struct {
112 /* RO 1 = BIST fail, 0 = BIST pass */ 169 /* RO 1 = BIST fail, 0 = BIST pass */
113 uint64_t tlbbist:1; 170 __BITFIELD_FIELD(uint64_t tlbbist:1,
114 /* RO 1 = BIST fail, 0 = BIST pass */ 171 /* RO 1 = BIST fail, 0 = BIST pass */
115 uint64_t l1cbist:1; 172 __BITFIELD_FIELD(uint64_t l1cbist:1,
116 /* RO 1 = BIST fail, 0 = BIST pass */ 173 /* RO 1 = BIST fail, 0 = BIST pass */
117 uint64_t l1dbist:1; 174 __BITFIELD_FIELD(uint64_t l1dbist:1,
118 /* RO 1 = BIST fail, 0 = BIST pass */ 175 /* RO 1 = BIST fail, 0 = BIST pass */
119 uint64_t dcmbist:1; 176 __BITFIELD_FIELD(uint64_t dcmbist:1,
120 /* RO 1 = BIST fail, 0 = BIST pass */ 177 /* RO 1 = BIST fail, 0 = BIST pass */
121 uint64_t ptgbist:1; 178 __BITFIELD_FIELD(uint64_t ptgbist:1,
122 /* RO 1 = BIST fail, 0 = BIST pass */ 179 /* RO 1 = BIST fail, 0 = BIST pass */
123 uint64_t wbfbist:1; 180 __BITFIELD_FIELD(uint64_t wbfbist:1,
124 /* Reserved */ 181 /* Reserved */
125 uint64_t reserved:22; 182 __BITFIELD_FIELD(uint64_t reserved:17,
183 /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
184 * This field selects between the TLB replacement policies:
185 * bitmask LRU or NLU. Bitmask LRU maintains a mask of
186 * recently used TLB entries and avoids them as new entries
187 * are allocated. NLU simply guarantees that the next
188 * allocation is not the last used TLB entry. */
189 __BITFIELD_FIELD(uint64_t tlbnlu:1,
190 /* OCTEON II - Selects the bit in the counter used for
191 * releasing a PAUSE. This counter trips every 2(8+PAUSETIME)
192 * cycles. If not already released, the cnMIPS II core will
193 * always release a given PAUSE instruction within
194 * 2(8+PAUSETIME). If the counter trip happens to line up,
195 * the cnMIPS II core may release the PAUSE instantly. */
196 __BITFIELD_FIELD(uint64_t pausetime:3,
197 /* OCTEON II - This field is an extension of
198 * CvmMemCtl[DIDTTO] */
199 __BITFIELD_FIELD(uint64_t didtto2:1,
126 /* R/W If set, marked write-buffer entries time out 200 /* R/W If set, marked write-buffer entries time out
127 * the same as as other entries; if clear, marked 201 * the same as as other entries; if clear, marked
128 * write-buffer entries use the maximum timeout. */ 202 * write-buffer entries use the maximum timeout. */
129 uint64_t dismarkwblongto:1; 203 __BITFIELD_FIELD(uint64_t dismarkwblongto:1,
130 /* R/W If set, a merged store does not clear the 204 /* R/W If set, a merged store does not clear the
131 * write-buffer entry timeout state. */ 205 * write-buffer entry timeout state. */
132 uint64_t dismrgclrwbto:1; 206 __BITFIELD_FIELD(uint64_t dismrgclrwbto:1,
133 /* R/W Two bits that are the MSBs of the resultant 207 /* R/W Two bits that are the MSBs of the resultant
134 * CVMSEG LM word location for an IOBDMA. The other 8 208 * CVMSEG LM word location for an IOBDMA. The other 8
135 * bits come from the SCRADDR field of the IOBDMA. */ 209 * bits come from the SCRADDR field of the IOBDMA. */
136 uint64_t iobdmascrmsb:2; 210 __BITFIELD_FIELD(uint64_t iobdmascrmsb:2,
137 /* R/W If set, SYNCWS and SYNCS only order marked 211 /* R/W If set, SYNCWS and SYNCS only order marked
138 * stores; if clear, SYNCWS and SYNCS only order 212 * stores; if clear, SYNCWS and SYNCS only order
139 * unmarked stores. SYNCWSMARKED has no effect when 213 * unmarked stores. SYNCWSMARKED has no effect when
140 * DISSYNCWS is set. */ 214 * DISSYNCWS is set. */
141 uint64_t syncwsmarked:1; 215 __BITFIELD_FIELD(uint64_t syncwsmarked:1,
142 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as 216 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
143 * SYNC. */ 217 * SYNC. */
144 uint64_t dissyncws:1; 218 __BITFIELD_FIELD(uint64_t dissyncws:1,
145 /* R/W If set, no stall happens on write buffer 219 /* R/W If set, no stall happens on write buffer
146 * full. */ 220 * full. */
147 uint64_t diswbfst:1; 221 __BITFIELD_FIELD(uint64_t diswbfst:1,
148 /* R/W If set (and SX set), supervisor-level 222 /* R/W If set (and SX set), supervisor-level
149 * loads/stores can use XKPHYS addresses with 223 * loads/stores can use XKPHYS addresses with
150 * VA<48>==0 */ 224 * VA<48>==0 */
151 uint64_t xkmemenas:1; 225 __BITFIELD_FIELD(uint64_t xkmemenas:1,
152 /* R/W If set (and UX set), user-level loads/stores 226 /* R/W If set (and UX set), user-level loads/stores
153 * can use XKPHYS addresses with VA<48>==0 */ 227 * can use XKPHYS addresses with VA<48>==0 */
154 uint64_t xkmemenau:1; 228 __BITFIELD_FIELD(uint64_t xkmemenau:1,
155 /* R/W If set (and SX set), supervisor-level 229 /* R/W If set (and SX set), supervisor-level
156 * loads/stores can use XKPHYS addresses with 230 * loads/stores can use XKPHYS addresses with
157 * VA<48>==1 */ 231 * VA<48>==1 */
158 uint64_t xkioenas:1; 232 __BITFIELD_FIELD(uint64_t xkioenas:1,
159 /* R/W If set (and UX set), user-level loads/stores 233 /* R/W If set (and UX set), user-level loads/stores
160 * can use XKPHYS addresses with VA<48>==1 */ 234 * can use XKPHYS addresses with VA<48>==1 */
161 uint64_t xkioenau:1; 235 __BITFIELD_FIELD(uint64_t xkioenau:1,
162 /* R/W If set, all stores act as SYNCW (NOMERGE must 236 /* R/W If set, all stores act as SYNCW (NOMERGE must
163 * be set when this is set) RW, reset to 0. */ 237 * be set when this is set) RW, reset to 0. */
164 uint64_t allsyncw:1; 238 __BITFIELD_FIELD(uint64_t allsyncw:1,
165 /* R/W If set, no stores merge, and all stores reach 239 /* R/W If set, no stores merge, and all stores reach
166 * the coherent bus in order. */ 240 * the coherent bus in order. */
167 uint64_t nomerge:1; 241 __BITFIELD_FIELD(uint64_t nomerge:1,
168 /* R/W Selects the bit in the counter used for DID 242 /* R/W Selects the bit in the counter used for DID
169 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 = 243 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
170 * 214. Actual time-out is between 1x and 2x this 244 * 214. Actual time-out is between 1x and 2x this
171 * interval. For example, with DIDTTO=3, expiration 245 * interval. For example, with DIDTTO=3, expiration
172 * interval is between 16K and 32K. */ 246 * interval is between 16K and 32K. */
173 uint64_t didtto:2; 247 __BITFIELD_FIELD(uint64_t didtto:2,
174 /* R/W If set, the (mem) CSR clock never turns off. */ 248 /* R/W If set, the (mem) CSR clock never turns off. */
175 uint64_t csrckalwys:1; 249 __BITFIELD_FIELD(uint64_t csrckalwys:1,
176 /* R/W If set, mclk never turns off. */ 250 /* R/W If set, mclk never turns off. */
177 uint64_t mclkalwys:1; 251 __BITFIELD_FIELD(uint64_t mclkalwys:1,
178 /* R/W Selects the bit in the counter used for write 252 /* R/W Selects the bit in the counter used for write
179 * buffer flush time-outs (WBFLT+11) is the bit 253 * buffer flush time-outs (WBFLT+11) is the bit
180 * position in an internal counter used to determine 254 * position in an internal counter used to determine
@@ -182,25 +256,26 @@ union octeon_cvmemctl {
182 * 2x this interval. For example, with WBFLT = 0, a 256 * 2x this interval. For example, with WBFLT = 0, a
183 * write buffer expires between 2K and 4K cycles after 257 * write buffer expires between 2K and 4K cycles after
184 * the write buffer entry is allocated. */ 258 * the write buffer entry is allocated. */
185 uint64_t wbfltime:3; 259 __BITFIELD_FIELD(uint64_t wbfltime:3,
186 /* R/W If set, do not put Istream in the L2 cache. */ 260 /* R/W If set, do not put Istream in the L2 cache. */
187 uint64_t istrnol2:1; 261 __BITFIELD_FIELD(uint64_t istrnol2:1,
188 /* R/W The write buffer threshold. */ 262 /* R/W The write buffer threshold. */
189 uint64_t wbthresh:4; 263 __BITFIELD_FIELD(uint64_t wbthresh:4,
190 /* Reserved */ 264 /* Reserved */
191 uint64_t reserved2:2; 265 __BITFIELD_FIELD(uint64_t reserved2:2,
192 /* R/W If set, CVMSEG is available for loads/stores in 266 /* R/W If set, CVMSEG is available for loads/stores in
193 * kernel/debug mode. */ 267 * kernel/debug mode. */
194 uint64_t cvmsegenak:1; 268 __BITFIELD_FIELD(uint64_t cvmsegenak:1,
195 /* R/W If set, CVMSEG is available for loads/stores in 269 /* R/W If set, CVMSEG is available for loads/stores in
196 * supervisor mode. */ 270 * supervisor mode. */
197 uint64_t cvmsegenas:1; 271 __BITFIELD_FIELD(uint64_t cvmsegenas:1,
198 /* R/W If set, CVMSEG is available for loads/stores in 272 /* R/W If set, CVMSEG is available for loads/stores in
199 * user mode. */ 273 * user mode. */
200 uint64_t cvmsegenau:1; 274 __BITFIELD_FIELD(uint64_t cvmsegenau:1,
201 /* R/W Size of local memory in cache blocks, 54 (6912 275 /* R/W Size of local memory in cache blocks, 54 (6912
202 * bytes) is max legal value. */ 276 * bytes) is max legal value. */
203 uint64_t lmemsz:6; 277 __BITFIELD_FIELD(uint64_t lmemsz:6,
278 ;)))))))))))))))))))))))))))))))))
204 } s; 279 } s;
205}; 280};
206 281
@@ -224,6 +299,19 @@ static inline void octeon_npi_write32(uint64_t address, uint32_t val)
224 cvmx_read64_uint32(address ^ 4); 299 cvmx_read64_uint32(address ^ 4);
225} 300}
226 301
302/* Octeon multiplier save/restore routines from octeon_switch.S */
303void octeon_mult_save(void);
304void octeon_mult_restore(void);
305void octeon_mult_save_end(void);
306void octeon_mult_restore_end(void);
307void octeon_mult_save3(void);
308void octeon_mult_save3_end(void);
309void octeon_mult_save2(void);
310void octeon_mult_save2_end(void);
311void octeon_mult_restore3(void);
312void octeon_mult_restore3_end(void);
313void octeon_mult_restore2(void);
314void octeon_mult_restore2_end(void);
227 315
228/** 316/**
229 * Read a 32bit value from the Octeon NPI register space 317 * Read a 32bit value from the Octeon NPI register space
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 69529624a005..193b4c6b7541 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -121,6 +121,7 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
121} 121}
122#endif 122#endif
123 123
124#ifdef CONFIG_PCI_DOMAINS
124#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index 125#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
125 126
126static inline int pci_proc_domain(struct pci_bus *bus) 127static inline int pci_proc_domain(struct pci_bus *bus)
@@ -128,6 +129,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)
128 struct pci_controller *hose = bus->sysdata; 129 struct pci_controller *hose = bus->sysdata;
129 return hose->need_domain_info; 130 return hose->need_domain_info;
130} 131}
132#endif /* CONFIG_PCI_DOMAINS */
131 133
132#endif /* __KERNEL__ */ 134#endif /* __KERNEL__ */
133 135
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index fc807aa5ec8d..91747c282bb3 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -35,7 +35,7 @@
35#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 35#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
36 36
37/* 37/*
38 * The following bits are directly used by the TLB hardware 38 * The following bits are implemented by the TLB hardware
39 */ 39 */
40#define _PAGE_GLOBAL_SHIFT 0 40#define _PAGE_GLOBAL_SHIFT 0
41#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 41#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
@@ -60,43 +60,40 @@
60#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 60#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
61#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 61#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
62 62
63#define _PAGE_SILENT_READ _PAGE_VALID
64#define _PAGE_SILENT_WRITE _PAGE_DIRTY
65
66#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 63#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
67 64
68#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 65#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
69 66
70/* 67/*
71 * The following are implemented by software 68 * The following bits are implemented in software
72 */ 69 */
73#define _PAGE_PRESENT_SHIFT 0 70#define _PAGE_PRESENT_SHIFT (0)
74#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 71#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
75#define _PAGE_READ_SHIFT 1 72#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
76#define _PAGE_READ (1 << _PAGE_READ_SHIFT) 73#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
77#define _PAGE_WRITE_SHIFT 2 74#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
78#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 75#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
79#define _PAGE_ACCESSED_SHIFT 3 76#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
80#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 77#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
81#define _PAGE_MODIFIED_SHIFT 4 78#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
82#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 79#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
83 80
84/* 81/*
85 * And these are the hardware TLB bits 82 * The following bits are implemented by the TLB hardware
86 */ 83 */
87#define _PAGE_GLOBAL_SHIFT 8 84#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
88#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 85#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
89#define _PAGE_VALID_SHIFT 9 86#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
90#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 87#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
91#define _PAGE_SILENT_READ (1 << _PAGE_VALID_SHIFT) /* synonym */ 88#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
92#define _PAGE_DIRTY_SHIFT 10
93#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 89#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
94#define _PAGE_SILENT_WRITE (1 << _PAGE_DIRTY_SHIFT) 90#define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
95#define _CACHE_UNCACHED_SHIFT 11
96#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) 91#define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
97#define _CACHE_MASK (1 << _CACHE_UNCACHED_SHIFT) 92#define _CACHE_MASK _CACHE_UNCACHED
98 93
99#else /* 'Normal' r4K case */ 94#define _PFN_SHIFT PAGE_SHIFT
95
96#else
100/* 97/*
101 * When using the RI/XI bit support, we have 13 bits of flags below 98 * When using the RI/XI bit support, we have 13 bits of flags below
102 * the physical address. The RI/XI bits are placed such that a SRL 5 99 * the physical address. The RI/XI bits are placed such that a SRL 5
@@ -107,10 +104,8 @@
107 104
108/* 105/*
109 * The following bits are implemented in software 106 * The following bits are implemented in software
110 *
111 * _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi.
112 */ 107 */
113#define _PAGE_PRESENT_SHIFT (0) 108#define _PAGE_PRESENT_SHIFT 0
114#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 109#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
115#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) 110#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
116#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) 111#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
@@ -125,16 +120,11 @@
125/* huge tlb page */ 120/* huge tlb page */
126#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 121#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
127#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 122#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
128#else
129#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT)
130#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
131#endif
132
133#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
134/* huge tlb page */
135#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) 123#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
136#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 124#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
137#else 125#else
126#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT)
127#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
138#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT) 128#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT)
139#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */ 129#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */
140#endif 130#endif
@@ -149,17 +139,10 @@
149 139
150#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 140#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
151#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 141#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
152
153#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 142#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
154#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 143#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
155/* synonym */
156#define _PAGE_SILENT_READ (_PAGE_VALID)
157
158/* The MIPS dirty bit */
159#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 144#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
160#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 145#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
161#define _PAGE_SILENT_WRITE (_PAGE_DIRTY)
162
163#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 146#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
164#define _CACHE_MASK (7 << _CACHE_SHIFT) 147#define _CACHE_MASK (7 << _CACHE_SHIFT)
165 148
@@ -167,9 +150,9 @@
167 150
168#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ 151#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
169 152
170#ifndef _PFN_SHIFT 153#define _PAGE_SILENT_READ _PAGE_VALID
171#define _PFN_SHIFT PAGE_SHIFT 154#define _PAGE_SILENT_WRITE _PAGE_DIRTY
172#endif 155
173#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) 156#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
174 157
175#ifndef _PAGE_NO_READ 158#ifndef _PAGE_NO_READ
@@ -179,9 +162,6 @@
179#ifndef _PAGE_NO_EXEC 162#ifndef _PAGE_NO_EXEC
180#define _PAGE_NO_EXEC ({BUG(); 0; }) 163#define _PAGE_NO_EXEC ({BUG(); 0; })
181#endif 164#endif
182#ifndef _PAGE_GLOBAL_SHIFT
183#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL)
184#endif
185 165
186 166
187#ifndef __ASSEMBLY__ 167#ifndef __ASSEMBLY__
@@ -266,8 +246,9 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
266#endif 246#endif
267 247
268#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) 248#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
269#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 249#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
270 250
271#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 251#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
252 _PFN_MASK | _CACHE_MASK)
272 253
273#endif /* _ASM_PGTABLE_BITS_H */ 254#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 583ff4215479..bef782c4a44b 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -99,29 +99,35 @@ extern void paging_init(void);
99 99
100#define htw_stop() \ 100#define htw_stop() \
101do { \ 101do { \
102 if (cpu_has_htw) \ 102 unsigned long flags; \
103 write_c0_pwctl(read_c0_pwctl() & \ 103 \
104 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \ 104 if (cpu_has_htw) { \
105 local_irq_save(flags); \
106 if(!raw_current_cpu_data.htw_seq++) { \
107 write_c0_pwctl(read_c0_pwctl() & \
108 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
109 back_to_back_c0_hazard(); \
110 } \
111 local_irq_restore(flags); \
112 } \
105} while(0) 113} while(0)
106 114
107#define htw_start() \ 115#define htw_start() \
108do { \ 116do { \
109 if (cpu_has_htw) \ 117 unsigned long flags; \
110 write_c0_pwctl(read_c0_pwctl() | \ 118 \
111 (1 << MIPS_PWCTL_PWEN_SHIFT)); \
112} while(0)
113
114
115#define htw_reset() \
116do { \
117 if (cpu_has_htw) { \ 119 if (cpu_has_htw) { \
118 htw_stop(); \ 120 local_irq_save(flags); \
119 back_to_back_c0_hazard(); \ 121 if (!--raw_current_cpu_data.htw_seq) { \
120 htw_start(); \ 122 write_c0_pwctl(read_c0_pwctl() | \
121 back_to_back_c0_hazard(); \ 123 (1 << MIPS_PWCTL_PWEN_SHIFT)); \
124 back_to_back_c0_hazard(); \
125 } \
126 local_irq_restore(flags); \
122 } \ 127 } \
123} while(0) 128} while(0)
124 129
130
125extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 131extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
126 pte_t pteval); 132 pte_t pteval);
127 133
@@ -153,12 +159,13 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
153{ 159{
154 pte_t null = __pte(0); 160 pte_t null = __pte(0);
155 161
162 htw_stop();
156 /* Preserve global status for the pair */ 163 /* Preserve global status for the pair */
157 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL) 164 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
158 null.pte_low = null.pte_high = _PAGE_GLOBAL; 165 null.pte_low = null.pte_high = _PAGE_GLOBAL;
159 166
160 set_pte_at(mm, addr, ptep, null); 167 set_pte_at(mm, addr, ptep, null);
161 htw_reset(); 168 htw_start();
162} 169}
163#else 170#else
164 171
@@ -188,6 +195,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
188 195
189static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 196static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
190{ 197{
198 htw_stop();
191#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX) 199#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
192 /* Preserve global status for the pair */ 200 /* Preserve global status for the pair */
193 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) 201 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
@@ -195,7 +203,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
195 else 203 else
196#endif 204#endif
197 set_pte_at(mm, addr, ptep, __pte(0)); 205 set_pte_at(mm, addr, ptep, __pte(0));
198 htw_reset(); 206 htw_start();
199} 207}
200#endif 208#endif
201 209
@@ -334,7 +342,7 @@ static inline pte_t pte_mkyoung(pte_t pte)
334 return pte; 342 return pte;
335} 343}
336 344
337#ifdef _PAGE_HUGE 345#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
338static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; } 346static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
339 347
340static inline pte_t pte_mkhuge(pte_t pte) 348static inline pte_t pte_mkhuge(pte_t pte)
@@ -342,7 +350,7 @@ static inline pte_t pte_mkhuge(pte_t pte)
342 pte_val(pte) |= _PAGE_HUGE; 350 pte_val(pte) |= _PAGE_HUGE;
343 return pte; 351 return pte;
344} 352}
345#endif /* _PAGE_HUGE */ 353#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
346#endif 354#endif
347static inline int pte_special(pte_t pte) { return 0; } 355static inline int pte_special(pte_t pte) { return 0; }
348static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 356static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index f1df4cb4a286..b5dcbee01fd7 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -54,9 +54,7 @@ extern unsigned int vced_count, vcei_count;
54#define TASK_SIZE 0x7fff8000UL 54#define TASK_SIZE 0x7fff8000UL
55#endif 55#endif
56 56
57#ifdef __KERNEL__
58#define STACK_TOP_MAX TASK_SIZE 57#define STACK_TOP_MAX TASK_SIZE
59#endif
60 58
61#define TASK_IS_32BIT_ADDR 1 59#define TASK_IS_32BIT_ADDR 1
62 60
@@ -73,11 +71,7 @@ extern unsigned int vced_count, vcei_count;
73#define TASK_SIZE32 0x7fff8000UL 71#define TASK_SIZE32 0x7fff8000UL
74#define TASK_SIZE64 0x10000000000UL 72#define TASK_SIZE64 0x10000000000UL
75#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 73#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
76
77#ifdef __KERNEL__
78#define STACK_TOP_MAX TASK_SIZE64 74#define STACK_TOP_MAX TASK_SIZE64
79#endif
80
81 75
82#define TASK_SIZE_OF(tsk) \ 76#define TASK_SIZE_OF(tsk) \
83 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 77 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
@@ -211,6 +205,8 @@ struct octeon_cop2_state {
211 unsigned long cop2_gfm_poly; 205 unsigned long cop2_gfm_poly;
212 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 206 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
213 unsigned long cop2_gfm_result[2]; 207 unsigned long cop2_gfm_result[2];
208 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
209 unsigned long cop2_sha3[2];
214}; 210};
215#define COP2_INIT \ 211#define COP2_INIT \
216 .cp2 = {0,}, 212 .cp2 = {0,},
@@ -399,4 +395,15 @@ unsigned long get_wchan(struct task_struct *p);
399 395
400#endif 396#endif
401 397
398/*
399 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
400 * to the prctl syscall.
401 */
402extern int mips_get_process_fp_mode(struct task_struct *task);
403extern int mips_set_process_fp_mode(struct task_struct *task,
404 unsigned int value);
405
406#define GET_FP_MODE(task) mips_get_process_fp_mode(task)
407#define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value)
408
402#endif /* _ASM_PROCESSOR_H */ 409#endif /* _ASM_PROCESSOR_H */
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index eaa26270a5e5..8ebc2aa5f3e1 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -24,13 +24,6 @@ struct boot_param_header;
24extern void __dt_setup_arch(void *bph); 24extern void __dt_setup_arch(void *bph);
25extern int __dt_register_buses(const char *bus0, const char *bus1); 25extern int __dt_register_buses(const char *bus0, const char *bus1);
26 26
27#define dt_setup_arch(sym) \
28({ \
29 extern char __dtb_##sym##_begin[]; \
30 \
31 __dt_setup_arch(__dtb_##sym##_begin); \
32})
33
34#else /* CONFIG_OF */ 27#else /* CONFIG_OF */
35static inline void device_tree_init(void) { } 28static inline void device_tree_init(void) { }
36#endif /* CONFIG_OF */ 29#endif /* CONFIG_OF */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index fc783f843bdc..ffc320389f40 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -40,8 +40,8 @@ struct pt_regs {
40 unsigned long cp0_cause; 40 unsigned long cp0_cause;
41 unsigned long cp0_epc; 41 unsigned long cp0_epc;
42#ifdef CONFIG_CPU_CAVIUM_OCTEON 42#ifdef CONFIG_CPU_CAVIUM_OCTEON
43 unsigned long long mpl[3]; /* MTM{0,1,2} */ 43 unsigned long long mpl[6]; /* MTM{0-5} */
44 unsigned long long mtp[3]; /* MTP{0,1,2} */ 44 unsigned long long mtp[6]; /* MTP{0-5} */
45#endif 45#endif
46} __aligned(8); 46} __aligned(8);
47 47
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index e293a8d89a6d..1b22d2da88a1 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -14,6 +14,7 @@
14 14
15#include <asm/asm.h> 15#include <asm/asm.h>
16#include <asm/cacheops.h> 16#include <asm/cacheops.h>
17#include <asm/compiler.h>
17#include <asm/cpu-features.h> 18#include <asm/cpu-features.h>
18#include <asm/cpu-type.h> 19#include <asm/cpu-type.h>
19#include <asm/mipsmtregs.h> 20#include <asm/mipsmtregs.h>
@@ -39,7 +40,7 @@ extern void (*r4k_blast_icache)(void);
39 __asm__ __volatile__( \ 40 __asm__ __volatile__( \
40 " .set push \n" \ 41 " .set push \n" \
41 " .set noreorder \n" \ 42 " .set noreorder \n" \
42 " .set arch=r4000 \n" \ 43 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
43 " cache %0, %1 \n" \ 44 " cache %0, %1 \n" \
44 " .set pop \n" \ 45 " .set pop \n" \
45 : \ 46 : \
@@ -147,7 +148,7 @@ static inline void flush_scache_line(unsigned long addr)
147 __asm__ __volatile__( \ 148 __asm__ __volatile__( \
148 " .set push \n" \ 149 " .set push \n" \
149 " .set noreorder \n" \ 150 " .set noreorder \n" \
150 " .set arch=r4000 \n" \ 151 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
151 "1: cache %0, (%1) \n" \ 152 "1: cache %0, (%1) \n" \
152 "2: .set pop \n" \ 153 "2: .set pop \n" \
153 " .section __ex_table,\"a\" \n" \ 154 " .section __ex_table,\"a\" \n" \
@@ -218,6 +219,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
218 cache_op(Page_Invalidate_T, addr); 219 cache_op(Page_Invalidate_T, addr);
219} 220}
220 221
222#ifndef CONFIG_CPU_MIPSR6
221#define cache16_unroll32(base,op) \ 223#define cache16_unroll32(base,op) \
222 __asm__ __volatile__( \ 224 __asm__ __volatile__( \
223 " .set push \n" \ 225 " .set push \n" \
@@ -322,6 +324,150 @@ static inline void invalidate_tcache_page(unsigned long addr)
322 : "r" (base), \ 324 : "r" (base), \
323 "i" (op)); 325 "i" (op));
324 326
327#else
328/*
329 * MIPS R6 changed the cache opcode and moved to a 8-bit offset field.
330 * This means we now need to increment the base register before we flush
331 * more cache lines
332 */
333#define cache16_unroll32(base,op) \
334 __asm__ __volatile__( \
335 " .set push\n" \
336 " .set noreorder\n" \
337 " .set mips64r6\n" \
338 " .set noat\n" \
339 " cache %1, 0x000(%0); cache %1, 0x010(%0)\n" \
340 " cache %1, 0x020(%0); cache %1, 0x030(%0)\n" \
341 " cache %1, 0x040(%0); cache %1, 0x050(%0)\n" \
342 " cache %1, 0x060(%0); cache %1, 0x070(%0)\n" \
343 " cache %1, 0x080(%0); cache %1, 0x090(%0)\n" \
344 " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \
345 " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \
346 " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \
347 " addiu $1, $0, 0x100 \n" \
348 " cache %1, 0x000($1); cache %1, 0x010($1)\n" \
349 " cache %1, 0x020($1); cache %1, 0x030($1)\n" \
350 " cache %1, 0x040($1); cache %1, 0x050($1)\n" \
351 " cache %1, 0x060($1); cache %1, 0x070($1)\n" \
352 " cache %1, 0x080($1); cache %1, 0x090($1)\n" \
353 " cache %1, 0x0a0($1); cache %1, 0x0b0($1)\n" \
354 " cache %1, 0x0c0($1); cache %1, 0x0d0($1)\n" \
355 " cache %1, 0x0e0($1); cache %1, 0x0f0($1)\n" \
356 " .set pop\n" \
357 : \
358 : "r" (base), \
359 "i" (op));
360
361#define cache32_unroll32(base,op) \
362 __asm__ __volatile__( \
363 " .set push\n" \
364 " .set noreorder\n" \
365 " .set mips64r6\n" \
366 " .set noat\n" \
367 " cache %1, 0x000(%0); cache %1, 0x020(%0)\n" \
368 " cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \
369 " cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \
370 " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \
371 " addiu $1, %0, 0x100\n" \
372 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \
373 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \
374 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
375 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
376 " addiu $1, $1, 0x100\n" \
377 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \
378 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \
379 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
380 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
381 " addiu $1, $1, 0x100\n" \
382 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \
383 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \
384 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
385 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
386 " .set pop\n" \
387 : \
388 : "r" (base), \
389 "i" (op));
390
391#define cache64_unroll32(base,op) \
392 __asm__ __volatile__( \
393 " .set push\n" \
394 " .set noreorder\n" \
395 " .set mips64r6\n" \
396 " .set noat\n" \
397 " cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \
398 " cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \
399 " addiu $1, %0, 0x100\n" \
400 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
401 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
402 " addiu $1, %0, 0x100\n" \
403 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
404 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
405 " addiu $1, %0, 0x100\n" \
406 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
407 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
408 " addiu $1, %0, 0x100\n" \
409 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
410 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
411 " addiu $1, %0, 0x100\n" \
412 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
413 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
414 " addiu $1, %0, 0x100\n" \
415 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
416 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
417 " addiu $1, %0, 0x100\n" \
418 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
419 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
420 " .set pop\n" \
421 : \
422 : "r" (base), \
423 "i" (op));
424
425#define cache128_unroll32(base,op) \
426 __asm__ __volatile__( \
427 " .set push\n" \
428 " .set noreorder\n" \
429 " .set mips64r6\n" \
430 " .set noat\n" \
431 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
432 " addiu $1, %0, 0x100\n" \
433 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
434 " addiu $1, %0, 0x100\n" \
435 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
436 " addiu $1, %0, 0x100\n" \
437 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
438 " addiu $1, %0, 0x100\n" \
439 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
440 " addiu $1, %0, 0x100\n" \
441 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
442 " addiu $1, %0, 0x100\n" \
443 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
444 " addiu $1, %0, 0x100\n" \
445 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
446 " addiu $1, %0, 0x100\n" \
447 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
448 " addiu $1, %0, 0x100\n" \
449 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
450 " addiu $1, %0, 0x100\n" \
451 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
452 " addiu $1, %0, 0x100\n" \
453 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
454 " addiu $1, %0, 0x100\n" \
455 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
456 " addiu $1, %0, 0x100\n" \
457 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
458 " addiu $1, %0, 0x100\n" \
459 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
460 " addiu $1, %0, 0x100\n" \
461 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
462 " addiu $1, %0, 0x100\n" \
463 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
464 " addiu $1, %0, 0x100\n" \
465 " .set pop\n" \
466 : \
467 : "r" (base), \
468 "i" (op));
469#endif /* CONFIG_CPU_MIPSR6 */
470
325/* 471/*
326 * Perform the cache operation specified by op using a user mode virtual 472 * Perform the cache operation specified by op using a user mode virtual
327 * address while in kernel mode. 473 * address while in kernel mode.
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index 753275accd18..195db5045ae5 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -11,6 +11,7 @@
11#ifndef _ASM_SGIALIB_H 11#ifndef _ASM_SGIALIB_H
12#define _ASM_SGIALIB_H 12#define _ASM_SGIALIB_H
13 13
14#include <linux/compiler.h>
14#include <asm/sgiarcs.h> 15#include <asm/sgiarcs.h>
15 16
16extern struct linux_romvec *romvec; 17extern struct linux_romvec *romvec;
@@ -70,8 +71,11 @@ extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
70extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt); 71extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
71 72
72/* Misc. routines. */ 73/* Misc. routines. */
73extern VOID ArcReboot(VOID) __attribute__((noreturn)); 74extern VOID ArcHalt(VOID) __noreturn;
74extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); 75extern VOID ArcPowerDown(VOID) __noreturn;
76extern VOID ArcRestart(VOID) __noreturn;
77extern VOID ArcReboot(VOID) __noreturn;
78extern VOID ArcEnterInteractiveMode(VOID) __noreturn;
75extern VOID ArcFlushAllCaches(VOID); 79extern VOID ArcFlushAllCaches(VOID);
76extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID); 80extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID);
77 81
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
deleted file mode 100644
index dd9a762646fc..000000000000
--- a/arch/mips/include/asm/siginfo.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 1999, 2001, 2003 Ralf Baechle
7 * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SIGINFO_H
10#define _ASM_SIGINFO_H
11
12#include <uapi/asm/siginfo.h>
13
14
15/*
16 * Duplicated here because of <asm-generic/siginfo.h> braindamage ...
17 */
18#include <linux/string.h>
19
20static inline void copy_siginfo(struct siginfo *to, struct siginfo *from)
21{
22 if (from->si_code < 0)
23 memcpy(to, from, sizeof(*to));
24 else
25 /* _sigchld is currently the largest know union member */
26 memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld));
27}
28
29#endif /* _ASM_SIGINFO_H */
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index c6d06d383ef9..b4548690ade9 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -89,7 +89,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
89 " subu %[ticket], %[ticket], 1 \n" 89 " subu %[ticket], %[ticket], 1 \n"
90 " .previous \n" 90 " .previous \n"
91 " .set pop \n" 91 " .set pop \n"
92 : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock), 92 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
93 [serving_now_ptr] "+m" (lock->h.serving_now), 93 [serving_now_ptr] "+m" (lock->h.serving_now),
94 [ticket] "=&r" (tmp), 94 [ticket] "=&r" (tmp),
95 [my_ticket] "=&r" (my_ticket) 95 [my_ticket] "=&r" (my_ticket)
@@ -122,7 +122,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
122 " subu %[ticket], %[ticket], 1 \n" 122 " subu %[ticket], %[ticket], 1 \n"
123 " .previous \n" 123 " .previous \n"
124 " .set pop \n" 124 " .set pop \n"
125 : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock), 125 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
126 [serving_now_ptr] "+m" (lock->h.serving_now), 126 [serving_now_ptr] "+m" (lock->h.serving_now),
127 [ticket] "=&r" (tmp), 127 [ticket] "=&r" (tmp),
128 [my_ticket] "=&r" (my_ticket) 128 [my_ticket] "=&r" (my_ticket)
@@ -164,7 +164,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
164 " li %[ticket], 0 \n" 164 " li %[ticket], 0 \n"
165 " .previous \n" 165 " .previous \n"
166 " .set pop \n" 166 " .set pop \n"
167 : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock), 167 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
168 [ticket] "=&r" (tmp), 168 [ticket] "=&r" (tmp),
169 [my_ticket] "=&r" (tmp2), 169 [my_ticket] "=&r" (tmp2),
170 [now_serving] "=&r" (tmp3) 170 [now_serving] "=&r" (tmp3)
@@ -188,7 +188,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
188 " li %[ticket], 0 \n" 188 " li %[ticket], 0 \n"
189 " .previous \n" 189 " .previous \n"
190 " .set pop \n" 190 " .set pop \n"
191 : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock), 191 : [ticket_ptr] "+" GCC_OFF_SMALL_ASM() (lock->lock),
192 [ticket] "=&r" (tmp), 192 [ticket] "=&r" (tmp),
193 [my_ticket] "=&r" (tmp2), 193 [my_ticket] "=&r" (tmp2),
194 [now_serving] "=&r" (tmp3) 194 [now_serving] "=&r" (tmp3)
@@ -235,8 +235,8 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
235 " beqzl %1, 1b \n" 235 " beqzl %1, 1b \n"
236 " nop \n" 236 " nop \n"
237 " .set reorder \n" 237 " .set reorder \n"
238 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp) 238 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
239 : GCC_OFF12_ASM() (rw->lock) 239 : GCC_OFF_SMALL_ASM() (rw->lock)
240 : "memory"); 240 : "memory");
241 } else { 241 } else {
242 do { 242 do {
@@ -245,8 +245,8 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
245 " bltz %1, 1b \n" 245 " bltz %1, 1b \n"
246 " addu %1, 1 \n" 246 " addu %1, 1 \n"
247 "2: sc %1, %0 \n" 247 "2: sc %1, %0 \n"
248 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp) 248 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
249 : GCC_OFF12_ASM() (rw->lock) 249 : GCC_OFF_SMALL_ASM() (rw->lock)
250 : "memory"); 250 : "memory");
251 } while (unlikely(!tmp)); 251 } while (unlikely(!tmp));
252 } 252 }
@@ -254,9 +254,6 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
254 smp_llsc_mb(); 254 smp_llsc_mb();
255} 255}
256 256
257/* Note the use of sub, not subu which will make the kernel die with an
258 overflow exception if we ever try to unlock an rwlock that is already
259 unlocked or is being held by a writer. */
260static inline void arch_read_unlock(arch_rwlock_t *rw) 257static inline void arch_read_unlock(arch_rwlock_t *rw)
261{ 258{
262 unsigned int tmp; 259 unsigned int tmp;
@@ -266,20 +263,20 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
266 if (R10000_LLSC_WAR) { 263 if (R10000_LLSC_WAR) {
267 __asm__ __volatile__( 264 __asm__ __volatile__(
268 "1: ll %1, %2 # arch_read_unlock \n" 265 "1: ll %1, %2 # arch_read_unlock \n"
269 " sub %1, 1 \n" 266 " addiu %1, 1 \n"
270 " sc %1, %0 \n" 267 " sc %1, %0 \n"
271 " beqzl %1, 1b \n" 268 " beqzl %1, 1b \n"
272 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp) 269 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
273 : GCC_OFF12_ASM() (rw->lock) 270 : GCC_OFF_SMALL_ASM() (rw->lock)
274 : "memory"); 271 : "memory");
275 } else { 272 } else {
276 do { 273 do {
277 __asm__ __volatile__( 274 __asm__ __volatile__(
278 "1: ll %1, %2 # arch_read_unlock \n" 275 "1: ll %1, %2 # arch_read_unlock \n"
279 " sub %1, 1 \n" 276 " addiu %1, -1 \n"
280 " sc %1, %0 \n" 277 " sc %1, %0 \n"
281 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp) 278 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
282 : GCC_OFF12_ASM() (rw->lock) 279 : GCC_OFF_SMALL_ASM() (rw->lock)
283 : "memory"); 280 : "memory");
284 } while (unlikely(!tmp)); 281 } while (unlikely(!tmp));
285 } 282 }
@@ -299,8 +296,8 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
299 " beqzl %1, 1b \n" 296 " beqzl %1, 1b \n"
300 " nop \n" 297 " nop \n"
301 " .set reorder \n" 298 " .set reorder \n"
302 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp) 299 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
303 : GCC_OFF12_ASM() (rw->lock) 300 : GCC_OFF_SMALL_ASM() (rw->lock)
304 : "memory"); 301 : "memory");
305 } else { 302 } else {
306 do { 303 do {
@@ -309,8 +306,8 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
309 " bnez %1, 1b \n" 306 " bnez %1, 1b \n"
310 " lui %1, 0x8000 \n" 307 " lui %1, 0x8000 \n"
311 "2: sc %1, %0 \n" 308 "2: sc %1, %0 \n"
312 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp) 309 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
313 : GCC_OFF12_ASM() (rw->lock) 310 : GCC_OFF_SMALL_ASM() (rw->lock)
314 : "memory"); 311 : "memory");
315 } while (unlikely(!tmp)); 312 } while (unlikely(!tmp));
316 } 313 }
@@ -349,8 +346,8 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
349 __WEAK_LLSC_MB 346 __WEAK_LLSC_MB
350 " li %2, 1 \n" 347 " li %2, 1 \n"
351 "2: \n" 348 "2: \n"
352 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) 349 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
353 : GCC_OFF12_ASM() (rw->lock) 350 : GCC_OFF_SMALL_ASM() (rw->lock)
354 : "memory"); 351 : "memory");
355 } else { 352 } else {
356 __asm__ __volatile__( 353 __asm__ __volatile__(
@@ -366,8 +363,8 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
366 __WEAK_LLSC_MB 363 __WEAK_LLSC_MB
367 " li %2, 1 \n" 364 " li %2, 1 \n"
368 "2: \n" 365 "2: \n"
369 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) 366 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
370 : GCC_OFF12_ASM() (rw->lock) 367 : GCC_OFF_SMALL_ASM() (rw->lock)
371 : "memory"); 368 : "memory");
372 } 369 }
373 370
@@ -393,8 +390,8 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
393 " li %2, 1 \n" 390 " li %2, 1 \n"
394 " .set reorder \n" 391 " .set reorder \n"
395 "2: \n" 392 "2: \n"
396 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret) 393 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
397 : GCC_OFF12_ASM() (rw->lock) 394 : GCC_OFF_SMALL_ASM() (rw->lock)
398 : "memory"); 395 : "memory");
399 } else { 396 } else {
400 do { 397 do {
@@ -406,9 +403,9 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
406 " sc %1, %0 \n" 403 " sc %1, %0 \n"
407 " li %2, 1 \n" 404 " li %2, 1 \n"
408 "2: \n" 405 "2: \n"
409 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), 406 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp),
410 "=&r" (ret) 407 "=&r" (ret)
411 : GCC_OFF12_ASM() (rw->lock) 408 : GCC_OFF_SMALL_ASM() (rw->lock)
412 : "memory"); 409 : "memory");
413 } while (unlikely(!tmp)); 410 } while (unlikely(!tmp));
414 411
diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h
index 0b89006e4907..0f90d88e464d 100644
--- a/arch/mips/include/asm/spram.h
+++ b/arch/mips/include/asm/spram.h
@@ -1,10 +1,10 @@
1#ifndef _MIPS_SPRAM_H 1#ifndef _MIPS_SPRAM_H
2#define _MIPS_SPRAM_H 2#define _MIPS_SPRAM_H
3 3
4#ifdef CONFIG_CPU_MIPSR2 4#if defined(CONFIG_MIPS_SPRAM)
5extern __init void spram_config(void); 5extern __init void spram_config(void);
6#else 6#else
7static inline void spram_config(void) { }; 7static inline void spram_config(void) { };
8#endif /* CONFIG_CPU_MIPSR2 */ 8#endif /* CONFIG_MIPS_SPRAM */
9 9
10#endif /* _MIPS_SPRAM_H */ 10#endif /* _MIPS_SPRAM_H */
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index b188c797565c..28d6d9364bd1 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -40,7 +40,7 @@
40 LONG_S v1, PT_HI(sp) 40 LONG_S v1, PT_HI(sp)
41 mflhxu v1 41 mflhxu v1
42 LONG_S v1, PT_ACX(sp) 42 LONG_S v1, PT_ACX(sp)
43#else 43#elif !defined(CONFIG_CPU_MIPSR6)
44 mfhi v1 44 mfhi v1
45#endif 45#endif
46#ifdef CONFIG_32BIT 46#ifdef CONFIG_32BIT
@@ -50,7 +50,7 @@
50 LONG_S $10, PT_R10(sp) 50 LONG_S $10, PT_R10(sp)
51 LONG_S $11, PT_R11(sp) 51 LONG_S $11, PT_R11(sp)
52 LONG_S $12, PT_R12(sp) 52 LONG_S $12, PT_R12(sp)
53#ifndef CONFIG_CPU_HAS_SMARTMIPS 53#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
54 LONG_S v1, PT_HI(sp) 54 LONG_S v1, PT_HI(sp)
55 mflo v1 55 mflo v1
56#endif 56#endif
@@ -58,7 +58,7 @@
58 LONG_S $14, PT_R14(sp) 58 LONG_S $14, PT_R14(sp)
59 LONG_S $15, PT_R15(sp) 59 LONG_S $15, PT_R15(sp)
60 LONG_S $24, PT_R24(sp) 60 LONG_S $24, PT_R24(sp)
61#ifndef CONFIG_CPU_HAS_SMARTMIPS 61#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
62 LONG_S v1, PT_LO(sp) 62 LONG_S v1, PT_LO(sp)
63#endif 63#endif
64#ifdef CONFIG_CPU_CAVIUM_OCTEON 64#ifdef CONFIG_CPU_CAVIUM_OCTEON
@@ -226,7 +226,7 @@
226 mtlhx $24 226 mtlhx $24
227 LONG_L $24, PT_LO(sp) 227 LONG_L $24, PT_LO(sp)
228 mtlhx $24 228 mtlhx $24
229#else 229#elif !defined(CONFIG_CPU_MIPSR6)
230 LONG_L $24, PT_LO(sp) 230 LONG_L $24, PT_LO(sp)
231 mtlo $24 231 mtlo $24
232 LONG_L $24, PT_HI(sp) 232 LONG_L $24, PT_HI(sp)
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index b928b6f898cd..e92d6c4b5ed1 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -75,9 +75,12 @@ do { \
75#endif 75#endif
76 76
77#define __clear_software_ll_bit() \ 77#define __clear_software_ll_bit() \
78do { \ 78do { if (cpu_has_rw_llb) { \
79 if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \ 79 write_c0_lladdr(0); \
80 ll_bit = 0; \ 80 } else { \
81 if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)\
82 ll_bit = 0; \
83 } \
81} while (0) 84} while (0)
82 85
83#define switch_to(prev, next, last) \ 86#define switch_to(prev, next, last) \
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 9e1295f874f0..55ed6602204c 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -28,7 +28,7 @@ struct thread_info {
28 unsigned long tp_value; /* thread pointer */ 28 unsigned long tp_value; /* thread pointer */
29 __u32 cpu; /* current CPU */ 29 __u32 cpu; /* current CPU */
30 int preempt_count; /* 0 => preemptable, <0 => BUG */ 30 int preempt_count; /* 0 => preemptable, <0 => BUG */
31 31 int r2_emul_return; /* 1 => Returning from R2 emulator */
32 mm_segment_t addr_limit; /* 32 mm_segment_t addr_limit; /*
33 * thread address space limit: 33 * thread address space limit:
34 * 0x7fffffff for user-thead 34 * 0x7fffffff for user-thead
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 01:14:07 -0500