1 files changed, 8 insertions, 8 deletions

diff --git a/arch/mips/include/asm/sn/intr.h b/arch/mips/include/asm/sn/intr.h
index 6718b644b970..fc1348193957 100644
--- a/arch/mips/include/asm/sn/intr.h
+++ b/arch/mips/include/asm/sn/intr.h
@@ -14,8 +14,8 @@
 #define INT_PEND0_BASELVL       0
 #define INT_PEND1_BASELVL       64
 
-#define N_INTPENDJUNK_BITS      8
-#define INTPENDJUNK_CLRBIT      0x80
+#define N_INTPENDJUNK_BITS      8
+#define INTPENDJUNK_CLRBIT      0x80
 
 /*
  * Macros to manipulate the interrupt register on the calling hub chip.
@@ -32,7 +32,7 @@
  * We do an uncached load of the int_pend0 register to ensure this.
  */
 
-#define LOCAL_HUB_CLR_INTR(level)                               \
+#define LOCAL_HUB_CLR_INTR(level)                               \
 do {                                                            \
         LOCAL_HUB_S(PI_INT_PEND_MOD, (level));                  \
         LOCAL_HUB_L(PI_INT_PEND0);                              \
@@ -40,7 +40,7 @@ do {								\
 
 #define REMOTE_HUB_CLR_INTR(hub, level)                         \
 do {                                                            \
-        nasid_t  __hub = (hub);                                 \
+        nasid_t  __hub = (hub);                                 \
                                                                 \
         REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));          \
         REMOTE_HUB_L(__hub, PI_INT_PEND0);                      \
@@ -102,8 +102,8 @@ do {								\
 #define LLP_PFAIL_INTR_A        41      /* see ml/SN/SN0/sysctlr.c */
 #define LLP_PFAIL_INTR_B        42
 
-#define TLB_INTR_A              43      /* used for tlb flush random */
-#define TLB_INTR_B              44
+#define TLB_INTR_A              43      /* used for tlb flush random */
+#define TLB_INTR_B              44
 
 #define IP27_INTR_0             45      /* Reserved for PROM use */
 #define IP27_INTR_1             46      /* do not use in Kernel */
@@ -116,8 +116,8 @@ do {								\
 
 #define BRIDGE_ERROR_INTR       53      /* Setup by PROM to catch       */
                                         /* Bridge Errors */
-#define DEBUG_INTR_A            54
-#define DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
+#define DEBUG_INTR_A            54
+#define DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
 #define IO_ERROR_INTR           57      /* Setup by PROM */
 #define CLK_ERR_INTR            58
 #define COR_ERR_INTR_A          59