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-rw-r--r--arch/mips/include/asm/octeon/cvmx-npi-defs.h1136
1 files changed, 1135 insertions, 1 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
index f089c780060f..129bb250e534 100644
--- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2012 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -152,8 +152,13 @@
152union cvmx_npi_base_addr_inputx { 152union cvmx_npi_base_addr_inputx {
153 uint64_t u64; 153 uint64_t u64;
154 struct cvmx_npi_base_addr_inputx_s { 154 struct cvmx_npi_base_addr_inputx_s {
155#ifdef __BIG_ENDIAN_BITFIELD
155 uint64_t baddr:61; 156 uint64_t baddr:61;
156 uint64_t reserved_0_2:3; 157 uint64_t reserved_0_2:3;
158#else
159 uint64_t reserved_0_2:3;
160 uint64_t baddr:61;
161#endif
157 } s; 162 } s;
158 struct cvmx_npi_base_addr_inputx_s cn30xx; 163 struct cvmx_npi_base_addr_inputx_s cn30xx;
159 struct cvmx_npi_base_addr_inputx_s cn31xx; 164 struct cvmx_npi_base_addr_inputx_s cn31xx;
@@ -167,8 +172,13 @@ union cvmx_npi_base_addr_inputx {
167union cvmx_npi_base_addr_outputx { 172union cvmx_npi_base_addr_outputx {
168 uint64_t u64; 173 uint64_t u64;
169 struct cvmx_npi_base_addr_outputx_s { 174 struct cvmx_npi_base_addr_outputx_s {
175#ifdef __BIG_ENDIAN_BITFIELD
170 uint64_t baddr:61; 176 uint64_t baddr:61;
171 uint64_t reserved_0_2:3; 177 uint64_t reserved_0_2:3;
178#else
179 uint64_t reserved_0_2:3;
180 uint64_t baddr:61;
181#endif
172 } s; 182 } s;
173 struct cvmx_npi_base_addr_outputx_s cn30xx; 183 struct cvmx_npi_base_addr_outputx_s cn30xx;
174 struct cvmx_npi_base_addr_outputx_s cn31xx; 184 struct cvmx_npi_base_addr_outputx_s cn31xx;
@@ -182,6 +192,7 @@ union cvmx_npi_base_addr_outputx {
182union cvmx_npi_bist_status { 192union cvmx_npi_bist_status {
183 uint64_t u64; 193 uint64_t u64;
184 struct cvmx_npi_bist_status_s { 194 struct cvmx_npi_bist_status_s {
195#ifdef __BIG_ENDIAN_BITFIELD
185 uint64_t reserved_20_63:44; 196 uint64_t reserved_20_63:44;
186 uint64_t csr_bs:1; 197 uint64_t csr_bs:1;
187 uint64_t dif_bs:1; 198 uint64_t dif_bs:1;
@@ -203,8 +214,32 @@ union cvmx_npi_bist_status {
203 uint64_t dob_bs:1; 214 uint64_t dob_bs:1;
204 uint64_t pdf_bs:1; 215 uint64_t pdf_bs:1;
205 uint64_t dpi_bs:1; 216 uint64_t dpi_bs:1;
217#else
218 uint64_t dpi_bs:1;
219 uint64_t pdf_bs:1;
220 uint64_t dob_bs:1;
221 uint64_t nus_bs:1;
222 uint64_t pos_bs:1;
223 uint64_t pof3_bs:1;
224 uint64_t pof2_bs:1;
225 uint64_t pof1_bs:1;
226 uint64_t pof0_bs:1;
227 uint64_t pig_bs:1;
228 uint64_t pgf_bs:1;
229 uint64_t rdnl_bs:1;
230 uint64_t pcad_bs:1;
231 uint64_t pcac_bs:1;
232 uint64_t rdn_bs:1;
233 uint64_t pcn_bs:1;
234 uint64_t pcnc_bs:1;
235 uint64_t rdp_bs:1;
236 uint64_t dif_bs:1;
237 uint64_t csr_bs:1;
238 uint64_t reserved_20_63:44;
239#endif
206 } s; 240 } s;
207 struct cvmx_npi_bist_status_cn30xx { 241 struct cvmx_npi_bist_status_cn30xx {
242#ifdef __BIG_ENDIAN_BITFIELD
208 uint64_t reserved_20_63:44; 243 uint64_t reserved_20_63:44;
209 uint64_t csr_bs:1; 244 uint64_t csr_bs:1;
210 uint64_t dif_bs:1; 245 uint64_t dif_bs:1;
@@ -224,11 +259,33 @@ union cvmx_npi_bist_status {
224 uint64_t dob_bs:1; 259 uint64_t dob_bs:1;
225 uint64_t pdf_bs:1; 260 uint64_t pdf_bs:1;
226 uint64_t dpi_bs:1; 261 uint64_t dpi_bs:1;
262#else
263 uint64_t dpi_bs:1;
264 uint64_t pdf_bs:1;
265 uint64_t dob_bs:1;
266 uint64_t nus_bs:1;
267 uint64_t pos_bs:1;
268 uint64_t reserved_5_7:3;
269 uint64_t pof0_bs:1;
270 uint64_t pig_bs:1;
271 uint64_t pgf_bs:1;
272 uint64_t rdnl_bs:1;
273 uint64_t pcad_bs:1;
274 uint64_t pcac_bs:1;
275 uint64_t rdn_bs:1;
276 uint64_t pcn_bs:1;
277 uint64_t pcnc_bs:1;
278 uint64_t rdp_bs:1;
279 uint64_t dif_bs:1;
280 uint64_t csr_bs:1;
281 uint64_t reserved_20_63:44;
282#endif
227 } cn30xx; 283 } cn30xx;
228 struct cvmx_npi_bist_status_s cn31xx; 284 struct cvmx_npi_bist_status_s cn31xx;
229 struct cvmx_npi_bist_status_s cn38xx; 285 struct cvmx_npi_bist_status_s cn38xx;
230 struct cvmx_npi_bist_status_s cn38xxp2; 286 struct cvmx_npi_bist_status_s cn38xxp2;
231 struct cvmx_npi_bist_status_cn50xx { 287 struct cvmx_npi_bist_status_cn50xx {
288#ifdef __BIG_ENDIAN_BITFIELD
232 uint64_t reserved_20_63:44; 289 uint64_t reserved_20_63:44;
233 uint64_t csr_bs:1; 290 uint64_t csr_bs:1;
234 uint64_t dif_bs:1; 291 uint64_t dif_bs:1;
@@ -249,6 +306,28 @@ union cvmx_npi_bist_status {
249 uint64_t dob_bs:1; 306 uint64_t dob_bs:1;
250 uint64_t pdf_bs:1; 307 uint64_t pdf_bs:1;
251 uint64_t dpi_bs:1; 308 uint64_t dpi_bs:1;
309#else
310 uint64_t dpi_bs:1;
311 uint64_t pdf_bs:1;
312 uint64_t dob_bs:1;
313 uint64_t nus_bs:1;
314 uint64_t pos_bs:1;
315 uint64_t reserved_5_6:2;
316 uint64_t pof1_bs:1;
317 uint64_t pof0_bs:1;
318 uint64_t pig_bs:1;
319 uint64_t pgf_bs:1;
320 uint64_t rdnl_bs:1;
321 uint64_t pcad_bs:1;
322 uint64_t pcac_bs:1;
323 uint64_t rdn_bs:1;
324 uint64_t pcn_bs:1;
325 uint64_t pcnc_bs:1;
326 uint64_t rdp_bs:1;
327 uint64_t dif_bs:1;
328 uint64_t csr_bs:1;
329 uint64_t reserved_20_63:44;
330#endif
252 } cn50xx; 331 } cn50xx;
253 struct cvmx_npi_bist_status_s cn58xx; 332 struct cvmx_npi_bist_status_s cn58xx;
254 struct cvmx_npi_bist_status_s cn58xxp1; 333 struct cvmx_npi_bist_status_s cn58xxp1;
@@ -257,9 +336,15 @@ union cvmx_npi_bist_status {
257union cvmx_npi_buff_size_outputx { 336union cvmx_npi_buff_size_outputx {
258 uint64_t u64; 337 uint64_t u64;
259 struct cvmx_npi_buff_size_outputx_s { 338 struct cvmx_npi_buff_size_outputx_s {
339#ifdef __BIG_ENDIAN_BITFIELD
260 uint64_t reserved_23_63:41; 340 uint64_t reserved_23_63:41;
261 uint64_t isize:7; 341 uint64_t isize:7;
262 uint64_t bsize:16; 342 uint64_t bsize:16;
343#else
344 uint64_t bsize:16;
345 uint64_t isize:7;
346 uint64_t reserved_23_63:41;
347#endif
263 } s; 348 } s;
264 struct cvmx_npi_buff_size_outputx_s cn30xx; 349 struct cvmx_npi_buff_size_outputx_s cn30xx;
265 struct cvmx_npi_buff_size_outputx_s cn31xx; 350 struct cvmx_npi_buff_size_outputx_s cn31xx;
@@ -273,9 +358,15 @@ union cvmx_npi_buff_size_outputx {
273union cvmx_npi_comp_ctl { 358union cvmx_npi_comp_ctl {
274 uint64_t u64; 359 uint64_t u64;
275 struct cvmx_npi_comp_ctl_s { 360 struct cvmx_npi_comp_ctl_s {
361#ifdef __BIG_ENDIAN_BITFIELD
276 uint64_t reserved_10_63:54; 362 uint64_t reserved_10_63:54;
277 uint64_t pctl:5; 363 uint64_t pctl:5;
278 uint64_t nctl:5; 364 uint64_t nctl:5;
365#else
366 uint64_t nctl:5;
367 uint64_t pctl:5;
368 uint64_t reserved_10_63:54;
369#endif
279 } s; 370 } s;
280 struct cvmx_npi_comp_ctl_s cn50xx; 371 struct cvmx_npi_comp_ctl_s cn50xx;
281 struct cvmx_npi_comp_ctl_s cn58xx; 372 struct cvmx_npi_comp_ctl_s cn58xx;
@@ -285,6 +376,7 @@ union cvmx_npi_comp_ctl {
285union cvmx_npi_ctl_status { 376union cvmx_npi_ctl_status {
286 uint64_t u64; 377 uint64_t u64;
287 struct cvmx_npi_ctl_status_s { 378 struct cvmx_npi_ctl_status_s {
379#ifdef __BIG_ENDIAN_BITFIELD
288 uint64_t reserved_63_63:1; 380 uint64_t reserved_63_63:1;
289 uint64_t chip_rev:8; 381 uint64_t chip_rev:8;
290 uint64_t dis_pniw:1; 382 uint64_t dis_pniw:1;
@@ -306,8 +398,32 @@ union cvmx_npi_ctl_status {
306 uint64_t max_word:5; 398 uint64_t max_word:5;
307 uint64_t reserved_10_31:22; 399 uint64_t reserved_10_31:22;
308 uint64_t timer:10; 400 uint64_t timer:10;
401#else
402 uint64_t timer:10;
403 uint64_t reserved_10_31:22;
404 uint64_t max_word:5;
405 uint64_t reserved_37_39:3;
406 uint64_t wait_com:1;
407 uint64_t pci_wdis:1;
408 uint64_t ins0_64b:1;
409 uint64_t ins1_64b:1;
410 uint64_t ins2_64b:1;
411 uint64_t ins3_64b:1;
412 uint64_t ins0_enb:1;
413 uint64_t ins1_enb:1;
414 uint64_t ins2_enb:1;
415 uint64_t ins3_enb:1;
416 uint64_t out0_enb:1;
417 uint64_t out1_enb:1;
418 uint64_t out2_enb:1;
419 uint64_t out3_enb:1;
420 uint64_t dis_pniw:1;
421 uint64_t chip_rev:8;
422 uint64_t reserved_63_63:1;
423#endif
309 } s; 424 } s;
310 struct cvmx_npi_ctl_status_cn30xx { 425 struct cvmx_npi_ctl_status_cn30xx {
426#ifdef __BIG_ENDIAN_BITFIELD
311 uint64_t reserved_63_63:1; 427 uint64_t reserved_63_63:1;
312 uint64_t chip_rev:8; 428 uint64_t chip_rev:8;
313 uint64_t dis_pniw:1; 429 uint64_t dis_pniw:1;
@@ -323,8 +439,26 @@ union cvmx_npi_ctl_status {
323 uint64_t max_word:5; 439 uint64_t max_word:5;
324 uint64_t reserved_10_31:22; 440 uint64_t reserved_10_31:22;
325 uint64_t timer:10; 441 uint64_t timer:10;
442#else
443 uint64_t timer:10;
444 uint64_t reserved_10_31:22;
445 uint64_t max_word:5;
446 uint64_t reserved_37_39:3;
447 uint64_t wait_com:1;
448 uint64_t pci_wdis:1;
449 uint64_t ins0_64b:1;
450 uint64_t reserved_43_45:3;
451 uint64_t ins0_enb:1;
452 uint64_t reserved_47_49:3;
453 uint64_t out0_enb:1;
454 uint64_t reserved_51_53:3;
455 uint64_t dis_pniw:1;
456 uint64_t chip_rev:8;
457 uint64_t reserved_63_63:1;
458#endif
326 } cn30xx; 459 } cn30xx;
327 struct cvmx_npi_ctl_status_cn31xx { 460 struct cvmx_npi_ctl_status_cn31xx {
461#ifdef __BIG_ENDIAN_BITFIELD
328 uint64_t reserved_63_63:1; 462 uint64_t reserved_63_63:1;
329 uint64_t chip_rev:8; 463 uint64_t chip_rev:8;
330 uint64_t dis_pniw:1; 464 uint64_t dis_pniw:1;
@@ -343,6 +477,26 @@ union cvmx_npi_ctl_status {
343 uint64_t max_word:5; 477 uint64_t max_word:5;
344 uint64_t reserved_10_31:22; 478 uint64_t reserved_10_31:22;
345 uint64_t timer:10; 479 uint64_t timer:10;
480#else
481 uint64_t timer:10;
482 uint64_t reserved_10_31:22;
483 uint64_t max_word:5;
484 uint64_t reserved_37_39:3;
485 uint64_t wait_com:1;
486 uint64_t pci_wdis:1;
487 uint64_t ins0_64b:1;
488 uint64_t ins1_64b:1;
489 uint64_t reserved_44_45:2;
490 uint64_t ins0_enb:1;
491 uint64_t ins1_enb:1;
492 uint64_t reserved_48_49:2;
493 uint64_t out0_enb:1;
494 uint64_t out1_enb:1;
495 uint64_t reserved_52_53:2;
496 uint64_t dis_pniw:1;
497 uint64_t chip_rev:8;
498 uint64_t reserved_63_63:1;
499#endif
346 } cn31xx; 500 } cn31xx;
347 struct cvmx_npi_ctl_status_s cn38xx; 501 struct cvmx_npi_ctl_status_s cn38xx;
348 struct cvmx_npi_ctl_status_s cn38xxp2; 502 struct cvmx_npi_ctl_status_s cn38xxp2;
@@ -354,8 +508,13 @@ union cvmx_npi_ctl_status {
354union cvmx_npi_dbg_select { 508union cvmx_npi_dbg_select {
355 uint64_t u64; 509 uint64_t u64;
356 struct cvmx_npi_dbg_select_s { 510 struct cvmx_npi_dbg_select_s {
511#ifdef __BIG_ENDIAN_BITFIELD
357 uint64_t reserved_16_63:48; 512 uint64_t reserved_16_63:48;
358 uint64_t dbg_sel:16; 513 uint64_t dbg_sel:16;
514#else
515 uint64_t dbg_sel:16;
516 uint64_t reserved_16_63:48;
517#endif
359 } s; 518 } s;
360 struct cvmx_npi_dbg_select_s cn30xx; 519 struct cvmx_npi_dbg_select_s cn30xx;
361 struct cvmx_npi_dbg_select_s cn31xx; 520 struct cvmx_npi_dbg_select_s cn31xx;
@@ -369,6 +528,7 @@ union cvmx_npi_dbg_select {
369union cvmx_npi_dma_control { 528union cvmx_npi_dma_control {
370 uint64_t u64; 529 uint64_t u64;
371 struct cvmx_npi_dma_control_s { 530 struct cvmx_npi_dma_control_s {
531#ifdef __BIG_ENDIAN_BITFIELD
372 uint64_t reserved_36_63:28; 532 uint64_t reserved_36_63:28;
373 uint64_t b0_lend:1; 533 uint64_t b0_lend:1;
374 uint64_t dwb_denb:1; 534 uint64_t dwb_denb:1;
@@ -382,6 +542,21 @@ union cvmx_npi_dma_control {
382 uint64_t hp_enb:1; 542 uint64_t hp_enb:1;
383 uint64_t lp_enb:1; 543 uint64_t lp_enb:1;
384 uint64_t csize:14; 544 uint64_t csize:14;
545#else
546 uint64_t csize:14;
547 uint64_t lp_enb:1;
548 uint64_t hp_enb:1;
549 uint64_t o_mode:1;
550 uint64_t o_es:2;
551 uint64_t o_ns:1;
552 uint64_t o_ro:1;
553 uint64_t o_add1:1;
554 uint64_t fpa_que:3;
555 uint64_t dwb_ichk:9;
556 uint64_t dwb_denb:1;
557 uint64_t b0_lend:1;
558 uint64_t reserved_36_63:28;
559#endif
385 } s; 560 } s;
386 struct cvmx_npi_dma_control_s cn30xx; 561 struct cvmx_npi_dma_control_s cn30xx;
387 struct cvmx_npi_dma_control_s cn31xx; 562 struct cvmx_npi_dma_control_s cn31xx;
@@ -395,9 +570,15 @@ union cvmx_npi_dma_control {
395union cvmx_npi_dma_highp_counts { 570union cvmx_npi_dma_highp_counts {
396 uint64_t u64; 571 uint64_t u64;
397 struct cvmx_npi_dma_highp_counts_s { 572 struct cvmx_npi_dma_highp_counts_s {
573#ifdef __BIG_ENDIAN_BITFIELD
398 uint64_t reserved_39_63:25; 574 uint64_t reserved_39_63:25;
399 uint64_t fcnt:7; 575 uint64_t fcnt:7;
400 uint64_t dbell:32; 576 uint64_t dbell:32;
577#else
578 uint64_t dbell:32;
579 uint64_t fcnt:7;
580 uint64_t reserved_39_63:25;
581#endif
401 } s; 582 } s;
402 struct cvmx_npi_dma_highp_counts_s cn30xx; 583 struct cvmx_npi_dma_highp_counts_s cn30xx;
403 struct cvmx_npi_dma_highp_counts_s cn31xx; 584 struct cvmx_npi_dma_highp_counts_s cn31xx;
@@ -411,9 +592,15 @@ union cvmx_npi_dma_highp_counts {
411union cvmx_npi_dma_highp_naddr { 592union cvmx_npi_dma_highp_naddr {
412 uint64_t u64; 593 uint64_t u64;
413 struct cvmx_npi_dma_highp_naddr_s { 594 struct cvmx_npi_dma_highp_naddr_s {
595#ifdef __BIG_ENDIAN_BITFIELD
414 uint64_t reserved_40_63:24; 596 uint64_t reserved_40_63:24;
415 uint64_t state:4; 597 uint64_t state:4;
416 uint64_t addr:36; 598 uint64_t addr:36;
599#else
600 uint64_t addr:36;
601 uint64_t state:4;
602 uint64_t reserved_40_63:24;
603#endif
417 } s; 604 } s;
418 struct cvmx_npi_dma_highp_naddr_s cn30xx; 605 struct cvmx_npi_dma_highp_naddr_s cn30xx;
419 struct cvmx_npi_dma_highp_naddr_s cn31xx; 606 struct cvmx_npi_dma_highp_naddr_s cn31xx;
@@ -427,9 +614,15 @@ union cvmx_npi_dma_highp_naddr {
427union cvmx_npi_dma_lowp_counts { 614union cvmx_npi_dma_lowp_counts {
428 uint64_t u64; 615 uint64_t u64;
429 struct cvmx_npi_dma_lowp_counts_s { 616 struct cvmx_npi_dma_lowp_counts_s {
617#ifdef __BIG_ENDIAN_BITFIELD
430 uint64_t reserved_39_63:25; 618 uint64_t reserved_39_63:25;
431 uint64_t fcnt:7; 619 uint64_t fcnt:7;
432 uint64_t dbell:32; 620 uint64_t dbell:32;
621#else
622 uint64_t dbell:32;
623 uint64_t fcnt:7;
624 uint64_t reserved_39_63:25;
625#endif
433 } s; 626 } s;
434 struct cvmx_npi_dma_lowp_counts_s cn30xx; 627 struct cvmx_npi_dma_lowp_counts_s cn30xx;
435 struct cvmx_npi_dma_lowp_counts_s cn31xx; 628 struct cvmx_npi_dma_lowp_counts_s cn31xx;
@@ -443,9 +636,15 @@ union cvmx_npi_dma_lowp_counts {
443union cvmx_npi_dma_lowp_naddr { 636union cvmx_npi_dma_lowp_naddr {
444 uint64_t u64; 637 uint64_t u64;
445 struct cvmx_npi_dma_lowp_naddr_s { 638 struct cvmx_npi_dma_lowp_naddr_s {
639#ifdef __BIG_ENDIAN_BITFIELD
446 uint64_t reserved_40_63:24; 640 uint64_t reserved_40_63:24;
447 uint64_t state:4; 641 uint64_t state:4;
448 uint64_t addr:36; 642 uint64_t addr:36;
643#else
644 uint64_t addr:36;
645 uint64_t state:4;
646 uint64_t reserved_40_63:24;
647#endif
449 } s; 648 } s;
450 struct cvmx_npi_dma_lowp_naddr_s cn30xx; 649 struct cvmx_npi_dma_lowp_naddr_s cn30xx;
451 struct cvmx_npi_dma_lowp_naddr_s cn31xx; 650 struct cvmx_npi_dma_lowp_naddr_s cn31xx;
@@ -459,8 +658,13 @@ union cvmx_npi_dma_lowp_naddr {
459union cvmx_npi_highp_dbell { 658union cvmx_npi_highp_dbell {
460 uint64_t u64; 659 uint64_t u64;
461 struct cvmx_npi_highp_dbell_s { 660 struct cvmx_npi_highp_dbell_s {
661#ifdef __BIG_ENDIAN_BITFIELD
462 uint64_t reserved_16_63:48; 662 uint64_t reserved_16_63:48;
463 uint64_t dbell:16; 663 uint64_t dbell:16;
664#else
665 uint64_t dbell:16;
666 uint64_t reserved_16_63:48;
667#endif
464 } s; 668 } s;
465 struct cvmx_npi_highp_dbell_s cn30xx; 669 struct cvmx_npi_highp_dbell_s cn30xx;
466 struct cvmx_npi_highp_dbell_s cn31xx; 670 struct cvmx_npi_highp_dbell_s cn31xx;
@@ -474,8 +678,13 @@ union cvmx_npi_highp_dbell {
474union cvmx_npi_highp_ibuff_saddr { 678union cvmx_npi_highp_ibuff_saddr {
475 uint64_t u64; 679 uint64_t u64;
476 struct cvmx_npi_highp_ibuff_saddr_s { 680 struct cvmx_npi_highp_ibuff_saddr_s {
681#ifdef __BIG_ENDIAN_BITFIELD
477 uint64_t reserved_36_63:28; 682 uint64_t reserved_36_63:28;
478 uint64_t saddr:36; 683 uint64_t saddr:36;
684#else
685 uint64_t saddr:36;
686 uint64_t reserved_36_63:28;
687#endif
479 } s; 688 } s;
480 struct cvmx_npi_highp_ibuff_saddr_s cn30xx; 689 struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
481 struct cvmx_npi_highp_ibuff_saddr_s cn31xx; 690 struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
@@ -489,6 +698,7 @@ union cvmx_npi_highp_ibuff_saddr {
489union cvmx_npi_input_control { 698union cvmx_npi_input_control {
490 uint64_t u64; 699 uint64_t u64;
491 struct cvmx_npi_input_control_s { 700 struct cvmx_npi_input_control_s {
701#ifdef __BIG_ENDIAN_BITFIELD
492 uint64_t reserved_23_63:41; 702 uint64_t reserved_23_63:41;
493 uint64_t pkt_rr:1; 703 uint64_t pkt_rr:1;
494 uint64_t pbp_dhi:13; 704 uint64_t pbp_dhi:13;
@@ -499,8 +709,21 @@ union cvmx_npi_input_control {
499 uint64_t nsr:1; 709 uint64_t nsr:1;
500 uint64_t esr:2; 710 uint64_t esr:2;
501 uint64_t ror:1; 711 uint64_t ror:1;
712#else
713 uint64_t ror:1;
714 uint64_t esr:2;
715 uint64_t nsr:1;
716 uint64_t use_csr:1;
717 uint64_t d_ror:1;
718 uint64_t d_esr:2;
719 uint64_t d_nsr:1;
720 uint64_t pbp_dhi:13;
721 uint64_t pkt_rr:1;
722 uint64_t reserved_23_63:41;
723#endif
502 } s; 724 } s;
503 struct cvmx_npi_input_control_cn30xx { 725 struct cvmx_npi_input_control_cn30xx {
726#ifdef __BIG_ENDIAN_BITFIELD
504 uint64_t reserved_22_63:42; 727 uint64_t reserved_22_63:42;
505 uint64_t pbp_dhi:13; 728 uint64_t pbp_dhi:13;
506 uint64_t d_nsr:1; 729 uint64_t d_nsr:1;
@@ -510,6 +733,17 @@ union cvmx_npi_input_control {
510 uint64_t nsr:1; 733 uint64_t nsr:1;
511 uint64_t esr:2; 734 uint64_t esr:2;
512 uint64_t ror:1; 735 uint64_t ror:1;
736#else
737 uint64_t ror:1;
738 uint64_t esr:2;
739 uint64_t nsr:1;
740 uint64_t use_csr:1;
741 uint64_t d_ror:1;
742 uint64_t d_esr:2;
743 uint64_t d_nsr:1;
744 uint64_t pbp_dhi:13;
745 uint64_t reserved_22_63:42;
746#endif
513 } cn30xx; 747 } cn30xx;
514 struct cvmx_npi_input_control_cn30xx cn31xx; 748 struct cvmx_npi_input_control_cn30xx cn31xx;
515 struct cvmx_npi_input_control_s cn38xx; 749 struct cvmx_npi_input_control_s cn38xx;
@@ -522,6 +756,7 @@ union cvmx_npi_input_control {
522union cvmx_npi_int_enb { 756union cvmx_npi_int_enb {
523 uint64_t u64; 757 uint64_t u64;
524 struct cvmx_npi_int_enb_s { 758 struct cvmx_npi_int_enb_s {
759#ifdef __BIG_ENDIAN_BITFIELD
525 uint64_t reserved_62_63:2; 760 uint64_t reserved_62_63:2;
526 uint64_t q1_a_f:1; 761 uint64_t q1_a_f:1;
527 uint64_t q1_s_e:1; 762 uint64_t q1_s_e:1;
@@ -585,8 +820,74 @@ union cvmx_npi_int_enb {
585 uint64_t pci_rsl:1; 820 uint64_t pci_rsl:1;
586 uint64_t rml_wto:1; 821 uint64_t rml_wto:1;
587 uint64_t rml_rto:1; 822 uint64_t rml_rto:1;
823#else
824 uint64_t rml_rto:1;
825 uint64_t rml_wto:1;
826 uint64_t pci_rsl:1;
827 uint64_t po0_2sml:1;
828 uint64_t po1_2sml:1;
829 uint64_t po2_2sml:1;
830 uint64_t po3_2sml:1;
831 uint64_t i0_rtout:1;
832 uint64_t i1_rtout:1;
833 uint64_t i2_rtout:1;
834 uint64_t i3_rtout:1;
835 uint64_t i0_overf:1;
836 uint64_t i1_overf:1;
837 uint64_t i2_overf:1;
838 uint64_t i3_overf:1;
839 uint64_t p0_rtout:1;
840 uint64_t p1_rtout:1;
841 uint64_t p2_rtout:1;
842 uint64_t p3_rtout:1;
843 uint64_t p0_perr:1;
844 uint64_t p1_perr:1;
845 uint64_t p2_perr:1;
846 uint64_t p3_perr:1;
847 uint64_t g0_rtout:1;
848 uint64_t g1_rtout:1;
849 uint64_t g2_rtout:1;
850 uint64_t g3_rtout:1;
851 uint64_t p0_pperr:1;
852 uint64_t p1_pperr:1;
853 uint64_t p2_pperr:1;
854 uint64_t p3_pperr:1;
855 uint64_t p0_ptout:1;
856 uint64_t p1_ptout:1;
857 uint64_t p2_ptout:1;
858 uint64_t p3_ptout:1;
859 uint64_t i0_pperr:1;
860 uint64_t i1_pperr:1;
861 uint64_t i2_pperr:1;
862 uint64_t i3_pperr:1;
863 uint64_t win_rto:1;
864 uint64_t p_dperr:1;
865 uint64_t iobdma:1;
866 uint64_t fcr_s_e:1;
867 uint64_t fcr_a_f:1;
868 uint64_t pcr_s_e:1;
869 uint64_t pcr_a_f:1;
870 uint64_t q2_s_e:1;
871 uint64_t q2_a_f:1;
872 uint64_t q3_s_e:1;
873 uint64_t q3_a_f:1;
874 uint64_t com_s_e:1;
875 uint64_t com_a_f:1;
876 uint64_t pnc_s_e:1;
877 uint64_t pnc_a_f:1;
878 uint64_t rwx_s_e:1;
879 uint64_t rdx_s_e:1;
880 uint64_t pcf_p_e:1;
881 uint64_t pcf_p_f:1;
882 uint64_t pdf_p_e:1;
883 uint64_t pdf_p_f:1;
884 uint64_t q1_s_e:1;
885 uint64_t q1_a_f:1;
886 uint64_t reserved_62_63:2;
887#endif
588 } s; 888 } s;
589 struct cvmx_npi_int_enb_cn30xx { 889 struct cvmx_npi_int_enb_cn30xx {
890#ifdef __BIG_ENDIAN_BITFIELD
590 uint64_t reserved_62_63:2; 891 uint64_t reserved_62_63:2;
591 uint64_t q1_a_f:1; 892 uint64_t q1_a_f:1;
592 uint64_t q1_s_e:1; 893 uint64_t q1_s_e:1;
@@ -632,8 +933,56 @@ union cvmx_npi_int_enb {
632 uint64_t pci_rsl:1; 933 uint64_t pci_rsl:1;
633 uint64_t rml_wto:1; 934 uint64_t rml_wto:1;
634 uint64_t rml_rto:1; 935 uint64_t rml_rto:1;
936#else
937 uint64_t rml_rto:1;
938 uint64_t rml_wto:1;
939 uint64_t pci_rsl:1;
940 uint64_t po0_2sml:1;
941 uint64_t reserved_4_6:3;
942 uint64_t i0_rtout:1;
943 uint64_t reserved_8_10:3;
944 uint64_t i0_overf:1;
945 uint64_t reserved_12_14:3;
946 uint64_t p0_rtout:1;
947 uint64_t reserved_16_18:3;
948 uint64_t p0_perr:1;
949 uint64_t reserved_20_22:3;
950 uint64_t g0_rtout:1;
951 uint64_t reserved_24_26:3;
952 uint64_t p0_pperr:1;
953 uint64_t reserved_28_30:3;
954 uint64_t p0_ptout:1;
955 uint64_t reserved_32_34:3;
956 uint64_t i0_pperr:1;
957 uint64_t reserved_36_38:3;
958 uint64_t win_rto:1;
959 uint64_t p_dperr:1;
960 uint64_t iobdma:1;
961 uint64_t fcr_s_e:1;
962 uint64_t fcr_a_f:1;
963 uint64_t pcr_s_e:1;
964 uint64_t pcr_a_f:1;
965 uint64_t q2_s_e:1;
966 uint64_t q2_a_f:1;
967 uint64_t q3_s_e:1;
968 uint64_t q3_a_f:1;
969 uint64_t com_s_e:1;
970 uint64_t com_a_f:1;
971 uint64_t pnc_s_e:1;
972 uint64_t pnc_a_f:1;
973 uint64_t rwx_s_e:1;
974 uint64_t rdx_s_e:1;
975 uint64_t pcf_p_e:1;
976 uint64_t pcf_p_f:1;
977 uint64_t pdf_p_e:1;
978 uint64_t pdf_p_f:1;
979 uint64_t q1_s_e:1;
980 uint64_t q1_a_f:1;
981 uint64_t reserved_62_63:2;
982#endif
635 } cn30xx; 983 } cn30xx;
636 struct cvmx_npi_int_enb_cn31xx { 984 struct cvmx_npi_int_enb_cn31xx {
985#ifdef __BIG_ENDIAN_BITFIELD
637 uint64_t reserved_62_63:2; 986 uint64_t reserved_62_63:2;
638 uint64_t q1_a_f:1; 987 uint64_t q1_a_f:1;
639 uint64_t q1_s_e:1; 988 uint64_t q1_s_e:1;
@@ -688,9 +1037,66 @@ union cvmx_npi_int_enb {
688 uint64_t pci_rsl:1; 1037 uint64_t pci_rsl:1;
689 uint64_t rml_wto:1; 1038 uint64_t rml_wto:1;
690 uint64_t rml_rto:1; 1039 uint64_t rml_rto:1;
1040#else
1041 uint64_t rml_rto:1;
1042 uint64_t rml_wto:1;
1043 uint64_t pci_rsl:1;
1044 uint64_t po0_2sml:1;
1045 uint64_t po1_2sml:1;
1046 uint64_t reserved_5_6:2;
1047 uint64_t i0_rtout:1;
1048 uint64_t i1_rtout:1;
1049 uint64_t reserved_9_10:2;
1050 uint64_t i0_overf:1;
1051 uint64_t i1_overf:1;
1052 uint64_t reserved_13_14:2;
1053 uint64_t p0_rtout:1;
1054 uint64_t p1_rtout:1;
1055 uint64_t reserved_17_18:2;
1056 uint64_t p0_perr:1;
1057 uint64_t p1_perr:1;
1058 uint64_t reserved_21_22:2;
1059 uint64_t g0_rtout:1;
1060 uint64_t g1_rtout:1;
1061 uint64_t reserved_25_26:2;
1062 uint64_t p0_pperr:1;
1063 uint64_t p1_pperr:1;
1064 uint64_t reserved_29_30:2;
1065 uint64_t p0_ptout:1;
1066 uint64_t p1_ptout:1;
1067 uint64_t reserved_33_34:2;
1068 uint64_t i0_pperr:1;
1069 uint64_t i1_pperr:1;
1070 uint64_t reserved_37_38:2;
1071 uint64_t win_rto:1;
1072 uint64_t p_dperr:1;
1073 uint64_t iobdma:1;
1074 uint64_t fcr_s_e:1;
1075 uint64_t fcr_a_f:1;
1076 uint64_t pcr_s_e:1;
1077 uint64_t pcr_a_f:1;
1078 uint64_t q2_s_e:1;
1079 uint64_t q2_a_f:1;
1080 uint64_t q3_s_e:1;
1081 uint64_t q3_a_f:1;
1082 uint64_t com_s_e:1;
1083 uint64_t com_a_f:1;
1084 uint64_t pnc_s_e:1;
1085 uint64_t pnc_a_f:1;
1086 uint64_t rwx_s_e:1;
1087 uint64_t rdx_s_e:1;
1088 uint64_t pcf_p_e:1;
1089 uint64_t pcf_p_f:1;
1090 uint64_t pdf_p_e:1;
1091 uint64_t pdf_p_f:1;
1092 uint64_t q1_s_e:1;
1093 uint64_t q1_a_f:1;
1094 uint64_t reserved_62_63:2;
1095#endif
691 } cn31xx; 1096 } cn31xx;
692 struct cvmx_npi_int_enb_s cn38xx; 1097 struct cvmx_npi_int_enb_s cn38xx;
693 struct cvmx_npi_int_enb_cn38xxp2 { 1098 struct cvmx_npi_int_enb_cn38xxp2 {
1099#ifdef __BIG_ENDIAN_BITFIELD
694 uint64_t reserved_42_63:22; 1100 uint64_t reserved_42_63:22;
695 uint64_t iobdma:1; 1101 uint64_t iobdma:1;
696 uint64_t p_dperr:1; 1102 uint64_t p_dperr:1;
@@ -734,6 +1140,51 @@ union cvmx_npi_int_enb {
734 uint64_t pci_rsl:1; 1140 uint64_t pci_rsl:1;
735 uint64_t rml_wto:1; 1141 uint64_t rml_wto:1;
736 uint64_t rml_rto:1; 1142 uint64_t rml_rto:1;
1143#else
1144 uint64_t rml_rto:1;
1145 uint64_t rml_wto:1;
1146 uint64_t pci_rsl:1;
1147 uint64_t po0_2sml:1;
1148 uint64_t po1_2sml:1;
1149 uint64_t po2_2sml:1;
1150 uint64_t po3_2sml:1;
1151 uint64_t i0_rtout:1;
1152 uint64_t i1_rtout:1;
1153 uint64_t i2_rtout:1;
1154 uint64_t i3_rtout:1;
1155 uint64_t i0_overf:1;
1156 uint64_t i1_overf:1;
1157 uint64_t i2_overf:1;
1158 uint64_t i3_overf:1;
1159 uint64_t p0_rtout:1;
1160 uint64_t p1_rtout:1;
1161 uint64_t p2_rtout:1;
1162 uint64_t p3_rtout:1;
1163 uint64_t p0_perr:1;
1164 uint64_t p1_perr:1;
1165 uint64_t p2_perr:1;
1166 uint64_t p3_perr:1;
1167 uint64_t g0_rtout:1;
1168 uint64_t g1_rtout:1;
1169 uint64_t g2_rtout:1;
1170 uint64_t g3_rtout:1;
1171 uint64_t p0_pperr:1;
1172 uint64_t p1_pperr:1;
1173 uint64_t p2_pperr:1;
1174 uint64_t p3_pperr:1;
1175 uint64_t p0_ptout:1;
1176 uint64_t p1_ptout:1;
1177 uint64_t p2_ptout:1;
1178 uint64_t p3_ptout:1;
1179 uint64_t i0_pperr:1;
1180 uint64_t i1_pperr:1;
1181 uint64_t i2_pperr:1;
1182 uint64_t i3_pperr:1;
1183 uint64_t win_rto:1;
1184 uint64_t p_dperr:1;
1185 uint64_t iobdma:1;
1186 uint64_t reserved_42_63:22;
1187#endif
737 } cn38xxp2; 1188 } cn38xxp2;
738 struct cvmx_npi_int_enb_cn31xx cn50xx; 1189 struct cvmx_npi_int_enb_cn31xx cn50xx;
739 struct cvmx_npi_int_enb_s cn58xx; 1190 struct cvmx_npi_int_enb_s cn58xx;
@@ -743,6 +1194,7 @@ union cvmx_npi_int_enb {
743union cvmx_npi_int_sum { 1194union cvmx_npi_int_sum {
744 uint64_t u64; 1195 uint64_t u64;
745 struct cvmx_npi_int_sum_s { 1196 struct cvmx_npi_int_sum_s {
1197#ifdef __BIG_ENDIAN_BITFIELD
746 uint64_t reserved_62_63:2; 1198 uint64_t reserved_62_63:2;
747 uint64_t q1_a_f:1; 1199 uint64_t q1_a_f:1;
748 uint64_t q1_s_e:1; 1200 uint64_t q1_s_e:1;
@@ -806,8 +1258,74 @@ union cvmx_npi_int_sum {
806 uint64_t pci_rsl:1; 1258 uint64_t pci_rsl:1;
807 uint64_t rml_wto:1; 1259 uint64_t rml_wto:1;
808 uint64_t rml_rto:1; 1260 uint64_t rml_rto:1;
1261#else
1262 uint64_t rml_rto:1;
1263 uint64_t rml_wto:1;
1264 uint64_t pci_rsl:1;
1265 uint64_t po0_2sml:1;
1266 uint64_t po1_2sml:1;
1267 uint64_t po2_2sml:1;
1268 uint64_t po3_2sml:1;
1269 uint64_t i0_rtout:1;
1270 uint64_t i1_rtout:1;
1271 uint64_t i2_rtout:1;
1272 uint64_t i3_rtout:1;
1273 uint64_t i0_overf:1;
1274 uint64_t i1_overf:1;
1275 uint64_t i2_overf:1;
1276 uint64_t i3_overf:1;
1277 uint64_t p0_rtout:1;
1278 uint64_t p1_rtout:1;
1279 uint64_t p2_rtout:1;
1280 uint64_t p3_rtout:1;
1281 uint64_t p0_perr:1;
1282 uint64_t p1_perr:1;
1283 uint64_t p2_perr:1;
1284 uint64_t p3_perr:1;
1285 uint64_t g0_rtout:1;
1286 uint64_t g1_rtout:1;
1287 uint64_t g2_rtout:1;
1288 uint64_t g3_rtout:1;
1289 uint64_t p0_pperr:1;
1290 uint64_t p1_pperr:1;
1291 uint64_t p2_pperr:1;
1292 uint64_t p3_pperr:1;
1293 uint64_t p0_ptout:1;
1294 uint64_t p1_ptout:1;
1295 uint64_t p2_ptout:1;
1296 uint64_t p3_ptout:1;
1297 uint64_t i0_pperr:1;
1298 uint64_t i1_pperr:1;
1299 uint64_t i2_pperr:1;
1300 uint64_t i3_pperr:1;
1301 uint64_t win_rto:1;
1302 uint64_t p_dperr:1;
1303 uint64_t iobdma:1;
1304 uint64_t fcr_s_e:1;
1305 uint64_t fcr_a_f:1;
1306 uint64_t pcr_s_e:1;
1307 uint64_t pcr_a_f:1;
1308 uint64_t q2_s_e:1;
1309 uint64_t q2_a_f:1;
1310 uint64_t q3_s_e:1;
1311 uint64_t q3_a_f:1;
1312 uint64_t com_s_e:1;
1313 uint64_t com_a_f:1;
1314 uint64_t pnc_s_e:1;
1315 uint64_t pnc_a_f:1;
1316 uint64_t rwx_s_e:1;
1317 uint64_t rdx_s_e:1;
1318 uint64_t pcf_p_e:1;
1319 uint64_t pcf_p_f:1;
1320 uint64_t pdf_p_e:1;
1321 uint64_t pdf_p_f:1;
1322 uint64_t q1_s_e:1;
1323 uint64_t q1_a_f:1;
1324 uint64_t reserved_62_63:2;
1325#endif
809 } s; 1326 } s;
810 struct cvmx_npi_int_sum_cn30xx { 1327 struct cvmx_npi_int_sum_cn30xx {
1328#ifdef __BIG_ENDIAN_BITFIELD
811 uint64_t reserved_62_63:2; 1329 uint64_t reserved_62_63:2;
812 uint64_t q1_a_f:1; 1330 uint64_t q1_a_f:1;
813 uint64_t q1_s_e:1; 1331 uint64_t q1_s_e:1;
@@ -853,8 +1371,56 @@ union cvmx_npi_int_sum {
853 uint64_t pci_rsl:1; 1371 uint64_t pci_rsl:1;
854 uint64_t rml_wto:1; 1372 uint64_t rml_wto:1;
855 uint64_t rml_rto:1; 1373 uint64_t rml_rto:1;
1374#else
1375 uint64_t rml_rto:1;
1376 uint64_t rml_wto:1;
1377 uint64_t pci_rsl:1;
1378 uint64_t po0_2sml:1;
1379 uint64_t reserved_4_6:3;
1380 uint64_t i0_rtout:1;
1381 uint64_t reserved_8_10:3;
1382 uint64_t i0_overf:1;
1383 uint64_t reserved_12_14:3;
1384 uint64_t p0_rtout:1;
1385 uint64_t reserved_16_18:3;
1386 uint64_t p0_perr:1;
1387 uint64_t reserved_20_22:3;
1388 uint64_t g0_rtout:1;
1389 uint64_t reserved_24_26:3;
1390 uint64_t p0_pperr:1;
1391 uint64_t reserved_28_30:3;
1392 uint64_t p0_ptout:1;
1393 uint64_t reserved_32_34:3;
1394 uint64_t i0_pperr:1;
1395 uint64_t reserved_36_38:3;
1396 uint64_t win_rto:1;
1397 uint64_t p_dperr:1;
1398 uint64_t iobdma:1;
1399 uint64_t fcr_s_e:1;
1400 uint64_t fcr_a_f:1;
1401 uint64_t pcr_s_e:1;
1402 uint64_t pcr_a_f:1;
1403 uint64_t q2_s_e:1;
1404 uint64_t q2_a_f:1;
1405 uint64_t q3_s_e:1;
1406 uint64_t q3_a_f:1;
1407 uint64_t com_s_e:1;
1408 uint64_t com_a_f:1;
1409 uint64_t pnc_s_e:1;
1410 uint64_t pnc_a_f:1;
1411 uint64_t rwx_s_e:1;
1412 uint64_t rdx_s_e:1;
1413 uint64_t pcf_p_e:1;
1414 uint64_t pcf_p_f:1;
1415 uint64_t pdf_p_e:1;
1416 uint64_t pdf_p_f:1;
1417 uint64_t q1_s_e:1;
1418 uint64_t q1_a_f:1;
1419 uint64_t reserved_62_63:2;
1420#endif
856 } cn30xx; 1421 } cn30xx;
857 struct cvmx_npi_int_sum_cn31xx { 1422 struct cvmx_npi_int_sum_cn31xx {
1423#ifdef __BIG_ENDIAN_BITFIELD
858 uint64_t reserved_62_63:2; 1424 uint64_t reserved_62_63:2;
859 uint64_t q1_a_f:1; 1425 uint64_t q1_a_f:1;
860 uint64_t q1_s_e:1; 1426 uint64_t q1_s_e:1;
@@ -909,9 +1475,66 @@ union cvmx_npi_int_sum {
909 uint64_t pci_rsl:1; 1475 uint64_t pci_rsl:1;
910 uint64_t rml_wto:1; 1476 uint64_t rml_wto:1;
911 uint64_t rml_rto:1; 1477 uint64_t rml_rto:1;
1478#else
1479 uint64_t rml_rto:1;
1480 uint64_t rml_wto:1;
1481 uint64_t pci_rsl:1;
1482 uint64_t po0_2sml:1;
1483 uint64_t po1_2sml:1;
1484 uint64_t reserved_5_6:2;
1485 uint64_t i0_rtout:1;
1486 uint64_t i1_rtout:1;
1487 uint64_t reserved_9_10:2;
1488 uint64_t i0_overf:1;
1489 uint64_t i1_overf:1;
1490 uint64_t reserved_13_14:2;
1491 uint64_t p0_rtout:1;
1492 uint64_t p1_rtout:1;
1493 uint64_t reserved_17_18:2;
1494 uint64_t p0_perr:1;
1495 uint64_t p1_perr:1;
1496 uint64_t reserved_21_22:2;
1497 uint64_t g0_rtout:1;
1498 uint64_t g1_rtout:1;
1499 uint64_t reserved_25_26:2;
1500 uint64_t p0_pperr:1;
1501 uint64_t p1_pperr:1;
1502 uint64_t reserved_29_30:2;
1503 uint64_t p0_ptout:1;
1504 uint64_t p1_ptout:1;
1505 uint64_t reserved_33_34:2;
1506 uint64_t i0_pperr:1;
1507 uint64_t i1_pperr:1;
1508 uint64_t reserved_37_38:2;
1509 uint64_t win_rto:1;
1510 uint64_t p_dperr:1;
1511 uint64_t iobdma:1;
1512 uint64_t fcr_s_e:1;
1513 uint64_t fcr_a_f:1;
1514 uint64_t pcr_s_e:1;
1515 uint64_t pcr_a_f:1;
1516 uint64_t q2_s_e:1;
1517 uint64_t q2_a_f:1;
1518 uint64_t q3_s_e:1;
1519 uint64_t q3_a_f:1;
1520 uint64_t com_s_e:1;
1521 uint64_t com_a_f:1;
1522 uint64_t pnc_s_e:1;
1523 uint64_t pnc_a_f:1;
1524 uint64_t rwx_s_e:1;
1525 uint64_t rdx_s_e:1;
1526 uint64_t pcf_p_e:1;
1527 uint64_t pcf_p_f:1;
1528 uint64_t pdf_p_e:1;
1529 uint64_t pdf_p_f:1;
1530 uint64_t q1_s_e:1;
1531 uint64_t q1_a_f:1;
1532 uint64_t reserved_62_63:2;
1533#endif
912 } cn31xx; 1534 } cn31xx;
913 struct cvmx_npi_int_sum_s cn38xx; 1535 struct cvmx_npi_int_sum_s cn38xx;
914 struct cvmx_npi_int_sum_cn38xxp2 { 1536 struct cvmx_npi_int_sum_cn38xxp2 {
1537#ifdef __BIG_ENDIAN_BITFIELD
915 uint64_t reserved_42_63:22; 1538 uint64_t reserved_42_63:22;
916 uint64_t iobdma:1; 1539 uint64_t iobdma:1;
917 uint64_t p_dperr:1; 1540 uint64_t p_dperr:1;
@@ -955,6 +1578,51 @@ union cvmx_npi_int_sum {
955 uint64_t pci_rsl:1; 1578 uint64_t pci_rsl:1;
956 uint64_t rml_wto:1; 1579 uint64_t rml_wto:1;
957 uint64_t rml_rto:1; 1580 uint64_t rml_rto:1;
1581#else
1582 uint64_t rml_rto:1;
1583 uint64_t rml_wto:1;
1584 uint64_t pci_rsl:1;
1585 uint64_t po0_2sml:1;
1586 uint64_t po1_2sml:1;
1587 uint64_t po2_2sml:1;
1588 uint64_t po3_2sml:1;
1589 uint64_t i0_rtout:1;
1590 uint64_t i1_rtout:1;
1591 uint64_t i2_rtout:1;
1592 uint64_t i3_rtout:1;
1593 uint64_t i0_overf:1;
1594 uint64_t i1_overf:1;
1595 uint64_t i2_overf:1;
1596 uint64_t i3_overf:1;
1597 uint64_t p0_rtout:1;
1598 uint64_t p1_rtout:1;
1599 uint64_t p2_rtout:1;
1600 uint64_t p3_rtout:1;
1601 uint64_t p0_perr:1;
1602 uint64_t p1_perr:1;
1603 uint64_t p2_perr:1;
1604 uint64_t p3_perr:1;
1605 uint64_t g0_rtout:1;
1606 uint64_t g1_rtout:1;
1607 uint64_t g2_rtout:1;
1608 uint64_t g3_rtout:1;
1609 uint64_t p0_pperr:1;
1610 uint64_t p1_pperr:1;
1611 uint64_t p2_pperr:1;
1612 uint64_t p3_pperr:1;
1613 uint64_t p0_ptout:1;
1614 uint64_t p1_ptout:1;
1615 uint64_t p2_ptout:1;
1616 uint64_t p3_ptout:1;
1617 uint64_t i0_pperr:1;
1618 uint64_t i1_pperr:1;
1619 uint64_t i2_pperr:1;
1620 uint64_t i3_pperr:1;
1621 uint64_t win_rto:1;
1622 uint64_t p_dperr:1;
1623 uint64_t iobdma:1;
1624 uint64_t reserved_42_63:22;
1625#endif
958 } cn38xxp2; 1626 } cn38xxp2;
959 struct cvmx_npi_int_sum_cn31xx cn50xx; 1627 struct cvmx_npi_int_sum_cn31xx cn50xx;
960 struct cvmx_npi_int_sum_s cn58xx; 1628 struct cvmx_npi_int_sum_s cn58xx;
@@ -964,8 +1632,13 @@ union cvmx_npi_int_sum {
964union cvmx_npi_lowp_dbell { 1632union cvmx_npi_lowp_dbell {
965 uint64_t u64; 1633 uint64_t u64;
966 struct cvmx_npi_lowp_dbell_s { 1634 struct cvmx_npi_lowp_dbell_s {
1635#ifdef __BIG_ENDIAN_BITFIELD
967 uint64_t reserved_16_63:48; 1636 uint64_t reserved_16_63:48;
968 uint64_t dbell:16; 1637 uint64_t dbell:16;
1638#else
1639 uint64_t dbell:16;
1640 uint64_t reserved_16_63:48;
1641#endif
969 } s; 1642 } s;
970 struct cvmx_npi_lowp_dbell_s cn30xx; 1643 struct cvmx_npi_lowp_dbell_s cn30xx;
971 struct cvmx_npi_lowp_dbell_s cn31xx; 1644 struct cvmx_npi_lowp_dbell_s cn31xx;
@@ -979,8 +1652,13 @@ union cvmx_npi_lowp_dbell {
979union cvmx_npi_lowp_ibuff_saddr { 1652union cvmx_npi_lowp_ibuff_saddr {
980 uint64_t u64; 1653 uint64_t u64;
981 struct cvmx_npi_lowp_ibuff_saddr_s { 1654 struct cvmx_npi_lowp_ibuff_saddr_s {
1655#ifdef __BIG_ENDIAN_BITFIELD
982 uint64_t reserved_36_63:28; 1656 uint64_t reserved_36_63:28;
983 uint64_t saddr:36; 1657 uint64_t saddr:36;
1658#else
1659 uint64_t saddr:36;
1660 uint64_t reserved_36_63:28;
1661#endif
984 } s; 1662 } s;
985 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx; 1663 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
986 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx; 1664 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
@@ -994,6 +1672,7 @@ union cvmx_npi_lowp_ibuff_saddr {
994union cvmx_npi_mem_access_subidx { 1672union cvmx_npi_mem_access_subidx {
995 uint64_t u64; 1673 uint64_t u64;
996 struct cvmx_npi_mem_access_subidx_s { 1674 struct cvmx_npi_mem_access_subidx_s {
1675#ifdef __BIG_ENDIAN_BITFIELD
997 uint64_t reserved_38_63:26; 1676 uint64_t reserved_38_63:26;
998 uint64_t shortl:1; 1677 uint64_t shortl:1;
999 uint64_t nmerge:1; 1678 uint64_t nmerge:1;
@@ -1004,9 +1683,22 @@ union cvmx_npi_mem_access_subidx {
1004 uint64_t ror:1; 1683 uint64_t ror:1;
1005 uint64_t row:1; 1684 uint64_t row:1;
1006 uint64_t ba:28; 1685 uint64_t ba:28;
1686#else
1687 uint64_t ba:28;
1688 uint64_t row:1;
1689 uint64_t ror:1;
1690 uint64_t nsw:1;
1691 uint64_t nsr:1;
1692 uint64_t esw:2;
1693 uint64_t esr:2;
1694 uint64_t nmerge:1;
1695 uint64_t shortl:1;
1696 uint64_t reserved_38_63:26;
1697#endif
1007 } s; 1698 } s;
1008 struct cvmx_npi_mem_access_subidx_s cn30xx; 1699 struct cvmx_npi_mem_access_subidx_s cn30xx;
1009 struct cvmx_npi_mem_access_subidx_cn31xx { 1700 struct cvmx_npi_mem_access_subidx_cn31xx {
1701#ifdef __BIG_ENDIAN_BITFIELD
1010 uint64_t reserved_36_63:28; 1702 uint64_t reserved_36_63:28;
1011 uint64_t esr:2; 1703 uint64_t esr:2;
1012 uint64_t esw:2; 1704 uint64_t esw:2;
@@ -1015,6 +1707,16 @@ union cvmx_npi_mem_access_subidx {
1015 uint64_t ror:1; 1707 uint64_t ror:1;
1016 uint64_t row:1; 1708 uint64_t row:1;
1017 uint64_t ba:28; 1709 uint64_t ba:28;
1710#else
1711 uint64_t ba:28;
1712 uint64_t row:1;
1713 uint64_t ror:1;
1714 uint64_t nsw:1;
1715 uint64_t nsr:1;
1716 uint64_t esw:2;
1717 uint64_t esr:2;
1718 uint64_t reserved_36_63:28;
1719#endif
1018 } cn31xx; 1720 } cn31xx;
1019 struct cvmx_npi_mem_access_subidx_s cn38xx; 1721 struct cvmx_npi_mem_access_subidx_s cn38xx;
1020 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2; 1722 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
@@ -1026,7 +1728,11 @@ union cvmx_npi_mem_access_subidx {
1026union cvmx_npi_msi_rcv { 1728union cvmx_npi_msi_rcv {
1027 uint64_t u64; 1729 uint64_t u64;
1028 struct cvmx_npi_msi_rcv_s { 1730 struct cvmx_npi_msi_rcv_s {
1731#ifdef __BIG_ENDIAN_BITFIELD
1732 uint64_t int_vec:64;
1733#else
1029 uint64_t int_vec:64; 1734 uint64_t int_vec:64;
1735#endif
1030 } s; 1736 } s;
1031 struct cvmx_npi_msi_rcv_s cn30xx; 1737 struct cvmx_npi_msi_rcv_s cn30xx;
1032 struct cvmx_npi_msi_rcv_s cn31xx; 1738 struct cvmx_npi_msi_rcv_s cn31xx;
@@ -1040,8 +1746,13 @@ union cvmx_npi_msi_rcv {
1040union cvmx_npi_num_desc_outputx { 1746union cvmx_npi_num_desc_outputx {
1041 uint64_t u64; 1747 uint64_t u64;
1042 struct cvmx_npi_num_desc_outputx_s { 1748 struct cvmx_npi_num_desc_outputx_s {
1749#ifdef __BIG_ENDIAN_BITFIELD
1043 uint64_t reserved_32_63:32; 1750 uint64_t reserved_32_63:32;
1044 uint64_t size:32; 1751 uint64_t size:32;
1752#else
1753 uint64_t size:32;
1754 uint64_t reserved_32_63:32;
1755#endif
1045 } s; 1756 } s;
1046 struct cvmx_npi_num_desc_outputx_s cn30xx; 1757 struct cvmx_npi_num_desc_outputx_s cn30xx;
1047 struct cvmx_npi_num_desc_outputx_s cn31xx; 1758 struct cvmx_npi_num_desc_outputx_s cn31xx;
@@ -1055,6 +1766,7 @@ union cvmx_npi_num_desc_outputx {
1055union cvmx_npi_output_control { 1766union cvmx_npi_output_control {
1056 uint64_t u64; 1767 uint64_t u64;
1057 struct cvmx_npi_output_control_s { 1768 struct cvmx_npi_output_control_s {
1769#ifdef __BIG_ENDIAN_BITFIELD
1058 uint64_t reserved_49_63:15; 1770 uint64_t reserved_49_63:15;
1059 uint64_t pkt_rr:1; 1771 uint64_t pkt_rr:1;
1060 uint64_t p3_bmode:1; 1772 uint64_t p3_bmode:1;
@@ -1094,8 +1806,50 @@ union cvmx_npi_output_control {
1094 uint64_t esr_sl0:2; 1806 uint64_t esr_sl0:2;
1095 uint64_t nsr_sl0:1; 1807 uint64_t nsr_sl0:1;
1096 uint64_t ror_sl0:1; 1808 uint64_t ror_sl0:1;
1809#else
1810 uint64_t ror_sl0:1;
1811 uint64_t nsr_sl0:1;
1812 uint64_t esr_sl0:2;
1813 uint64_t ror_sl1:1;
1814 uint64_t nsr_sl1:1;
1815 uint64_t esr_sl1:2;
1816 uint64_t ror_sl2:1;
1817 uint64_t nsr_sl2:1;
1818 uint64_t esr_sl2:2;
1819 uint64_t ror_sl3:1;
1820 uint64_t nsr_sl3:1;
1821 uint64_t esr_sl3:2;
1822 uint64_t iptr_o0:1;
1823 uint64_t iptr_o1:1;
1824 uint64_t iptr_o2:1;
1825 uint64_t iptr_o3:1;
1826 uint64_t reserved_20_23:4;
1827 uint64_t o0_csrm:1;
1828 uint64_t o1_csrm:1;
1829 uint64_t o2_csrm:1;
1830 uint64_t o3_csrm:1;
1831 uint64_t o0_ro:1;
1832 uint64_t o0_ns:1;
1833 uint64_t o0_es:2;
1834 uint64_t o1_ro:1;
1835 uint64_t o1_ns:1;
1836 uint64_t o1_es:2;
1837 uint64_t o2_ro:1;
1838 uint64_t o2_ns:1;
1839 uint64_t o2_es:2;
1840 uint64_t o3_ro:1;
1841 uint64_t o3_ns:1;
1842 uint64_t o3_es:2;
1843 uint64_t p0_bmode:1;
1844 uint64_t p1_bmode:1;
1845 uint64_t p2_bmode:1;
1846 uint64_t p3_bmode:1;
1847 uint64_t pkt_rr:1;
1848 uint64_t reserved_49_63:15;
1849#endif
1097 } s; 1850 } s;
1098 struct cvmx_npi_output_control_cn30xx { 1851 struct cvmx_npi_output_control_cn30xx {
1852#ifdef __BIG_ENDIAN_BITFIELD
1099 uint64_t reserved_45_63:19; 1853 uint64_t reserved_45_63:19;
1100 uint64_t p0_bmode:1; 1854 uint64_t p0_bmode:1;
1101 uint64_t reserved_32_43:12; 1855 uint64_t reserved_32_43:12;
@@ -1110,8 +1864,25 @@ union cvmx_npi_output_control {
1110 uint64_t esr_sl0:2; 1864 uint64_t esr_sl0:2;
1111 uint64_t nsr_sl0:1; 1865 uint64_t nsr_sl0:1;
1112 uint64_t ror_sl0:1; 1866 uint64_t ror_sl0:1;
1867#else
1868 uint64_t ror_sl0:1;
1869 uint64_t nsr_sl0:1;
1870 uint64_t esr_sl0:2;
1871 uint64_t reserved_4_15:12;
1872 uint64_t iptr_o0:1;
1873 uint64_t reserved_17_23:7;
1874 uint64_t o0_csrm:1;
1875 uint64_t reserved_25_27:3;
1876 uint64_t o0_ro:1;
1877 uint64_t o0_ns:1;
1878 uint64_t o0_es:2;
1879 uint64_t reserved_32_43:12;
1880 uint64_t p0_bmode:1;
1881 uint64_t reserved_45_63:19;
1882#endif
1113 } cn30xx; 1883 } cn30xx;
1114 struct cvmx_npi_output_control_cn31xx { 1884 struct cvmx_npi_output_control_cn31xx {
1885#ifdef __BIG_ENDIAN_BITFIELD
1115 uint64_t reserved_46_63:18; 1886 uint64_t reserved_46_63:18;
1116 uint64_t p1_bmode:1; 1887 uint64_t p1_bmode:1;
1117 uint64_t p0_bmode:1; 1888 uint64_t p0_bmode:1;
@@ -1135,9 +1906,35 @@ union cvmx_npi_output_control {
1135 uint64_t esr_sl0:2; 1906 uint64_t esr_sl0:2;
1136 uint64_t nsr_sl0:1; 1907 uint64_t nsr_sl0:1;
1137 uint64_t ror_sl0:1; 1908 uint64_t ror_sl0:1;
1909#else
1910 uint64_t ror_sl0:1;
1911 uint64_t nsr_sl0:1;
1912 uint64_t esr_sl0:2;
1913 uint64_t ror_sl1:1;
1914 uint64_t nsr_sl1:1;
1915 uint64_t esr_sl1:2;
1916 uint64_t reserved_8_15:8;
1917 uint64_t iptr_o0:1;
1918 uint64_t iptr_o1:1;
1919 uint64_t reserved_18_23:6;
1920 uint64_t o0_csrm:1;
1921 uint64_t o1_csrm:1;
1922 uint64_t reserved_26_27:2;
1923 uint64_t o0_ro:1;
1924 uint64_t o0_ns:1;
1925 uint64_t o0_es:2;
1926 uint64_t o1_ro:1;
1927 uint64_t o1_ns:1;
1928 uint64_t o1_es:2;
1929 uint64_t reserved_36_43:8;
1930 uint64_t p0_bmode:1;
1931 uint64_t p1_bmode:1;
1932 uint64_t reserved_46_63:18;
1933#endif
1138 } cn31xx; 1934 } cn31xx;
1139 struct cvmx_npi_output_control_s cn38xx; 1935 struct cvmx_npi_output_control_s cn38xx;
1140 struct cvmx_npi_output_control_cn38xxp2 { 1936 struct cvmx_npi_output_control_cn38xxp2 {
1937#ifdef __BIG_ENDIAN_BITFIELD
1141 uint64_t reserved_48_63:16; 1938 uint64_t reserved_48_63:16;
1142 uint64_t p3_bmode:1; 1939 uint64_t p3_bmode:1;
1143 uint64_t p2_bmode:1; 1940 uint64_t p2_bmode:1;
@@ -1176,8 +1973,49 @@ union cvmx_npi_output_control {
1176 uint64_t esr_sl0:2; 1973 uint64_t esr_sl0:2;
1177 uint64_t nsr_sl0:1; 1974 uint64_t nsr_sl0:1;
1178 uint64_t ror_sl0:1; 1975 uint64_t ror_sl0:1;
1976#else
1977 uint64_t ror_sl0:1;
1978 uint64_t nsr_sl0:1;
1979 uint64_t esr_sl0:2;
1980 uint64_t ror_sl1:1;
1981 uint64_t nsr_sl1:1;
1982 uint64_t esr_sl1:2;
1983 uint64_t ror_sl2:1;
1984 uint64_t nsr_sl2:1;
1985 uint64_t esr_sl2:2;
1986 uint64_t ror_sl3:1;
1987 uint64_t nsr_sl3:1;
1988 uint64_t esr_sl3:2;
1989 uint64_t iptr_o0:1;
1990 uint64_t iptr_o1:1;
1991 uint64_t iptr_o2:1;
1992 uint64_t iptr_o3:1;
1993 uint64_t reserved_20_23:4;
1994 uint64_t o0_csrm:1;
1995 uint64_t o1_csrm:1;
1996 uint64_t o2_csrm:1;
1997 uint64_t o3_csrm:1;
1998 uint64_t o0_ro:1;
1999 uint64_t o0_ns:1;
2000 uint64_t o0_es:2;
2001 uint64_t o1_ro:1;
2002 uint64_t o1_ns:1;
2003 uint64_t o1_es:2;
2004 uint64_t o2_ro:1;
2005 uint64_t o2_ns:1;
2006 uint64_t o2_es:2;
2007 uint64_t o3_ro:1;
2008 uint64_t o3_ns:1;
2009 uint64_t o3_es:2;
2010 uint64_t p0_bmode:1;
2011 uint64_t p1_bmode:1;
2012 uint64_t p2_bmode:1;
2013 uint64_t p3_bmode:1;
2014 uint64_t reserved_48_63:16;
2015#endif
1179 } cn38xxp2; 2016 } cn38xxp2;
1180 struct cvmx_npi_output_control_cn50xx { 2017 struct cvmx_npi_output_control_cn50xx {
2018#ifdef __BIG_ENDIAN_BITFIELD
1181 uint64_t reserved_49_63:15; 2019 uint64_t reserved_49_63:15;
1182 uint64_t pkt_rr:1; 2020 uint64_t pkt_rr:1;
1183 uint64_t reserved_46_47:2; 2021 uint64_t reserved_46_47:2;
@@ -1203,6 +2041,33 @@ union cvmx_npi_output_control {
1203 uint64_t esr_sl0:2; 2041 uint64_t esr_sl0:2;
1204 uint64_t nsr_sl0:1; 2042 uint64_t nsr_sl0:1;
1205 uint64_t ror_sl0:1; 2043 uint64_t ror_sl0:1;
2044#else
2045 uint64_t ror_sl0:1;
2046 uint64_t nsr_sl0:1;
2047 uint64_t esr_sl0:2;
2048 uint64_t ror_sl1:1;
2049 uint64_t nsr_sl1:1;
2050 uint64_t esr_sl1:2;
2051 uint64_t reserved_8_15:8;
2052 uint64_t iptr_o0:1;
2053 uint64_t iptr_o1:1;
2054 uint64_t reserved_18_23:6;
2055 uint64_t o0_csrm:1;
2056 uint64_t o1_csrm:1;
2057 uint64_t reserved_26_27:2;
2058 uint64_t o0_ro:1;
2059 uint64_t o0_ns:1;
2060 uint64_t o0_es:2;
2061 uint64_t o1_ro:1;
2062 uint64_t o1_ns:1;
2063 uint64_t o1_es:2;
2064 uint64_t reserved_36_43:8;
2065 uint64_t p0_bmode:1;
2066 uint64_t p1_bmode:1;
2067 uint64_t reserved_46_47:2;
2068 uint64_t pkt_rr:1;
2069 uint64_t reserved_49_63:15;
2070#endif
1206 } cn50xx; 2071 } cn50xx;
1207 struct cvmx_npi_output_control_s cn58xx; 2072 struct cvmx_npi_output_control_s cn58xx;
1208 struct cvmx_npi_output_control_s cn58xxp1; 2073 struct cvmx_npi_output_control_s cn58xxp1;
@@ -1211,9 +2076,15 @@ union cvmx_npi_output_control {
1211union cvmx_npi_px_dbpair_addr { 2076union cvmx_npi_px_dbpair_addr {
1212 uint64_t u64; 2077 uint64_t u64;
1213 struct cvmx_npi_px_dbpair_addr_s { 2078 struct cvmx_npi_px_dbpair_addr_s {
2079#ifdef __BIG_ENDIAN_BITFIELD
1214 uint64_t reserved_63_63:1; 2080 uint64_t reserved_63_63:1;
1215 uint64_t state:2; 2081 uint64_t state:2;
1216 uint64_t naddr:61; 2082 uint64_t naddr:61;
2083#else
2084 uint64_t naddr:61;
2085 uint64_t state:2;
2086 uint64_t reserved_63_63:1;
2087#endif
1217 } s; 2088 } s;
1218 struct cvmx_npi_px_dbpair_addr_s cn30xx; 2089 struct cvmx_npi_px_dbpair_addr_s cn30xx;
1219 struct cvmx_npi_px_dbpair_addr_s cn31xx; 2090 struct cvmx_npi_px_dbpair_addr_s cn31xx;
@@ -1227,8 +2098,13 @@ union cvmx_npi_px_dbpair_addr {
1227union cvmx_npi_px_instr_addr { 2098union cvmx_npi_px_instr_addr {
1228 uint64_t u64; 2099 uint64_t u64;
1229 struct cvmx_npi_px_instr_addr_s { 2100 struct cvmx_npi_px_instr_addr_s {
2101#ifdef __BIG_ENDIAN_BITFIELD
1230 uint64_t state:3; 2102 uint64_t state:3;
1231 uint64_t naddr:61; 2103 uint64_t naddr:61;
2104#else
2105 uint64_t naddr:61;
2106 uint64_t state:3;
2107#endif
1232 } s; 2108 } s;
1233 struct cvmx_npi_px_instr_addr_s cn30xx; 2109 struct cvmx_npi_px_instr_addr_s cn30xx;
1234 struct cvmx_npi_px_instr_addr_s cn31xx; 2110 struct cvmx_npi_px_instr_addr_s cn31xx;
@@ -1242,9 +2118,15 @@ union cvmx_npi_px_instr_addr {
1242union cvmx_npi_px_instr_cnts { 2118union cvmx_npi_px_instr_cnts {
1243 uint64_t u64; 2119 uint64_t u64;
1244 struct cvmx_npi_px_instr_cnts_s { 2120 struct cvmx_npi_px_instr_cnts_s {
2121#ifdef __BIG_ENDIAN_BITFIELD
1245 uint64_t reserved_38_63:26; 2122 uint64_t reserved_38_63:26;
1246 uint64_t fcnt:6; 2123 uint64_t fcnt:6;
1247 uint64_t avail:32; 2124 uint64_t avail:32;
2125#else
2126 uint64_t avail:32;
2127 uint64_t fcnt:6;
2128 uint64_t reserved_38_63:26;
2129#endif
1248 } s; 2130 } s;
1249 struct cvmx_npi_px_instr_cnts_s cn30xx; 2131 struct cvmx_npi_px_instr_cnts_s cn30xx;
1250 struct cvmx_npi_px_instr_cnts_s cn31xx; 2132 struct cvmx_npi_px_instr_cnts_s cn31xx;
@@ -1258,9 +2140,15 @@ union cvmx_npi_px_instr_cnts {
1258union cvmx_npi_px_pair_cnts { 2140union cvmx_npi_px_pair_cnts {
1259 uint64_t u64; 2141 uint64_t u64;
1260 struct cvmx_npi_px_pair_cnts_s { 2142 struct cvmx_npi_px_pair_cnts_s {
2143#ifdef __BIG_ENDIAN_BITFIELD
1261 uint64_t reserved_37_63:27; 2144 uint64_t reserved_37_63:27;
1262 uint64_t fcnt:5; 2145 uint64_t fcnt:5;
1263 uint64_t avail:32; 2146 uint64_t avail:32;
2147#else
2148 uint64_t avail:32;
2149 uint64_t fcnt:5;
2150 uint64_t reserved_37_63:27;
2151#endif
1264 } s; 2152 } s;
1265 struct cvmx_npi_px_pair_cnts_s cn30xx; 2153 struct cvmx_npi_px_pair_cnts_s cn30xx;
1266 struct cvmx_npi_px_pair_cnts_s cn31xx; 2154 struct cvmx_npi_px_pair_cnts_s cn31xx;
@@ -1274,9 +2162,15 @@ union cvmx_npi_px_pair_cnts {
1274union cvmx_npi_pci_burst_size { 2162union cvmx_npi_pci_burst_size {
1275 uint64_t u64; 2163 uint64_t u64;
1276 struct cvmx_npi_pci_burst_size_s { 2164 struct cvmx_npi_pci_burst_size_s {
2165#ifdef __BIG_ENDIAN_BITFIELD
1277 uint64_t reserved_14_63:50; 2166 uint64_t reserved_14_63:50;
1278 uint64_t wr_brst:7; 2167 uint64_t wr_brst:7;
1279 uint64_t rd_brst:7; 2168 uint64_t rd_brst:7;
2169#else
2170 uint64_t rd_brst:7;
2171 uint64_t wr_brst:7;
2172 uint64_t reserved_14_63:50;
2173#endif
1280 } s; 2174 } s;
1281 struct cvmx_npi_pci_burst_size_s cn30xx; 2175 struct cvmx_npi_pci_burst_size_s cn30xx;
1282 struct cvmx_npi_pci_burst_size_s cn31xx; 2176 struct cvmx_npi_pci_burst_size_s cn31xx;
@@ -1290,6 +2184,7 @@ union cvmx_npi_pci_burst_size {
1290union cvmx_npi_pci_int_arb_cfg { 2184union cvmx_npi_pci_int_arb_cfg {
1291 uint64_t u64; 2185 uint64_t u64;
1292 struct cvmx_npi_pci_int_arb_cfg_s { 2186 struct cvmx_npi_pci_int_arb_cfg_s {
2187#ifdef __BIG_ENDIAN_BITFIELD
1293 uint64_t reserved_13_63:51; 2188 uint64_t reserved_13_63:51;
1294 uint64_t hostmode:1; 2189 uint64_t hostmode:1;
1295 uint64_t pci_ovr:4; 2190 uint64_t pci_ovr:4;
@@ -1297,12 +2192,28 @@ union cvmx_npi_pci_int_arb_cfg {
1297 uint64_t en:1; 2192 uint64_t en:1;
1298 uint64_t park_mod:1; 2193 uint64_t park_mod:1;
1299 uint64_t park_dev:3; 2194 uint64_t park_dev:3;
2195#else
2196 uint64_t park_dev:3;
2197 uint64_t park_mod:1;
2198 uint64_t en:1;
2199 uint64_t reserved_5_7:3;
2200 uint64_t pci_ovr:4;
2201 uint64_t hostmode:1;
2202 uint64_t reserved_13_63:51;
2203#endif
1300 } s; 2204 } s;
1301 struct cvmx_npi_pci_int_arb_cfg_cn30xx { 2205 struct cvmx_npi_pci_int_arb_cfg_cn30xx {
2206#ifdef __BIG_ENDIAN_BITFIELD
1302 uint64_t reserved_5_63:59; 2207 uint64_t reserved_5_63:59;
1303 uint64_t en:1; 2208 uint64_t en:1;
1304 uint64_t park_mod:1; 2209 uint64_t park_mod:1;
1305 uint64_t park_dev:3; 2210 uint64_t park_dev:3;
2211#else
2212 uint64_t park_dev:3;
2213 uint64_t park_mod:1;
2214 uint64_t en:1;
2215 uint64_t reserved_5_63:59;
2216#endif
1306 } cn30xx; 2217 } cn30xx;
1307 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx; 2218 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
1308 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx; 2219 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
@@ -1315,8 +2226,13 @@ union cvmx_npi_pci_int_arb_cfg {
1315union cvmx_npi_pci_read_cmd { 2226union cvmx_npi_pci_read_cmd {
1316 uint64_t u64; 2227 uint64_t u64;
1317 struct cvmx_npi_pci_read_cmd_s { 2228 struct cvmx_npi_pci_read_cmd_s {
2229#ifdef __BIG_ENDIAN_BITFIELD
1318 uint64_t reserved_11_63:53; 2230 uint64_t reserved_11_63:53;
1319 uint64_t cmd_size:11; 2231 uint64_t cmd_size:11;
2232#else
2233 uint64_t cmd_size:11;
2234 uint64_t reserved_11_63:53;
2235#endif
1320 } s; 2236 } s;
1321 struct cvmx_npi_pci_read_cmd_s cn30xx; 2237 struct cvmx_npi_pci_read_cmd_s cn30xx;
1322 struct cvmx_npi_pci_read_cmd_s cn31xx; 2238 struct cvmx_npi_pci_read_cmd_s cn31xx;
@@ -1330,6 +2246,7 @@ union cvmx_npi_pci_read_cmd {
1330union cvmx_npi_port32_instr_hdr { 2246union cvmx_npi_port32_instr_hdr {
1331 uint64_t u64; 2247 uint64_t u64;
1332 struct cvmx_npi_port32_instr_hdr_s { 2248 struct cvmx_npi_port32_instr_hdr_s {
2249#ifdef __BIG_ENDIAN_BITFIELD
1333 uint64_t reserved_44_63:20; 2250 uint64_t reserved_44_63:20;
1334 uint64_t pbp:1; 2251 uint64_t pbp:1;
1335 uint64_t rsv_f:5; 2252 uint64_t rsv_f:5;
@@ -1343,6 +2260,21 @@ union cvmx_npi_port32_instr_hdr {
1343 uint64_t rsv_b:1; 2260 uint64_t rsv_b:1;
1344 uint64_t skp_len:7; 2261 uint64_t skp_len:7;
1345 uint64_t rsv_a:6; 2262 uint64_t rsv_a:6;
2263#else
2264 uint64_t rsv_a:6;
2265 uint64_t skp_len:7;
2266 uint64_t rsv_b:1;
2267 uint64_t par_mode:2;
2268 uint64_t rsv_c:5;
2269 uint64_t use_ihdr:1;
2270 uint64_t rsv_d:6;
2271 uint64_t rskp_len:7;
2272 uint64_t rsv_e:1;
2273 uint64_t rparmode:2;
2274 uint64_t rsv_f:5;
2275 uint64_t pbp:1;
2276 uint64_t reserved_44_63:20;
2277#endif
1346 } s; 2278 } s;
1347 struct cvmx_npi_port32_instr_hdr_s cn30xx; 2279 struct cvmx_npi_port32_instr_hdr_s cn30xx;
1348 struct cvmx_npi_port32_instr_hdr_s cn31xx; 2280 struct cvmx_npi_port32_instr_hdr_s cn31xx;
@@ -1356,6 +2288,7 @@ union cvmx_npi_port32_instr_hdr {
1356union cvmx_npi_port33_instr_hdr { 2288union cvmx_npi_port33_instr_hdr {
1357 uint64_t u64; 2289 uint64_t u64;
1358 struct cvmx_npi_port33_instr_hdr_s { 2290 struct cvmx_npi_port33_instr_hdr_s {
2291#ifdef __BIG_ENDIAN_BITFIELD
1359 uint64_t reserved_44_63:20; 2292 uint64_t reserved_44_63:20;
1360 uint64_t pbp:1; 2293 uint64_t pbp:1;
1361 uint64_t rsv_f:5; 2294 uint64_t rsv_f:5;
@@ -1369,6 +2302,21 @@ union cvmx_npi_port33_instr_hdr {
1369 uint64_t rsv_b:1; 2302 uint64_t rsv_b:1;
1370 uint64_t skp_len:7; 2303 uint64_t skp_len:7;
1371 uint64_t rsv_a:6; 2304 uint64_t rsv_a:6;
2305#else
2306 uint64_t rsv_a:6;
2307 uint64_t skp_len:7;
2308 uint64_t rsv_b:1;
2309 uint64_t par_mode:2;
2310 uint64_t rsv_c:5;
2311 uint64_t use_ihdr:1;
2312 uint64_t rsv_d:6;
2313 uint64_t rskp_len:7;
2314 uint64_t rsv_e:1;
2315 uint64_t rparmode:2;
2316 uint64_t rsv_f:5;
2317 uint64_t pbp:1;
2318 uint64_t reserved_44_63:20;
2319#endif
1372 } s; 2320 } s;
1373 struct cvmx_npi_port33_instr_hdr_s cn31xx; 2321 struct cvmx_npi_port33_instr_hdr_s cn31xx;
1374 struct cvmx_npi_port33_instr_hdr_s cn38xx; 2322 struct cvmx_npi_port33_instr_hdr_s cn38xx;
@@ -1381,6 +2329,7 @@ union cvmx_npi_port33_instr_hdr {
1381union cvmx_npi_port34_instr_hdr { 2329union cvmx_npi_port34_instr_hdr {
1382 uint64_t u64; 2330 uint64_t u64;
1383 struct cvmx_npi_port34_instr_hdr_s { 2331 struct cvmx_npi_port34_instr_hdr_s {
2332#ifdef __BIG_ENDIAN_BITFIELD
1384 uint64_t reserved_44_63:20; 2333 uint64_t reserved_44_63:20;
1385 uint64_t pbp:1; 2334 uint64_t pbp:1;
1386 uint64_t rsv_f:5; 2335 uint64_t rsv_f:5;
@@ -1394,6 +2343,21 @@ union cvmx_npi_port34_instr_hdr {
1394 uint64_t rsv_b:1; 2343 uint64_t rsv_b:1;
1395 uint64_t skp_len:7; 2344 uint64_t skp_len:7;
1396 uint64_t rsv_a:6; 2345 uint64_t rsv_a:6;
2346#else
2347 uint64_t rsv_a:6;
2348 uint64_t skp_len:7;
2349 uint64_t rsv_b:1;
2350 uint64_t par_mode:2;
2351 uint64_t rsv_c:5;
2352 uint64_t use_ihdr:1;
2353 uint64_t rsv_d:6;
2354 uint64_t rskp_len:7;
2355 uint64_t rsv_e:1;
2356 uint64_t rparmode:2;
2357 uint64_t rsv_f:5;
2358 uint64_t pbp:1;
2359 uint64_t reserved_44_63:20;
2360#endif
1397 } s; 2361 } s;
1398 struct cvmx_npi_port34_instr_hdr_s cn38xx; 2362 struct cvmx_npi_port34_instr_hdr_s cn38xx;
1399 struct cvmx_npi_port34_instr_hdr_s cn38xxp2; 2363 struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
@@ -1404,6 +2368,7 @@ union cvmx_npi_port34_instr_hdr {
1404union cvmx_npi_port35_instr_hdr { 2368union cvmx_npi_port35_instr_hdr {
1405 uint64_t u64; 2369 uint64_t u64;
1406 struct cvmx_npi_port35_instr_hdr_s { 2370 struct cvmx_npi_port35_instr_hdr_s {
2371#ifdef __BIG_ENDIAN_BITFIELD
1407 uint64_t reserved_44_63:20; 2372 uint64_t reserved_44_63:20;
1408 uint64_t pbp:1; 2373 uint64_t pbp:1;
1409 uint64_t rsv_f:5; 2374 uint64_t rsv_f:5;
@@ -1417,6 +2382,21 @@ union cvmx_npi_port35_instr_hdr {
1417 uint64_t rsv_b:1; 2382 uint64_t rsv_b:1;
1418 uint64_t skp_len:7; 2383 uint64_t skp_len:7;
1419 uint64_t rsv_a:6; 2384 uint64_t rsv_a:6;
2385#else
2386 uint64_t rsv_a:6;
2387 uint64_t skp_len:7;
2388 uint64_t rsv_b:1;
2389 uint64_t par_mode:2;
2390 uint64_t rsv_c:5;
2391 uint64_t use_ihdr:1;
2392 uint64_t rsv_d:6;
2393 uint64_t rskp_len:7;
2394 uint64_t rsv_e:1;
2395 uint64_t rparmode:2;
2396 uint64_t rsv_f:5;
2397 uint64_t pbp:1;
2398 uint64_t reserved_44_63:20;
2399#endif
1420 } s; 2400 } s;
1421 struct cvmx_npi_port35_instr_hdr_s cn38xx; 2401 struct cvmx_npi_port35_instr_hdr_s cn38xx;
1422 struct cvmx_npi_port35_instr_hdr_s cn38xxp2; 2402 struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
@@ -1427,9 +2407,15 @@ union cvmx_npi_port35_instr_hdr {
1427union cvmx_npi_port_bp_control { 2407union cvmx_npi_port_bp_control {
1428 uint64_t u64; 2408 uint64_t u64;
1429 struct cvmx_npi_port_bp_control_s { 2409 struct cvmx_npi_port_bp_control_s {
2410#ifdef __BIG_ENDIAN_BITFIELD
1430 uint64_t reserved_8_63:56; 2411 uint64_t reserved_8_63:56;
1431 uint64_t bp_on:4; 2412 uint64_t bp_on:4;
1432 uint64_t enb:4; 2413 uint64_t enb:4;
2414#else
2415 uint64_t enb:4;
2416 uint64_t bp_on:4;
2417 uint64_t reserved_8_63:56;
2418#endif
1433 } s; 2419 } s;
1434 struct cvmx_npi_port_bp_control_s cn30xx; 2420 struct cvmx_npi_port_bp_control_s cn30xx;
1435 struct cvmx_npi_port_bp_control_s cn31xx; 2421 struct cvmx_npi_port_bp_control_s cn31xx;
@@ -1443,6 +2429,7 @@ union cvmx_npi_port_bp_control {
1443union cvmx_npi_rsl_int_blocks { 2429union cvmx_npi_rsl_int_blocks {
1444 uint64_t u64; 2430 uint64_t u64;
1445 struct cvmx_npi_rsl_int_blocks_s { 2431 struct cvmx_npi_rsl_int_blocks_s {
2432#ifdef __BIG_ENDIAN_BITFIELD
1446 uint64_t reserved_32_63:32; 2433 uint64_t reserved_32_63:32;
1447 uint64_t rint_31:1; 2434 uint64_t rint_31:1;
1448 uint64_t iob:1; 2435 uint64_t iob:1;
@@ -1474,8 +2461,42 @@ union cvmx_npi_rsl_int_blocks {
1474 uint64_t gmx1:1; 2461 uint64_t gmx1:1;
1475 uint64_t gmx0:1; 2462 uint64_t gmx0:1;
1476 uint64_t mio:1; 2463 uint64_t mio:1;
2464#else
2465 uint64_t mio:1;
2466 uint64_t gmx0:1;
2467 uint64_t gmx1:1;
2468 uint64_t npi:1;
2469 uint64_t key:1;
2470 uint64_t fpa:1;
2471 uint64_t dfa:1;
2472 uint64_t zip:1;
2473 uint64_t rint_8:1;
2474 uint64_t ipd:1;
2475 uint64_t pko:1;
2476 uint64_t tim:1;
2477 uint64_t pow:1;
2478 uint64_t reserved_13_14:2;
2479 uint64_t rint_15:1;
2480 uint64_t l2c:1;
2481 uint64_t lmc:1;
2482 uint64_t spx0:1;
2483 uint64_t spx1:1;
2484 uint64_t pip:1;
2485 uint64_t rint_21:1;
2486 uint64_t asx0:1;
2487 uint64_t asx1:1;
2488 uint64_t rint_24:1;
2489 uint64_t rint_25:1;
2490 uint64_t rint_26:1;
2491 uint64_t rint_27:1;
2492 uint64_t reserved_28_29:2;
2493 uint64_t iob:1;
2494 uint64_t rint_31:1;
2495 uint64_t reserved_32_63:32;
2496#endif
1477 } s; 2497 } s;
1478 struct cvmx_npi_rsl_int_blocks_cn30xx { 2498 struct cvmx_npi_rsl_int_blocks_cn30xx {
2499#ifdef __BIG_ENDIAN_BITFIELD
1479 uint64_t reserved_32_63:32; 2500 uint64_t reserved_32_63:32;
1480 uint64_t rint_31:1; 2501 uint64_t rint_31:1;
1481 uint64_t iob:1; 2502 uint64_t iob:1;
@@ -1509,9 +2530,45 @@ union cvmx_npi_rsl_int_blocks {
1509 uint64_t gmx1:1; 2530 uint64_t gmx1:1;
1510 uint64_t gmx0:1; 2531 uint64_t gmx0:1;
1511 uint64_t mio:1; 2532 uint64_t mio:1;
2533#else
2534 uint64_t mio:1;
2535 uint64_t gmx0:1;
2536 uint64_t gmx1:1;
2537 uint64_t npi:1;
2538 uint64_t key:1;
2539 uint64_t fpa:1;
2540 uint64_t dfa:1;
2541 uint64_t zip:1;
2542 uint64_t rint_8:1;
2543 uint64_t ipd:1;
2544 uint64_t pko:1;
2545 uint64_t tim:1;
2546 uint64_t pow:1;
2547 uint64_t usb:1;
2548 uint64_t rint_14:1;
2549 uint64_t rint_15:1;
2550 uint64_t l2c:1;
2551 uint64_t lmc:1;
2552 uint64_t spx0:1;
2553 uint64_t spx1:1;
2554 uint64_t pip:1;
2555 uint64_t rint_21:1;
2556 uint64_t asx0:1;
2557 uint64_t asx1:1;
2558 uint64_t rint_24:1;
2559 uint64_t rint_25:1;
2560 uint64_t rint_26:1;
2561 uint64_t rint_27:1;
2562 uint64_t rint_28:1;
2563 uint64_t rint_29:1;
2564 uint64_t iob:1;
2565 uint64_t rint_31:1;
2566 uint64_t reserved_32_63:32;
2567#endif
1512 } cn30xx; 2568 } cn30xx;
1513 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx; 2569 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
1514 struct cvmx_npi_rsl_int_blocks_cn38xx { 2570 struct cvmx_npi_rsl_int_blocks_cn38xx {
2571#ifdef __BIG_ENDIAN_BITFIELD
1515 uint64_t reserved_32_63:32; 2572 uint64_t reserved_32_63:32;
1516 uint64_t rint_31:1; 2573 uint64_t rint_31:1;
1517 uint64_t iob:1; 2574 uint64_t iob:1;
@@ -1545,9 +2602,45 @@ union cvmx_npi_rsl_int_blocks {
1545 uint64_t gmx1:1; 2602 uint64_t gmx1:1;
1546 uint64_t gmx0:1; 2603 uint64_t gmx0:1;
1547 uint64_t mio:1; 2604 uint64_t mio:1;
2605#else
2606 uint64_t mio:1;
2607 uint64_t gmx0:1;
2608 uint64_t gmx1:1;
2609 uint64_t npi:1;
2610 uint64_t key:1;
2611 uint64_t fpa:1;
2612 uint64_t dfa:1;
2613 uint64_t zip:1;
2614 uint64_t rint_8:1;
2615 uint64_t ipd:1;
2616 uint64_t pko:1;
2617 uint64_t tim:1;
2618 uint64_t pow:1;
2619 uint64_t rint_13:1;
2620 uint64_t rint_14:1;
2621 uint64_t rint_15:1;
2622 uint64_t l2c:1;
2623 uint64_t lmc:1;
2624 uint64_t spx0:1;
2625 uint64_t spx1:1;
2626 uint64_t pip:1;
2627 uint64_t rint_21:1;
2628 uint64_t asx0:1;
2629 uint64_t asx1:1;
2630 uint64_t rint_24:1;
2631 uint64_t rint_25:1;
2632 uint64_t rint_26:1;
2633 uint64_t rint_27:1;
2634 uint64_t rint_28:1;
2635 uint64_t rint_29:1;
2636 uint64_t iob:1;
2637 uint64_t rint_31:1;
2638 uint64_t reserved_32_63:32;
2639#endif
1548 } cn38xx; 2640 } cn38xx;
1549 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2; 2641 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
1550 struct cvmx_npi_rsl_int_blocks_cn50xx { 2642 struct cvmx_npi_rsl_int_blocks_cn50xx {
2643#ifdef __BIG_ENDIAN_BITFIELD
1551 uint64_t reserved_31_63:33; 2644 uint64_t reserved_31_63:33;
1552 uint64_t iob:1; 2645 uint64_t iob:1;
1553 uint64_t lmc1:1; 2646 uint64_t lmc1:1;
@@ -1577,6 +2670,37 @@ union cvmx_npi_rsl_int_blocks {
1577 uint64_t gmx1:1; 2670 uint64_t gmx1:1;
1578 uint64_t gmx0:1; 2671 uint64_t gmx0:1;
1579 uint64_t mio:1; 2672 uint64_t mio:1;
2673#else
2674 uint64_t mio:1;
2675 uint64_t gmx0:1;
2676 uint64_t gmx1:1;
2677 uint64_t npi:1;
2678 uint64_t key:1;
2679 uint64_t fpa:1;
2680 uint64_t dfa:1;
2681 uint64_t zip:1;
2682 uint64_t reserved_8_8:1;
2683 uint64_t ipd:1;
2684 uint64_t pko:1;
2685 uint64_t tim:1;
2686 uint64_t pow:1;
2687 uint64_t usb:1;
2688 uint64_t rad:1;
2689 uint64_t reserved_15_15:1;
2690 uint64_t l2c:1;
2691 uint64_t lmc:1;
2692 uint64_t spx0:1;
2693 uint64_t spx1:1;
2694 uint64_t pip:1;
2695 uint64_t reserved_21_21:1;
2696 uint64_t asx0:1;
2697 uint64_t asx1:1;
2698 uint64_t reserved_24_27:4;
2699 uint64_t agl:1;
2700 uint64_t lmc1:1;
2701 uint64_t iob:1;
2702 uint64_t reserved_31_63:33;
2703#endif
1580 } cn50xx; 2704 } cn50xx;
1581 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx; 2705 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
1582 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1; 2706 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
@@ -1585,8 +2709,13 @@ union cvmx_npi_rsl_int_blocks {
1585union cvmx_npi_size_inputx { 2709union cvmx_npi_size_inputx {
1586 uint64_t u64; 2710 uint64_t u64;
1587 struct cvmx_npi_size_inputx_s { 2711 struct cvmx_npi_size_inputx_s {
2712#ifdef __BIG_ENDIAN_BITFIELD
1588 uint64_t reserved_32_63:32; 2713 uint64_t reserved_32_63:32;
1589 uint64_t size:32; 2714 uint64_t size:32;
2715#else
2716 uint64_t size:32;
2717 uint64_t reserved_32_63:32;
2718#endif
1590 } s; 2719 } s;
1591 struct cvmx_npi_size_inputx_s cn30xx; 2720 struct cvmx_npi_size_inputx_s cn30xx;
1592 struct cvmx_npi_size_inputx_s cn31xx; 2721 struct cvmx_npi_size_inputx_s cn31xx;
@@ -1600,8 +2729,13 @@ union cvmx_npi_size_inputx {
1600union cvmx_npi_win_read_to { 2729union cvmx_npi_win_read_to {
1601 uint64_t u64; 2730 uint64_t u64;
1602 struct cvmx_npi_win_read_to_s { 2731 struct cvmx_npi_win_read_to_s {
2732#ifdef __BIG_ENDIAN_BITFIELD
1603 uint64_t reserved_32_63:32; 2733 uint64_t reserved_32_63:32;
1604 uint64_t time:32; 2734 uint64_t time:32;
2735#else
2736 uint64_t time:32;
2737 uint64_t reserved_32_63:32;
2738#endif
1605 } s; 2739 } s;
1606 struct cvmx_npi_win_read_to_s cn30xx; 2740 struct cvmx_npi_win_read_to_s cn30xx;
1607 struct cvmx_npi_win_read_to_s cn31xx; 2741 struct cvmx_npi_win_read_to_s cn31xx;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 17:21:30 -0400