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-rw-r--r--arch/mips/include/asm/octeon/cvmx-npei-defs.h681
1 files changed, 300 insertions, 381 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 4b347bb8ce80..9899a9d2ba72 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,206 +28,114 @@
28#ifndef __CVMX_NPEI_DEFS_H__ 28#ifndef __CVMX_NPEI_DEFS_H__
29#define __CVMX_NPEI_DEFS_H__ 29#define __CVMX_NPEI_DEFS_H__
30 30
31#define CVMX_NPEI_BAR1_INDEXX(offset) \ 31#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
32 (0x0000000000000000ull + (((offset) & 31) * 16)) 32#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
33#define CVMX_NPEI_BIST_STATUS \ 33#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
34 (0x0000000000000580ull) 34#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
35#define CVMX_NPEI_BIST_STATUS2 \ 35#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
36 (0x0000000000000680ull) 36#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
37#define CVMX_NPEI_CTL_PORT0 \ 37#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
38 (0x0000000000000250ull) 38#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
39#define CVMX_NPEI_CTL_PORT1 \ 39#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
40 (0x0000000000000260ull) 40#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
41#define CVMX_NPEI_CTL_STATUS \ 41#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
42 (0x0000000000000570ull) 42#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
43#define CVMX_NPEI_CTL_STATUS2 \ 43#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
44 (0x0000000000003C00ull) 44#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
45#define CVMX_NPEI_DATA_OUT_CNT \ 45#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
46 (0x00000000000005F0ull) 46#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
47#define CVMX_NPEI_DBG_DATA \ 47#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
48 (0x0000000000000510ull) 48#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
49#define CVMX_NPEI_DBG_SELECT \ 49#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
50 (0x0000000000000500ull) 50#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
51#define CVMX_NPEI_DMA0_INT_LEVEL \ 51#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
52 (0x00000000000005C0ull) 52#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
53#define CVMX_NPEI_DMA1_INT_LEVEL \ 53#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
54 (0x00000000000005D0ull) 54#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
55#define CVMX_NPEI_DMAX_COUNTS(offset) \ 55#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
56 (0x0000000000000450ull + (((offset) & 7) * 16)) 56#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
57#define CVMX_NPEI_DMAX_DBELL(offset) \ 57#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
58 (0x00000000000003B0ull + (((offset) & 7) * 16)) 58#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
59#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \ 59#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
60 (0x0000000000000400ull + (((offset) & 7) * 16)) 60#define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
61#define CVMX_NPEI_DMAX_NADDR(offset) \ 61#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
62 (0x00000000000004A0ull + (((offset) & 7) * 16)) 62#define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
63#define CVMX_NPEI_DMA_CNTS \ 63#define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
64 (0x00000000000005E0ull) 64#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
65#define CVMX_NPEI_DMA_CONTROL \ 65#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66 (0x00000000000003A0ull) 66#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67#define CVMX_NPEI_INT_A_ENB \ 67#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68 (0x0000000000000560ull) 68#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
69#define CVMX_NPEI_INT_A_ENB2 \ 69#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70 (0x0000000000003CE0ull) 70#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71#define CVMX_NPEI_INT_A_SUM \ 71#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
72 (0x0000000000000550ull) 72#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
73#define CVMX_NPEI_INT_ENB \ 73#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
74 (0x0000000000000540ull) 74#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
75#define CVMX_NPEI_INT_ENB2 \ 75#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
76 (0x0000000000003CD0ull) 76#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
77#define CVMX_NPEI_INT_INFO \ 77#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
78 (0x0000000000000590ull) 78#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
79#define CVMX_NPEI_INT_SUM \ 79#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
80 (0x0000000000000530ull) 80#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
81#define CVMX_NPEI_INT_SUM2 \ 81#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
82 (0x0000000000003CC0ull) 82#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
83#define CVMX_NPEI_LAST_WIN_RDATA0 \ 83#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
84 (0x0000000000000600ull) 84#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
85#define CVMX_NPEI_LAST_WIN_RDATA1 \ 85#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
86 (0x0000000000000610ull) 86#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
87#define CVMX_NPEI_MEM_ACCESS_CTL \ 87#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
88 (0x00000000000004F0ull) 88#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
89#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \ 89#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
90 (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12) 90#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
91#define CVMX_NPEI_MSI_ENB0 \ 91#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
92 (0x0000000000003C50ull) 92#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
93#define CVMX_NPEI_MSI_ENB1 \ 93#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
94 (0x0000000000003C60ull) 94#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
95#define CVMX_NPEI_MSI_ENB2 \ 95#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
96 (0x0000000000003C70ull) 96#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
97#define CVMX_NPEI_MSI_ENB3 \ 97#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
98 (0x0000000000003C80ull) 98#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
99#define CVMX_NPEI_MSI_RCV0 \ 99#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
100 (0x0000000000003C10ull) 100#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
101#define CVMX_NPEI_MSI_RCV1 \ 101#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
102 (0x0000000000003C20ull) 102#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
103#define CVMX_NPEI_MSI_RCV2 \ 103#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
104 (0x0000000000003C30ull) 104#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
105#define CVMX_NPEI_MSI_RCV3 \ 105#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
106 (0x0000000000003C40ull) 106#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
107#define CVMX_NPEI_MSI_RD_MAP \ 107#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
108 (0x0000000000003CA0ull) 108#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
109#define CVMX_NPEI_MSI_W1C_ENB0 \ 109#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
110 (0x0000000000003CF0ull) 110#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
111#define CVMX_NPEI_MSI_W1C_ENB1 \ 111#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
112 (0x0000000000003D00ull) 112#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
113#define CVMX_NPEI_MSI_W1C_ENB2 \ 113#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
114 (0x0000000000003D10ull) 114#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
115#define CVMX_NPEI_MSI_W1C_ENB3 \ 115#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
116 (0x0000000000003D20ull) 116#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
117#define CVMX_NPEI_MSI_W1S_ENB0 \ 117#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
118 (0x0000000000003D30ull) 118#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
119#define CVMX_NPEI_MSI_W1S_ENB1 \ 119#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
120 (0x0000000000003D40ull) 120#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
121#define CVMX_NPEI_MSI_W1S_ENB2 \ 121#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
122 (0x0000000000003D50ull) 122#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
123#define CVMX_NPEI_MSI_W1S_ENB3 \ 123#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
124 (0x0000000000003D60ull) 124#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
125#define CVMX_NPEI_MSI_WR_MAP \ 125#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
126 (0x0000000000003C90ull) 126#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
127#define CVMX_NPEI_PCIE_CREDIT_CNT \ 127#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
128 (0x0000000000003D70ull) 128#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
129#define CVMX_NPEI_PCIE_MSI_RCV \ 129#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
130 (0x0000000000003CB0ull) 130#define CVMX_NPEI_STATE1 (0x0000000000000620ull)
131#define CVMX_NPEI_PCIE_MSI_RCV_B1 \ 131#define CVMX_NPEI_STATE2 (0x0000000000000630ull)
132 (0x0000000000000650ull) 132#define CVMX_NPEI_STATE3 (0x0000000000000640ull)
133#define CVMX_NPEI_PCIE_MSI_RCV_B2 \ 133#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
134 (0x0000000000000660ull) 134#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
135#define CVMX_NPEI_PCIE_MSI_RCV_B3 \ 135#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
136 (0x0000000000000670ull) 136#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
137#define CVMX_NPEI_PKTX_CNTS(offset) \ 137#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
138 (0x0000000000002400ull + (((offset) & 31) * 16)) 138#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
139#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
140 (0x0000000000002800ull + (((offset) & 31) * 16))
141#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
142 (0x0000000000002C00ull + (((offset) & 31) * 16))
143#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
144 (0x0000000000003000ull + (((offset) & 31) * 16))
145#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
146 (0x0000000000003400ull + (((offset) & 31) * 16))
147#define CVMX_NPEI_PKTX_IN_BP(offset) \
148 (0x0000000000003800ull + (((offset) & 31) * 16))
149#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
150 (0x0000000000001400ull + (((offset) & 31) * 16))
151#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
152 (0x0000000000001800ull + (((offset) & 31) * 16))
153#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
154 (0x0000000000001C00ull + (((offset) & 31) * 16))
155#define CVMX_NPEI_PKT_CNT_INT \
156 (0x0000000000001110ull)
157#define CVMX_NPEI_PKT_CNT_INT_ENB \
158 (0x0000000000001130ull)
159#define CVMX_NPEI_PKT_DATA_OUT_ES \
160 (0x00000000000010B0ull)
161#define CVMX_NPEI_PKT_DATA_OUT_NS \
162 (0x00000000000010A0ull)
163#define CVMX_NPEI_PKT_DATA_OUT_ROR \
164 (0x0000000000001090ull)
165#define CVMX_NPEI_PKT_DPADDR \
166 (0x0000000000001080ull)
167#define CVMX_NPEI_PKT_INPUT_CONTROL \
168 (0x0000000000001150ull)
169#define CVMX_NPEI_PKT_INSTR_ENB \
170 (0x0000000000001000ull)
171#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
172 (0x0000000000001190ull)
173#define CVMX_NPEI_PKT_INSTR_SIZE \
174 (0x0000000000001020ull)
175#define CVMX_NPEI_PKT_INT_LEVELS \
176 (0x0000000000001100ull)
177#define CVMX_NPEI_PKT_IN_BP \
178 (0x00000000000006B0ull)
179#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
180 (0x0000000000002000ull + (((offset) & 31) * 16))
181#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
182 (0x00000000000006A0ull)
183#define CVMX_NPEI_PKT_IN_PCIE_PORT \
184 (0x00000000000011A0ull)
185#define CVMX_NPEI_PKT_IPTR \
186 (0x0000000000001070ull)
187#define CVMX_NPEI_PKT_OUTPUT_WMARK \
188 (0x0000000000001160ull)
189#define CVMX_NPEI_PKT_OUT_BMODE \
190 (0x00000000000010D0ull)
191#define CVMX_NPEI_PKT_OUT_ENB \
192 (0x0000000000001010ull)
193#define CVMX_NPEI_PKT_PCIE_PORT \
194 (0x00000000000010E0ull)
195#define CVMX_NPEI_PKT_PORT_IN_RST \
196 (0x0000000000000690ull)
197#define CVMX_NPEI_PKT_SLIST_ES \
198 (0x0000000000001050ull)
199#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
200 (0x0000000000001180ull)
201#define CVMX_NPEI_PKT_SLIST_NS \
202 (0x0000000000001040ull)
203#define CVMX_NPEI_PKT_SLIST_ROR \
204 (0x0000000000001030ull)
205#define CVMX_NPEI_PKT_TIME_INT \
206 (0x0000000000001120ull)
207#define CVMX_NPEI_PKT_TIME_INT_ENB \
208 (0x0000000000001140ull)
209#define CVMX_NPEI_RSL_INT_BLOCKS \
210 (0x0000000000000520ull)
211#define CVMX_NPEI_SCRATCH_1 \
212 (0x0000000000000270ull)
213#define CVMX_NPEI_STATE1 \
214 (0x0000000000000620ull)
215#define CVMX_NPEI_STATE2 \
216 (0x0000000000000630ull)
217#define CVMX_NPEI_STATE3 \
218 (0x0000000000000640ull)
219#define CVMX_NPEI_WINDOW_CTL \
220 (0x0000000000000380ull)
221#define CVMX_NPEI_WIN_RD_ADDR \
222 (0x0000000000000210ull)
223#define CVMX_NPEI_WIN_RD_DATA \
224 (0x0000000000000240ull)
225#define CVMX_NPEI_WIN_WR_ADDR \
226 (0x0000000000000200ull)
227#define CVMX_NPEI_WIN_WR_DATA \
228 (0x0000000000000220ull)
229#define CVMX_NPEI_WIN_WR_MASK \
230 (0x0000000000000230ull)
231 139
232union cvmx_npei_bar1_indexx { 140union cvmx_npei_bar1_indexx {
233 uint32_t u32; 141 uint32_t u32;
@@ -248,9 +156,7 @@ union cvmx_npei_bist_status {
248 uint64_t u64; 156 uint64_t u64;
249 struct cvmx_npei_bist_status_s { 157 struct cvmx_npei_bist_status_s {
250 uint64_t pkt_rdf:1; 158 uint64_t pkt_rdf:1;
251 uint64_t pkt_pmem:1; 159 uint64_t reserved_60_62:3;
252 uint64_t pkt_p1:1;
253 uint64_t reserved_60_60:1;
254 uint64_t pcr_gim:1; 160 uint64_t pcr_gim:1;
255 uint64_t pkt_pif:1; 161 uint64_t pkt_pif:1;
256 uint64_t pcsr_int:1; 162 uint64_t pcsr_int:1;
@@ -301,9 +207,7 @@ union cvmx_npei_bist_status {
301 } s; 207 } s;
302 struct cvmx_npei_bist_status_cn52xx { 208 struct cvmx_npei_bist_status_cn52xx {
303 uint64_t pkt_rdf:1; 209 uint64_t pkt_rdf:1;
304 uint64_t pkt_pmem:1; 210 uint64_t reserved_60_62:3;
305 uint64_t pkt_p1:1;
306 uint64_t reserved_60_60:1;
307 uint64_t pcr_gim:1; 211 uint64_t pcr_gim:1;
308 uint64_t pkt_pif:1; 212 uint64_t pkt_pif:1;
309 uint64_t pcsr_int:1; 213 uint64_t pcsr_int:1;
@@ -410,66 +314,7 @@ union cvmx_npei_bist_status {
410 uint64_t msi:1; 314 uint64_t msi:1;
411 uint64_t ncb_cmd:1; 315 uint64_t ncb_cmd:1;
412 } cn52xxp1; 316 } cn52xxp1;
413 struct cvmx_npei_bist_status_cn56xx { 317 struct cvmx_npei_bist_status_cn52xx cn56xx;
414 uint64_t pkt_rdf:1;
415 uint64_t reserved_60_62:3;
416 uint64_t pcr_gim:1;
417 uint64_t pkt_pif:1;
418 uint64_t pcsr_int:1;
419 uint64_t pcsr_im:1;
420 uint64_t pcsr_cnt:1;
421 uint64_t pcsr_id:1;
422 uint64_t pcsr_sl:1;
423 uint64_t pkt_imem:1;
424 uint64_t pkt_pfm:1;
425 uint64_t pkt_pof:1;
426 uint64_t reserved_48_49:2;
427 uint64_t pkt_pop0:1;
428 uint64_t pkt_pop1:1;
429 uint64_t d0_mem:1;
430 uint64_t d1_mem:1;
431 uint64_t d2_mem:1;
432 uint64_t d3_mem:1;
433 uint64_t d4_mem:1;
434 uint64_t ds_mem:1;
435 uint64_t reserved_36_39:4;
436 uint64_t d0_pst:1;
437 uint64_t d1_pst:1;
438 uint64_t d2_pst:1;
439 uint64_t d3_pst:1;
440 uint64_t d4_pst:1;
441 uint64_t n2p0_c:1;
442 uint64_t n2p0_o:1;
443 uint64_t n2p1_c:1;
444 uint64_t n2p1_o:1;
445 uint64_t cpl_p0:1;
446 uint64_t cpl_p1:1;
447 uint64_t p2n1_po:1;
448 uint64_t p2n1_no:1;
449 uint64_t p2n1_co:1;
450 uint64_t p2n0_po:1;
451 uint64_t p2n0_no:1;
452 uint64_t p2n0_co:1;
453 uint64_t p2n0_c0:1;
454 uint64_t p2n0_c1:1;
455 uint64_t p2n0_n:1;
456 uint64_t p2n0_p0:1;
457 uint64_t p2n0_p1:1;
458 uint64_t p2n1_c0:1;
459 uint64_t p2n1_c1:1;
460 uint64_t p2n1_n:1;
461 uint64_t p2n1_p0:1;
462 uint64_t p2n1_p1:1;
463 uint64_t csm0:1;
464 uint64_t csm1:1;
465 uint64_t dif0:1;
466 uint64_t dif1:1;
467 uint64_t dif2:1;
468 uint64_t dif3:1;
469 uint64_t dif4:1;
470 uint64_t msi:1;
471 uint64_t ncb_cmd:1;
472 } cn56xx;
473 struct cvmx_npei_bist_status_cn56xxp1 { 318 struct cvmx_npei_bist_status_cn56xxp1 {
474 uint64_t reserved_58_63:6; 319 uint64_t reserved_58_63:6;
475 uint64_t pcsr_int:1; 320 uint64_t pcsr_int:1;
@@ -536,7 +381,16 @@ union cvmx_npei_bist_status {
536union cvmx_npei_bist_status2 { 381union cvmx_npei_bist_status2 {
537 uint64_t u64; 382 uint64_t u64;
538 struct cvmx_npei_bist_status2_s { 383 struct cvmx_npei_bist_status2_s {
539 uint64_t reserved_5_63:59; 384 uint64_t reserved_14_63:50;
385 uint64_t prd_tag:1;
386 uint64_t prd_st0:1;
387 uint64_t prd_st1:1;
388 uint64_t prd_err:1;
389 uint64_t nrd_st:1;
390 uint64_t nwe_st:1;
391 uint64_t nwe_wr0:1;
392 uint64_t nwe_wr1:1;
393 uint64_t pkt_rd:1;
540 uint64_t psc_p0:1; 394 uint64_t psc_p0:1;
541 uint64_t psc_p1:1; 395 uint64_t psc_p1:1;
542 uint64_t pkt_gd:1; 396 uint64_t pkt_gd:1;
@@ -630,8 +484,7 @@ union cvmx_npei_ctl_status {
630 } cn52xxp1; 484 } cn52xxp1;
631 struct cvmx_npei_ctl_status_s cn56xx; 485 struct cvmx_npei_ctl_status_s cn56xx;
632 struct cvmx_npei_ctl_status_cn56xxp1 { 486 struct cvmx_npei_ctl_status_cn56xxp1 {
633 uint64_t reserved_16_63:48; 487 uint64_t reserved_15_63:49;
634 uint64_t ring_en:1;
635 uint64_t lnk_rst:1; 488 uint64_t lnk_rst:1;
636 uint64_t arb:1; 489 uint64_t arb:1;
637 uint64_t pkt_bp:4; 490 uint64_t pkt_bp:4;
@@ -756,14 +609,14 @@ union cvmx_npei_dmax_ibuff_saddr {
756 uint64_t saddr:29; 609 uint64_t saddr:29;
757 uint64_t reserved_0_6:7; 610 uint64_t reserved_0_6:7;
758 } s; 611 } s;
759 struct cvmx_npei_dmax_ibuff_saddr_cn52xx { 612 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
613 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
760 uint64_t reserved_36_63:28; 614 uint64_t reserved_36_63:28;
761 uint64_t saddr:29; 615 uint64_t saddr:29;
762 uint64_t reserved_0_6:7; 616 uint64_t reserved_0_6:7;
763 } cn52xx; 617 } cn52xxp1;
764 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
765 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; 618 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
766 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1; 619 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
767}; 620};
768 621
769union cvmx_npei_dmax_naddr { 622union cvmx_npei_dmax_naddr {
@@ -817,7 +670,8 @@ union cvmx_npei_dma_cnts {
817union cvmx_npei_dma_control { 670union cvmx_npei_dma_control {
818 uint64_t u64; 671 uint64_t u64;
819 struct cvmx_npei_dma_control_s { 672 struct cvmx_npei_dma_control_s {
820 uint64_t reserved_39_63:25; 673 uint64_t reserved_40_63:24;
674 uint64_t p_32b_m:1;
821 uint64_t dma4_enb:1; 675 uint64_t dma4_enb:1;
822 uint64_t dma3_enb:1; 676 uint64_t dma3_enb:1;
823 uint64_t dma2_enb:1; 677 uint64_t dma2_enb:1;
@@ -853,7 +707,161 @@ union cvmx_npei_dma_control {
853 uint64_t csize:14; 707 uint64_t csize:14;
854 } cn52xxp1; 708 } cn52xxp1;
855 struct cvmx_npei_dma_control_s cn56xx; 709 struct cvmx_npei_dma_control_s cn56xx;
856 struct cvmx_npei_dma_control_s cn56xxp1; 710 struct cvmx_npei_dma_control_cn56xxp1 {
711 uint64_t reserved_39_63:25;
712 uint64_t dma4_enb:1;
713 uint64_t dma3_enb:1;
714 uint64_t dma2_enb:1;
715 uint64_t dma1_enb:1;
716 uint64_t dma0_enb:1;
717 uint64_t b0_lend:1;
718 uint64_t dwb_denb:1;
719 uint64_t dwb_ichk:9;
720 uint64_t fpa_que:3;
721 uint64_t o_add1:1;
722 uint64_t o_ro:1;
723 uint64_t o_ns:1;
724 uint64_t o_es:2;
725 uint64_t o_mode:1;
726 uint64_t csize:14;
727 } cn56xxp1;
728};
729
730union cvmx_npei_dma_pcie_req_num {
731 uint64_t u64;
732 struct cvmx_npei_dma_pcie_req_num_s {
733 uint64_t dma_arb:1;
734 uint64_t reserved_53_62:10;
735 uint64_t pkt_cnt:5;
736 uint64_t reserved_45_47:3;
737 uint64_t dma4_cnt:5;
738 uint64_t reserved_37_39:3;
739 uint64_t dma3_cnt:5;
740 uint64_t reserved_29_31:3;
741 uint64_t dma2_cnt:5;
742 uint64_t reserved_21_23:3;
743 uint64_t dma1_cnt:5;
744 uint64_t reserved_13_15:3;
745 uint64_t dma0_cnt:5;
746 uint64_t reserved_5_7:3;
747 uint64_t dma_cnt:5;
748 } s;
749 struct cvmx_npei_dma_pcie_req_num_s cn52xx;
750 struct cvmx_npei_dma_pcie_req_num_s cn56xx;
751};
752
753union cvmx_npei_dma_state1 {
754 uint64_t u64;
755 struct cvmx_npei_dma_state1_s {
756 uint64_t reserved_40_63:24;
757 uint64_t d4_dwe:8;
758 uint64_t d3_dwe:8;
759 uint64_t d2_dwe:8;
760 uint64_t d1_dwe:8;
761 uint64_t d0_dwe:8;
762 } s;
763 struct cvmx_npei_dma_state1_s cn52xx;
764};
765
766union cvmx_npei_dma_state1_p1 {
767 uint64_t u64;
768 struct cvmx_npei_dma_state1_p1_s {
769 uint64_t reserved_60_63:4;
770 uint64_t d0_difst:7;
771 uint64_t d1_difst:7;
772 uint64_t d2_difst:7;
773 uint64_t d3_difst:7;
774 uint64_t d4_difst:7;
775 uint64_t d0_reqst:5;
776 uint64_t d1_reqst:5;
777 uint64_t d2_reqst:5;
778 uint64_t d3_reqst:5;
779 uint64_t d4_reqst:5;
780 } s;
781 struct cvmx_npei_dma_state1_p1_cn52xxp1 {
782 uint64_t reserved_60_63:4;
783 uint64_t d0_difst:7;
784 uint64_t d1_difst:7;
785 uint64_t d2_difst:7;
786 uint64_t d3_difst:7;
787 uint64_t reserved_25_31:7;
788 uint64_t d0_reqst:5;
789 uint64_t d1_reqst:5;
790 uint64_t d2_reqst:5;
791 uint64_t d3_reqst:5;
792 uint64_t reserved_0_4:5;
793 } cn52xxp1;
794 struct cvmx_npei_dma_state1_p1_s cn56xxp1;
795};
796
797union cvmx_npei_dma_state2 {
798 uint64_t u64;
799 struct cvmx_npei_dma_state2_s {
800 uint64_t reserved_28_63:36;
801 uint64_t ndwe:4;
802 uint64_t reserved_21_23:3;
803 uint64_t ndre:5;
804 uint64_t reserved_10_15:6;
805 uint64_t prd:10;
806 } s;
807 struct cvmx_npei_dma_state2_s cn52xx;
808};
809
810union cvmx_npei_dma_state2_p1 {
811 uint64_t u64;
812 struct cvmx_npei_dma_state2_p1_s {
813 uint64_t reserved_45_63:19;
814 uint64_t d0_dffst:9;
815 uint64_t d1_dffst:9;
816 uint64_t d2_dffst:9;
817 uint64_t d3_dffst:9;
818 uint64_t d4_dffst:9;
819 } s;
820 struct cvmx_npei_dma_state2_p1_cn52xxp1 {
821 uint64_t reserved_45_63:19;
822 uint64_t d0_dffst:9;
823 uint64_t d1_dffst:9;
824 uint64_t d2_dffst:9;
825 uint64_t d3_dffst:9;
826 uint64_t reserved_0_8:9;
827 } cn52xxp1;
828 struct cvmx_npei_dma_state2_p1_s cn56xxp1;
829};
830
831union cvmx_npei_dma_state3_p1 {
832 uint64_t u64;
833 struct cvmx_npei_dma_state3_p1_s {
834 uint64_t reserved_60_63:4;
835 uint64_t d0_drest:15;
836 uint64_t d1_drest:15;
837 uint64_t d2_drest:15;
838 uint64_t d3_drest:15;
839 } s;
840 struct cvmx_npei_dma_state3_p1_s cn52xxp1;
841 struct cvmx_npei_dma_state3_p1_s cn56xxp1;
842};
843
844union cvmx_npei_dma_state4_p1 {
845 uint64_t u64;
846 struct cvmx_npei_dma_state4_p1_s {
847 uint64_t reserved_52_63:12;
848 uint64_t d0_dwest:13;
849 uint64_t d1_dwest:13;
850 uint64_t d2_dwest:13;
851 uint64_t d3_dwest:13;
852 } s;
853 struct cvmx_npei_dma_state4_p1_s cn52xxp1;
854 struct cvmx_npei_dma_state4_p1_s cn56xxp1;
855};
856
857union cvmx_npei_dma_state5_p1 {
858 uint64_t u64;
859 struct cvmx_npei_dma_state5_p1_s {
860 uint64_t reserved_28_63:36;
861 uint64_t d4_drest:15;
862 uint64_t d4_dwest:13;
863 } s;
864 struct cvmx_npei_dma_state5_p1_s cn56xxp1;
857}; 865};
858 866
859union cvmx_npei_int_a_enb { 867union cvmx_npei_int_a_enb {
@@ -871,17 +879,7 @@ union cvmx_npei_int_a_enb {
871 uint64_t dma1_cpl:1; 879 uint64_t dma1_cpl:1;
872 uint64_t dma0_cpl:1; 880 uint64_t dma0_cpl:1;
873 } s; 881 } s;
874 struct cvmx_npei_int_a_enb_cn52xx { 882 struct cvmx_npei_int_a_enb_s cn52xx;
875 uint64_t reserved_8_63:56;
876 uint64_t p1_rdlk:1;
877 uint64_t p0_rdlk:1;
878 uint64_t pgl_err:1;
879 uint64_t pdi_err:1;
880 uint64_t pop_err:1;
881 uint64_t pins_err:1;
882 uint64_t dma1_cpl:1;
883 uint64_t dma0_cpl:1;
884 } cn52xx;
885 struct cvmx_npei_int_a_enb_cn52xxp1 { 883 struct cvmx_npei_int_a_enb_cn52xxp1 {
886 uint64_t reserved_2_63:62; 884 uint64_t reserved_2_63:62;
887 uint64_t dma1_cpl:1; 885 uint64_t dma1_cpl:1;
@@ -905,16 +903,7 @@ union cvmx_npei_int_a_enb2 {
905 uint64_t dma1_cpl:1; 903 uint64_t dma1_cpl:1;
906 uint64_t dma0_cpl:1; 904 uint64_t dma0_cpl:1;
907 } s; 905 } s;
908 struct cvmx_npei_int_a_enb2_cn52xx { 906 struct cvmx_npei_int_a_enb2_s cn52xx;
909 uint64_t reserved_8_63:56;
910 uint64_t p1_rdlk:1;
911 uint64_t p0_rdlk:1;
912 uint64_t pgl_err:1;
913 uint64_t pdi_err:1;
914 uint64_t pop_err:1;
915 uint64_t pins_err:1;
916 uint64_t reserved_0_1:2;
917 } cn52xx;
918 struct cvmx_npei_int_a_enb2_cn52xxp1 { 907 struct cvmx_npei_int_a_enb2_cn52xxp1 {
919 uint64_t reserved_2_63:62; 908 uint64_t reserved_2_63:62;
920 uint64_t dma1_cpl:1; 909 uint64_t dma1_cpl:1;
@@ -938,17 +927,7 @@ union cvmx_npei_int_a_sum {
938 uint64_t dma1_cpl:1; 927 uint64_t dma1_cpl:1;
939 uint64_t dma0_cpl:1; 928 uint64_t dma0_cpl:1;
940 } s; 929 } s;
941 struct cvmx_npei_int_a_sum_cn52xx { 930 struct cvmx_npei_int_a_sum_s cn52xx;
942 uint64_t reserved_8_63:56;
943 uint64_t p1_rdlk:1;
944 uint64_t p0_rdlk:1;
945 uint64_t pgl_err:1;
946 uint64_t pdi_err:1;
947 uint64_t pop_err:1;
948 uint64_t pins_err:1;
949 uint64_t dma1_cpl:1;
950 uint64_t dma0_cpl:1;
951 } cn52xx;
952 struct cvmx_npei_int_a_sum_cn52xxp1 { 931 struct cvmx_npei_int_a_sum_cn52xxp1 {
953 uint64_t reserved_2_63:62; 932 uint64_t reserved_2_63:62;
954 uint64_t dma1_cpl:1; 933 uint64_t dma1_cpl:1;
@@ -1550,10 +1529,7 @@ union cvmx_npei_int_sum {
1550 uint64_t c0_se:1; 1529 uint64_t c0_se:1;
1551 uint64_t reserved_20_20:1; 1530 uint64_t reserved_20_20:1;
1552 uint64_t c0_aeri:1; 1531 uint64_t c0_aeri:1;
1553 uint64_t ptime:1; 1532 uint64_t reserved_15_18:4;
1554 uint64_t pcnt:1;
1555 uint64_t pidbof:1;
1556 uint64_t psldbof:1;
1557 uint64_t dtime1:1; 1533 uint64_t dtime1:1;
1558 uint64_t dtime0:1; 1534 uint64_t dtime0:1;
1559 uint64_t dcnt1:1; 1535 uint64_t dcnt1:1;
@@ -1959,7 +1935,6 @@ union cvmx_npei_pktx_cnts {
1959 } s; 1935 } s;
1960 struct cvmx_npei_pktx_cnts_s cn52xx; 1936 struct cvmx_npei_pktx_cnts_s cn52xx;
1961 struct cvmx_npei_pktx_cnts_s cn56xx; 1937 struct cvmx_npei_pktx_cnts_s cn56xx;
1962 struct cvmx_npei_pktx_cnts_s cn56xxp1;
1963}; 1938};
1964 1939
1965union cvmx_npei_pktx_in_bp { 1940union cvmx_npei_pktx_in_bp {
@@ -1970,7 +1945,6 @@ union cvmx_npei_pktx_in_bp {
1970 } s; 1945 } s;
1971 struct cvmx_npei_pktx_in_bp_s cn52xx; 1946 struct cvmx_npei_pktx_in_bp_s cn52xx;
1972 struct cvmx_npei_pktx_in_bp_s cn56xx; 1947 struct cvmx_npei_pktx_in_bp_s cn56xx;
1973 struct cvmx_npei_pktx_in_bp_s cn56xxp1;
1974}; 1948};
1975 1949
1976union cvmx_npei_pktx_instr_baddr { 1950union cvmx_npei_pktx_instr_baddr {
@@ -1981,7 +1955,6 @@ union cvmx_npei_pktx_instr_baddr {
1981 } s; 1955 } s;
1982 struct cvmx_npei_pktx_instr_baddr_s cn52xx; 1956 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
1983 struct cvmx_npei_pktx_instr_baddr_s cn56xx; 1957 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
1984 struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
1985}; 1958};
1986 1959
1987union cvmx_npei_pktx_instr_baoff_dbell { 1960union cvmx_npei_pktx_instr_baoff_dbell {
@@ -1992,7 +1965,6 @@ union cvmx_npei_pktx_instr_baoff_dbell {
1992 } s; 1965 } s;
1993 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; 1966 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
1994 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; 1967 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
1995 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
1996}; 1968};
1997 1969
1998union cvmx_npei_pktx_instr_fifo_rsize { 1970union cvmx_npei_pktx_instr_fifo_rsize {
@@ -2006,7 +1978,6 @@ union cvmx_npei_pktx_instr_fifo_rsize {
2006 } s; 1978 } s;
2007 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; 1979 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
2008 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; 1980 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
2009 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
2010}; 1981};
2011 1982
2012union cvmx_npei_pktx_instr_header { 1983union cvmx_npei_pktx_instr_header {
@@ -2014,21 +1985,20 @@ union cvmx_npei_pktx_instr_header {
2014 struct cvmx_npei_pktx_instr_header_s { 1985 struct cvmx_npei_pktx_instr_header_s {
2015 uint64_t reserved_44_63:20; 1986 uint64_t reserved_44_63:20;
2016 uint64_t pbp:1; 1987 uint64_t pbp:1;
2017 uint64_t rsv_f:5; 1988 uint64_t reserved_38_42:5;
2018 uint64_t rparmode:2; 1989 uint64_t rparmode:2;
2019 uint64_t rsv_e:1; 1990 uint64_t reserved_35_35:1;
2020 uint64_t rskp_len:7; 1991 uint64_t rskp_len:7;
2021 uint64_t rsv_d:6; 1992 uint64_t reserved_22_27:6;
2022 uint64_t use_ihdr:1; 1993 uint64_t use_ihdr:1;
2023 uint64_t rsv_c:5; 1994 uint64_t reserved_16_20:5;
2024 uint64_t par_mode:2; 1995 uint64_t par_mode:2;
2025 uint64_t rsv_b:1; 1996 uint64_t reserved_13_13:1;
2026 uint64_t skp_len:7; 1997 uint64_t skp_len:7;
2027 uint64_t rsv_a:6; 1998 uint64_t reserved_0_5:6;
2028 } s; 1999 } s;
2029 struct cvmx_npei_pktx_instr_header_s cn52xx; 2000 struct cvmx_npei_pktx_instr_header_s cn52xx;
2030 struct cvmx_npei_pktx_instr_header_s cn56xx; 2001 struct cvmx_npei_pktx_instr_header_s cn56xx;
2031 struct cvmx_npei_pktx_instr_header_s cn56xxp1;
2032}; 2002};
2033 2003
2034union cvmx_npei_pktx_slist_baddr { 2004union cvmx_npei_pktx_slist_baddr {
@@ -2039,7 +2009,6 @@ union cvmx_npei_pktx_slist_baddr {
2039 } s; 2009 } s;
2040 struct cvmx_npei_pktx_slist_baddr_s cn52xx; 2010 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2041 struct cvmx_npei_pktx_slist_baddr_s cn56xx; 2011 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2042 struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
2043}; 2012};
2044 2013
2045union cvmx_npei_pktx_slist_baoff_dbell { 2014union cvmx_npei_pktx_slist_baoff_dbell {
@@ -2050,7 +2019,6 @@ union cvmx_npei_pktx_slist_baoff_dbell {
2050 } s; 2019 } s;
2051 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; 2020 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2052 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; 2021 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2053 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
2054}; 2022};
2055 2023
2056union cvmx_npei_pktx_slist_fifo_rsize { 2024union cvmx_npei_pktx_slist_fifo_rsize {
@@ -2061,7 +2029,6 @@ union cvmx_npei_pktx_slist_fifo_rsize {
2061 } s; 2029 } s;
2062 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; 2030 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2063 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; 2031 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2064 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
2065}; 2032};
2066 2033
2067union cvmx_npei_pkt_cnt_int { 2034union cvmx_npei_pkt_cnt_int {
@@ -2072,7 +2039,6 @@ union cvmx_npei_pkt_cnt_int {
2072 } s; 2039 } s;
2073 struct cvmx_npei_pkt_cnt_int_s cn52xx; 2040 struct cvmx_npei_pkt_cnt_int_s cn52xx;
2074 struct cvmx_npei_pkt_cnt_int_s cn56xx; 2041 struct cvmx_npei_pkt_cnt_int_s cn56xx;
2075 struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
2076}; 2042};
2077 2043
2078union cvmx_npei_pkt_cnt_int_enb { 2044union cvmx_npei_pkt_cnt_int_enb {
@@ -2083,7 +2049,6 @@ union cvmx_npei_pkt_cnt_int_enb {
2083 } s; 2049 } s;
2084 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; 2050 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2085 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; 2051 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2086 struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
2087}; 2052};
2088 2053
2089union cvmx_npei_pkt_data_out_es { 2054union cvmx_npei_pkt_data_out_es {
@@ -2093,7 +2058,6 @@ union cvmx_npei_pkt_data_out_es {
2093 } s; 2058 } s;
2094 struct cvmx_npei_pkt_data_out_es_s cn52xx; 2059 struct cvmx_npei_pkt_data_out_es_s cn52xx;
2095 struct cvmx_npei_pkt_data_out_es_s cn56xx; 2060 struct cvmx_npei_pkt_data_out_es_s cn56xx;
2096 struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
2097}; 2061};
2098 2062
2099union cvmx_npei_pkt_data_out_ns { 2063union cvmx_npei_pkt_data_out_ns {
@@ -2104,7 +2068,6 @@ union cvmx_npei_pkt_data_out_ns {
2104 } s; 2068 } s;
2105 struct cvmx_npei_pkt_data_out_ns_s cn52xx; 2069 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2106 struct cvmx_npei_pkt_data_out_ns_s cn56xx; 2070 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2107 struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
2108}; 2071};
2109 2072
2110union cvmx_npei_pkt_data_out_ror { 2073union cvmx_npei_pkt_data_out_ror {
@@ -2115,7 +2078,6 @@ union cvmx_npei_pkt_data_out_ror {
2115 } s; 2078 } s;
2116 struct cvmx_npei_pkt_data_out_ror_s cn52xx; 2079 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2117 struct cvmx_npei_pkt_data_out_ror_s cn56xx; 2080 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2118 struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
2119}; 2081};
2120 2082
2121union cvmx_npei_pkt_dpaddr { 2083union cvmx_npei_pkt_dpaddr {
@@ -2126,7 +2088,6 @@ union cvmx_npei_pkt_dpaddr {
2126 } s; 2088 } s;
2127 struct cvmx_npei_pkt_dpaddr_s cn52xx; 2089 struct cvmx_npei_pkt_dpaddr_s cn52xx;
2128 struct cvmx_npei_pkt_dpaddr_s cn56xx; 2090 struct cvmx_npei_pkt_dpaddr_s cn56xx;
2129 struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
2130}; 2091};
2131 2092
2132union cvmx_npei_pkt_in_bp { 2093union cvmx_npei_pkt_in_bp {
@@ -2135,6 +2096,7 @@ union cvmx_npei_pkt_in_bp {
2135 uint64_t reserved_32_63:32; 2096 uint64_t reserved_32_63:32;
2136 uint64_t bp:32; 2097 uint64_t bp:32;
2137 } s; 2098 } s;
2099 struct cvmx_npei_pkt_in_bp_s cn52xx;
2138 struct cvmx_npei_pkt_in_bp_s cn56xx; 2100 struct cvmx_npei_pkt_in_bp_s cn56xx;
2139}; 2101};
2140 2102
@@ -2146,7 +2108,6 @@ union cvmx_npei_pkt_in_donex_cnts {
2146 } s; 2108 } s;
2147 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; 2109 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2148 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; 2110 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2149 struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
2150}; 2111};
2151 2112
2152union cvmx_npei_pkt_in_instr_counts { 2113union cvmx_npei_pkt_in_instr_counts {
@@ -2184,7 +2145,6 @@ union cvmx_npei_pkt_input_control {
2184 } s; 2145 } s;
2185 struct cvmx_npei_pkt_input_control_s cn52xx; 2146 struct cvmx_npei_pkt_input_control_s cn52xx;
2186 struct cvmx_npei_pkt_input_control_s cn56xx; 2147 struct cvmx_npei_pkt_input_control_s cn56xx;
2187 struct cvmx_npei_pkt_input_control_s cn56xxp1;
2188}; 2148};
2189 2149
2190union cvmx_npei_pkt_instr_enb { 2150union cvmx_npei_pkt_instr_enb {
@@ -2195,7 +2155,6 @@ union cvmx_npei_pkt_instr_enb {
2195 } s; 2155 } s;
2196 struct cvmx_npei_pkt_instr_enb_s cn52xx; 2156 struct cvmx_npei_pkt_instr_enb_s cn52xx;
2197 struct cvmx_npei_pkt_instr_enb_s cn56xx; 2157 struct cvmx_npei_pkt_instr_enb_s cn56xx;
2198 struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
2199}; 2158};
2200 2159
2201union cvmx_npei_pkt_instr_rd_size { 2160union cvmx_npei_pkt_instr_rd_size {
@@ -2215,7 +2174,6 @@ union cvmx_npei_pkt_instr_size {
2215 } s; 2174 } s;
2216 struct cvmx_npei_pkt_instr_size_s cn52xx; 2175 struct cvmx_npei_pkt_instr_size_s cn52xx;
2217 struct cvmx_npei_pkt_instr_size_s cn56xx; 2176 struct cvmx_npei_pkt_instr_size_s cn56xx;
2218 struct cvmx_npei_pkt_instr_size_s cn56xxp1;
2219}; 2177};
2220 2178
2221union cvmx_npei_pkt_int_levels { 2179union cvmx_npei_pkt_int_levels {
@@ -2227,7 +2185,6 @@ union cvmx_npei_pkt_int_levels {
2227 } s; 2185 } s;
2228 struct cvmx_npei_pkt_int_levels_s cn52xx; 2186 struct cvmx_npei_pkt_int_levels_s cn52xx;
2229 struct cvmx_npei_pkt_int_levels_s cn56xx; 2187 struct cvmx_npei_pkt_int_levels_s cn56xx;
2230 struct cvmx_npei_pkt_int_levels_s cn56xxp1;
2231}; 2188};
2232 2189
2233union cvmx_npei_pkt_iptr { 2190union cvmx_npei_pkt_iptr {
@@ -2238,7 +2195,6 @@ union cvmx_npei_pkt_iptr {
2238 } s; 2195 } s;
2239 struct cvmx_npei_pkt_iptr_s cn52xx; 2196 struct cvmx_npei_pkt_iptr_s cn52xx;
2240 struct cvmx_npei_pkt_iptr_s cn56xx; 2197 struct cvmx_npei_pkt_iptr_s cn56xx;
2241 struct cvmx_npei_pkt_iptr_s cn56xxp1;
2242}; 2198};
2243 2199
2244union cvmx_npei_pkt_out_bmode { 2200union cvmx_npei_pkt_out_bmode {
@@ -2249,7 +2205,6 @@ union cvmx_npei_pkt_out_bmode {
2249 } s; 2205 } s;
2250 struct cvmx_npei_pkt_out_bmode_s cn52xx; 2206 struct cvmx_npei_pkt_out_bmode_s cn52xx;
2251 struct cvmx_npei_pkt_out_bmode_s cn56xx; 2207 struct cvmx_npei_pkt_out_bmode_s cn56xx;
2252 struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
2253}; 2208};
2254 2209
2255union cvmx_npei_pkt_out_enb { 2210union cvmx_npei_pkt_out_enb {
@@ -2260,7 +2215,6 @@ union cvmx_npei_pkt_out_enb {
2260 } s; 2215 } s;
2261 struct cvmx_npei_pkt_out_enb_s cn52xx; 2216 struct cvmx_npei_pkt_out_enb_s cn52xx;
2262 struct cvmx_npei_pkt_out_enb_s cn56xx; 2217 struct cvmx_npei_pkt_out_enb_s cn56xx;
2263 struct cvmx_npei_pkt_out_enb_s cn56xxp1;
2264}; 2218};
2265 2219
2266union cvmx_npei_pkt_output_wmark { 2220union cvmx_npei_pkt_output_wmark {
@@ -2280,7 +2234,6 @@ union cvmx_npei_pkt_pcie_port {
2280 } s; 2234 } s;
2281 struct cvmx_npei_pkt_pcie_port_s cn52xx; 2235 struct cvmx_npei_pkt_pcie_port_s cn52xx;
2282 struct cvmx_npei_pkt_pcie_port_s cn56xx; 2236 struct cvmx_npei_pkt_pcie_port_s cn56xx;
2283 struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
2284}; 2237};
2285 2238
2286union cvmx_npei_pkt_port_in_rst { 2239union cvmx_npei_pkt_port_in_rst {
@@ -2300,7 +2253,6 @@ union cvmx_npei_pkt_slist_es {
2300 } s; 2253 } s;
2301 struct cvmx_npei_pkt_slist_es_s cn52xx; 2254 struct cvmx_npei_pkt_slist_es_s cn52xx;
2302 struct cvmx_npei_pkt_slist_es_s cn56xx; 2255 struct cvmx_npei_pkt_slist_es_s cn56xx;
2303 struct cvmx_npei_pkt_slist_es_s cn56xxp1;
2304}; 2256};
2305 2257
2306union cvmx_npei_pkt_slist_id_size { 2258union cvmx_npei_pkt_slist_id_size {
@@ -2312,7 +2264,6 @@ union cvmx_npei_pkt_slist_id_size {
2312 } s; 2264 } s;
2313 struct cvmx_npei_pkt_slist_id_size_s cn52xx; 2265 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2314 struct cvmx_npei_pkt_slist_id_size_s cn56xx; 2266 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2315 struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
2316}; 2267};
2317 2268
2318union cvmx_npei_pkt_slist_ns { 2269union cvmx_npei_pkt_slist_ns {
@@ -2323,7 +2274,6 @@ union cvmx_npei_pkt_slist_ns {
2323 } s; 2274 } s;
2324 struct cvmx_npei_pkt_slist_ns_s cn52xx; 2275 struct cvmx_npei_pkt_slist_ns_s cn52xx;
2325 struct cvmx_npei_pkt_slist_ns_s cn56xx; 2276 struct cvmx_npei_pkt_slist_ns_s cn56xx;
2326 struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
2327}; 2277};
2328 2278
2329union cvmx_npei_pkt_slist_ror { 2279union cvmx_npei_pkt_slist_ror {
@@ -2334,7 +2284,6 @@ union cvmx_npei_pkt_slist_ror {
2334 } s; 2284 } s;
2335 struct cvmx_npei_pkt_slist_ror_s cn52xx; 2285 struct cvmx_npei_pkt_slist_ror_s cn52xx;
2336 struct cvmx_npei_pkt_slist_ror_s cn56xx; 2286 struct cvmx_npei_pkt_slist_ror_s cn56xx;
2337 struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
2338}; 2287};
2339 2288
2340union cvmx_npei_pkt_time_int { 2289union cvmx_npei_pkt_time_int {
@@ -2345,7 +2294,6 @@ union cvmx_npei_pkt_time_int {
2345 } s; 2294 } s;
2346 struct cvmx_npei_pkt_time_int_s cn52xx; 2295 struct cvmx_npei_pkt_time_int_s cn52xx;
2347 struct cvmx_npei_pkt_time_int_s cn56xx; 2296 struct cvmx_npei_pkt_time_int_s cn56xx;
2348 struct cvmx_npei_pkt_time_int_s cn56xxp1;
2349}; 2297};
2350 2298
2351union cvmx_npei_pkt_time_int_enb { 2299union cvmx_npei_pkt_time_int_enb {
@@ -2356,7 +2304,6 @@ union cvmx_npei_pkt_time_int_enb {
2356 } s; 2304 } s;
2357 struct cvmx_npei_pkt_time_int_enb_s cn52xx; 2305 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2358 struct cvmx_npei_pkt_time_int_enb_s cn56xx; 2306 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2359 struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
2360}; 2307};
2361 2308
2362union cvmx_npei_rsl_int_blocks { 2309union cvmx_npei_rsl_int_blocks {
@@ -2371,7 +2318,8 @@ union cvmx_npei_rsl_int_blocks {
2371 uint64_t asxpcs0:1; 2318 uint64_t asxpcs0:1;
2372 uint64_t reserved_21_21:1; 2319 uint64_t reserved_21_21:1;
2373 uint64_t pip:1; 2320 uint64_t pip:1;
2374 uint64_t reserved_18_19:2; 2321 uint64_t spx1:1;
2322 uint64_t spx0:1;
2375 uint64_t lmc0:1; 2323 uint64_t lmc0:1;
2376 uint64_t l2c:1; 2324 uint64_t l2c:1;
2377 uint64_t usb1:1; 2325 uint64_t usb1:1;
@@ -2383,7 +2331,7 @@ union cvmx_npei_rsl_int_blocks {
2383 uint64_t ipd:1; 2331 uint64_t ipd:1;
2384 uint64_t reserved_8_8:1; 2332 uint64_t reserved_8_8:1;
2385 uint64_t zip:1; 2333 uint64_t zip:1;
2386 uint64_t reserved_6_6:1; 2334 uint64_t dfa:1;
2387 uint64_t fpa:1; 2335 uint64_t fpa:1;
2388 uint64_t key:1; 2336 uint64_t key:1;
2389 uint64_t npei:1; 2337 uint64_t npei:1;
@@ -2393,37 +2341,8 @@ union cvmx_npei_rsl_int_blocks {
2393 } s; 2341 } s;
2394 struct cvmx_npei_rsl_int_blocks_s cn52xx; 2342 struct cvmx_npei_rsl_int_blocks_s cn52xx;
2395 struct cvmx_npei_rsl_int_blocks_s cn52xxp1; 2343 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2396 struct cvmx_npei_rsl_int_blocks_cn56xx { 2344 struct cvmx_npei_rsl_int_blocks_s cn56xx;
2397 uint64_t reserved_31_63:33; 2345 struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
2398 uint64_t iob:1;
2399 uint64_t lmc1:1;
2400 uint64_t agl:1;
2401 uint64_t reserved_24_27:4;
2402 uint64_t asxpcs1:1;
2403 uint64_t asxpcs0:1;
2404 uint64_t reserved_21_21:1;
2405 uint64_t pip:1;
2406 uint64_t reserved_18_19:2;
2407 uint64_t lmc0:1;
2408 uint64_t l2c:1;
2409 uint64_t reserved_15_15:1;
2410 uint64_t rad:1;
2411 uint64_t usb:1;
2412 uint64_t pow:1;
2413 uint64_t tim:1;
2414 uint64_t pko:1;
2415 uint64_t ipd:1;
2416 uint64_t reserved_8_8:1;
2417 uint64_t zip:1;
2418 uint64_t reserved_6_6:1;
2419 uint64_t fpa:1;
2420 uint64_t key:1;
2421 uint64_t npei:1;
2422 uint64_t gmx1:1;
2423 uint64_t gmx0:1;
2424 uint64_t mio:1;
2425 } cn56xx;
2426 struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
2427}; 2346};
2428 2347
2429union cvmx_npei_scratch_1 { 2348union cvmx_npei_scratch_1 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 22:07:27 -0500