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Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-npei-defs.h')
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npei-defs.h1743
1 files changed, 1742 insertions, 1 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index a3075f733ca5..58114d414356 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2011 Cavium Networks 7 * Copyright (c) 2003-2012 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -140,11 +140,19 @@
140union cvmx_npei_bar1_indexx { 140union cvmx_npei_bar1_indexx {
141 uint32_t u32; 141 uint32_t u32;
142 struct cvmx_npei_bar1_indexx_s { 142 struct cvmx_npei_bar1_indexx_s {
143#ifdef __BIG_ENDIAN_BITFIELD
143 uint32_t reserved_18_31:14; 144 uint32_t reserved_18_31:14;
144 uint32_t addr_idx:14; 145 uint32_t addr_idx:14;
145 uint32_t ca:1; 146 uint32_t ca:1;
146 uint32_t end_swp:2; 147 uint32_t end_swp:2;
147 uint32_t addr_v:1; 148 uint32_t addr_v:1;
149#else
150 uint32_t addr_v:1;
151 uint32_t end_swp:2;
152 uint32_t ca:1;
153 uint32_t addr_idx:14;
154 uint32_t reserved_18_31:14;
155#endif
148 } s; 156 } s;
149 struct cvmx_npei_bar1_indexx_s cn52xx; 157 struct cvmx_npei_bar1_indexx_s cn52xx;
150 struct cvmx_npei_bar1_indexx_s cn52xxp1; 158 struct cvmx_npei_bar1_indexx_s cn52xxp1;
@@ -155,6 +163,7 @@ union cvmx_npei_bar1_indexx {
155union cvmx_npei_bist_status { 163union cvmx_npei_bist_status {
156 uint64_t u64; 164 uint64_t u64;
157 struct cvmx_npei_bist_status_s { 165 struct cvmx_npei_bist_status_s {
166#ifdef __BIG_ENDIAN_BITFIELD
158 uint64_t pkt_rdf:1; 167 uint64_t pkt_rdf:1;
159 uint64_t reserved_60_62:3; 168 uint64_t reserved_60_62:3;
160 uint64_t pcr_gim:1; 169 uint64_t pcr_gim:1;
@@ -204,8 +213,60 @@ union cvmx_npei_bist_status {
204 uint64_t reserved_2_2:1; 213 uint64_t reserved_2_2:1;
205 uint64_t msi:1; 214 uint64_t msi:1;
206 uint64_t ncb_cmd:1; 215 uint64_t ncb_cmd:1;
216#else
217 uint64_t ncb_cmd:1;
218 uint64_t msi:1;
219 uint64_t reserved_2_2:1;
220 uint64_t dif3:1;
221 uint64_t dif2:1;
222 uint64_t dif1:1;
223 uint64_t dif0:1;
224 uint64_t csm1:1;
225 uint64_t csm0:1;
226 uint64_t p2n1_p1:1;
227 uint64_t p2n1_p0:1;
228 uint64_t p2n1_n:1;
229 uint64_t p2n1_c1:1;
230 uint64_t p2n1_c0:1;
231 uint64_t p2n0_p1:1;
232 uint64_t p2n0_p0:1;
233 uint64_t p2n0_n:1;
234 uint64_t p2n0_c1:1;
235 uint64_t p2n0_c0:1;
236 uint64_t p2n0_co:1;
237 uint64_t p2n0_no:1;
238 uint64_t p2n0_po:1;
239 uint64_t p2n1_co:1;
240 uint64_t p2n1_no:1;
241 uint64_t p2n1_po:1;
242 uint64_t cpl_p1:1;
243 uint64_t cpl_p0:1;
244 uint64_t n2p1_o:1;
245 uint64_t n2p1_c:1;
246 uint64_t n2p0_o:1;
247 uint64_t n2p0_c:1;
248 uint64_t reserved_31_31:1;
249 uint64_t d3_pst:1;
250 uint64_t d2_pst:1;
251 uint64_t d1_pst:1;
252 uint64_t d0_pst:1;
253 uint64_t reserved_36_47:12;
254 uint64_t pkt_slm:1;
255 uint64_t pkt_ind:1;
256 uint64_t reserved_50_52:3;
257 uint64_t pcsr_sl:1;
258 uint64_t pcsr_id:1;
259 uint64_t pcsr_cnt:1;
260 uint64_t pcsr_im:1;
261 uint64_t pcsr_int:1;
262 uint64_t pkt_pif:1;
263 uint64_t pcr_gim:1;
264 uint64_t reserved_60_62:3;
265 uint64_t pkt_rdf:1;
266#endif
207 } s; 267 } s;
208 struct cvmx_npei_bist_status_cn52xx { 268 struct cvmx_npei_bist_status_cn52xx {
269#ifdef __BIG_ENDIAN_BITFIELD
209 uint64_t pkt_rdf:1; 270 uint64_t pkt_rdf:1;
210 uint64_t reserved_60_62:3; 271 uint64_t reserved_60_62:3;
211 uint64_t pcr_gim:1; 272 uint64_t pcr_gim:1;
@@ -264,8 +325,69 @@ union cvmx_npei_bist_status {
264 uint64_t dif4:1; 325 uint64_t dif4:1;
265 uint64_t msi:1; 326 uint64_t msi:1;
266 uint64_t ncb_cmd:1; 327 uint64_t ncb_cmd:1;
328#else
329 uint64_t ncb_cmd:1;
330 uint64_t msi:1;
331 uint64_t dif4:1;
332 uint64_t dif3:1;
333 uint64_t dif2:1;
334 uint64_t dif1:1;
335 uint64_t dif0:1;
336 uint64_t csm1:1;
337 uint64_t csm0:1;
338 uint64_t p2n1_p1:1;
339 uint64_t p2n1_p0:1;
340 uint64_t p2n1_n:1;
341 uint64_t p2n1_c1:1;
342 uint64_t p2n1_c0:1;
343 uint64_t p2n0_p1:1;
344 uint64_t p2n0_p0:1;
345 uint64_t p2n0_n:1;
346 uint64_t p2n0_c1:1;
347 uint64_t p2n0_c0:1;
348 uint64_t p2n0_co:1;
349 uint64_t p2n0_no:1;
350 uint64_t p2n0_po:1;
351 uint64_t p2n1_co:1;
352 uint64_t p2n1_no:1;
353 uint64_t p2n1_po:1;
354 uint64_t cpl_p1:1;
355 uint64_t cpl_p0:1;
356 uint64_t n2p1_o:1;
357 uint64_t n2p1_c:1;
358 uint64_t n2p0_o:1;
359 uint64_t n2p0_c:1;
360 uint64_t d4_pst:1;
361 uint64_t d3_pst:1;
362 uint64_t d2_pst:1;
363 uint64_t d1_pst:1;
364 uint64_t d0_pst:1;
365 uint64_t reserved_36_39:4;
366 uint64_t ds_mem:1;
367 uint64_t d4_mem:1;
368 uint64_t d3_mem:1;
369 uint64_t d2_mem:1;
370 uint64_t d1_mem:1;
371 uint64_t d0_mem:1;
372 uint64_t pkt_pop1:1;
373 uint64_t pkt_pop0:1;
374 uint64_t reserved_48_49:2;
375 uint64_t pkt_pof:1;
376 uint64_t pkt_pfm:1;
377 uint64_t pkt_imem:1;
378 uint64_t pcsr_sl:1;
379 uint64_t pcsr_id:1;
380 uint64_t pcsr_cnt:1;
381 uint64_t pcsr_im:1;
382 uint64_t pcsr_int:1;
383 uint64_t pkt_pif:1;
384 uint64_t pcr_gim:1;
385 uint64_t reserved_60_62:3;
386 uint64_t pkt_rdf:1;
387#endif
267 } cn52xx; 388 } cn52xx;
268 struct cvmx_npei_bist_status_cn52xxp1 { 389 struct cvmx_npei_bist_status_cn52xxp1 {
390#ifdef __BIG_ENDIAN_BITFIELD
269 uint64_t reserved_46_63:18; 391 uint64_t reserved_46_63:18;
270 uint64_t d0_mem0:1; 392 uint64_t d0_mem0:1;
271 uint64_t d1_mem1:1; 393 uint64_t d1_mem1:1;
@@ -313,9 +435,59 @@ union cvmx_npei_bist_status {
313 uint64_t dr3_mem:1; 435 uint64_t dr3_mem:1;
314 uint64_t msi:1; 436 uint64_t msi:1;
315 uint64_t ncb_cmd:1; 437 uint64_t ncb_cmd:1;
438#else
439 uint64_t ncb_cmd:1;
440 uint64_t msi:1;
441 uint64_t dr3_mem:1;
442 uint64_t dif3:1;
443 uint64_t dif2:1;
444 uint64_t dif1:1;
445 uint64_t dif0:1;
446 uint64_t csm1:1;
447 uint64_t csm0:1;
448 uint64_t p2n1_p1:1;
449 uint64_t p2n1_p0:1;
450 uint64_t p2n1_n:1;
451 uint64_t p2n1_c1:1;
452 uint64_t p2n1_c0:1;
453 uint64_t p2n0_p1:1;
454 uint64_t p2n0_p0:1;
455 uint64_t p2n0_n:1;
456 uint64_t p2n0_c1:1;
457 uint64_t p2n0_c0:1;
458 uint64_t p2n0_co:1;
459 uint64_t p2n0_no:1;
460 uint64_t p2n0_po:1;
461 uint64_t p2n1_co:1;
462 uint64_t p2n1_no:1;
463 uint64_t p2n1_po:1;
464 uint64_t cpl_p1:1;
465 uint64_t cpl_p0:1;
466 uint64_t n2p1_o:1;
467 uint64_t n2p1_c:1;
468 uint64_t n2p0_o:1;
469 uint64_t n2p0_c:1;
470 uint64_t dr2_mem:1;
471 uint64_t d3_pst:1;
472 uint64_t d2_pst:1;
473 uint64_t d1_pst:1;
474 uint64_t d0_pst:1;
475 uint64_t dr1_mem:1;
476 uint64_t d3_mem:1;
477 uint64_t d2_mem:1;
478 uint64_t d1_mem:1;
479 uint64_t d0_mem:1;
480 uint64_t dr0_mem:1;
481 uint64_t d3_mem3:1;
482 uint64_t d2_mem2:1;
483 uint64_t d1_mem1:1;
484 uint64_t d0_mem0:1;
485 uint64_t reserved_46_63:18;
486#endif
316 } cn52xxp1; 487 } cn52xxp1;
317 struct cvmx_npei_bist_status_cn52xx cn56xx; 488 struct cvmx_npei_bist_status_cn52xx cn56xx;
318 struct cvmx_npei_bist_status_cn56xxp1 { 489 struct cvmx_npei_bist_status_cn56xxp1 {
490#ifdef __BIG_ENDIAN_BITFIELD
319 uint64_t reserved_58_63:6; 491 uint64_t reserved_58_63:6;
320 uint64_t pcsr_int:1; 492 uint64_t pcsr_int:1;
321 uint64_t pcsr_im:1; 493 uint64_t pcsr_im:1;
@@ -375,12 +547,74 @@ union cvmx_npei_bist_status {
375 uint64_t dif4:1; 547 uint64_t dif4:1;
376 uint64_t msi:1; 548 uint64_t msi:1;
377 uint64_t ncb_cmd:1; 549 uint64_t ncb_cmd:1;
550#else
551 uint64_t ncb_cmd:1;
552 uint64_t msi:1;
553 uint64_t dif4:1;
554 uint64_t dif3:1;
555 uint64_t dif2:1;
556 uint64_t dif1:1;
557 uint64_t dif0:1;
558 uint64_t csm1:1;
559 uint64_t csm0:1;
560 uint64_t p2n1_p1:1;
561 uint64_t p2n1_p0:1;
562 uint64_t p2n1_n:1;
563 uint64_t p2n1_c1:1;
564 uint64_t p2n1_c0:1;
565 uint64_t p2n0_p1:1;
566 uint64_t p2n0_p0:1;
567 uint64_t p2n0_n:1;
568 uint64_t p2n0_c1:1;
569 uint64_t p2n0_c0:1;
570 uint64_t p2n0_co:1;
571 uint64_t p2n0_no:1;
572 uint64_t p2n0_po:1;
573 uint64_t p2n1_co:1;
574 uint64_t p2n1_no:1;
575 uint64_t p2n1_po:1;
576 uint64_t cpl_p1:1;
577 uint64_t cpl_p0:1;
578 uint64_t n2p1_o:1;
579 uint64_t n2p1_c:1;
580 uint64_t n2p0_o:1;
581 uint64_t n2p0_c:1;
582 uint64_t d4_pst:1;
583 uint64_t d3_pst:1;
584 uint64_t d2_pst:1;
585 uint64_t d1_pst:1;
586 uint64_t d0_pst:1;
587 uint64_t d4_mem:1;
588 uint64_t d3_mem:1;
589 uint64_t d2_mem:1;
590 uint64_t d1_mem:1;
591 uint64_t d0_mem:1;
592 uint64_t pkt_s1:1;
593 uint64_t pkt_s0:1;
594 uint64_t pkt_i1:1;
595 uint64_t pkt_i0:1;
596 uint64_t pkt_out:1;
597 uint64_t pkt_oif:1;
598 uint64_t pkt_odf:1;
599 uint64_t pkt_slm:1;
600 uint64_t pkt_ind:1;
601 uint64_t pkt_cntm:1;
602 uint64_t pkt_imem:1;
603 uint64_t pkt_pout:1;
604 uint64_t pcsr_sl:1;
605 uint64_t pcsr_id:1;
606 uint64_t pcsr_cnt:1;
607 uint64_t pcsr_im:1;
608 uint64_t pcsr_int:1;
609 uint64_t reserved_58_63:6;
610#endif
378 } cn56xxp1; 611 } cn56xxp1;
379}; 612};
380 613
381union cvmx_npei_bist_status2 { 614union cvmx_npei_bist_status2 {
382 uint64_t u64; 615 uint64_t u64;
383 struct cvmx_npei_bist_status2_s { 616 struct cvmx_npei_bist_status2_s {
617#ifdef __BIG_ENDIAN_BITFIELD
384 uint64_t reserved_14_63:50; 618 uint64_t reserved_14_63:50;
385 uint64_t prd_tag:1; 619 uint64_t prd_tag:1;
386 uint64_t prd_st0:1; 620 uint64_t prd_st0:1;
@@ -396,6 +630,23 @@ union cvmx_npei_bist_status2 {
396 uint64_t pkt_gd:1; 630 uint64_t pkt_gd:1;
397 uint64_t pkt_gl:1; 631 uint64_t pkt_gl:1;
398 uint64_t pkt_blk:1; 632 uint64_t pkt_blk:1;
633#else
634 uint64_t pkt_blk:1;
635 uint64_t pkt_gl:1;
636 uint64_t pkt_gd:1;
637 uint64_t psc_p1:1;
638 uint64_t psc_p0:1;
639 uint64_t pkt_rd:1;
640 uint64_t nwe_wr1:1;
641 uint64_t nwe_wr0:1;
642 uint64_t nwe_st:1;
643 uint64_t nrd_st:1;
644 uint64_t prd_err:1;
645 uint64_t prd_st1:1;
646 uint64_t prd_st0:1;
647 uint64_t prd_tag:1;
648 uint64_t reserved_14_63:50;
649#endif
399 } s; 650 } s;
400 struct cvmx_npei_bist_status2_s cn52xx; 651 struct cvmx_npei_bist_status2_s cn52xx;
401 struct cvmx_npei_bist_status2_s cn56xx; 652 struct cvmx_npei_bist_status2_s cn56xx;
@@ -404,6 +655,7 @@ union cvmx_npei_bist_status2 {
404union cvmx_npei_ctl_port0 { 655union cvmx_npei_ctl_port0 {
405 uint64_t u64; 656 uint64_t u64;
406 struct cvmx_npei_ctl_port0_s { 657 struct cvmx_npei_ctl_port0_s {
658#ifdef __BIG_ENDIAN_BITFIELD
407 uint64_t reserved_21_63:43; 659 uint64_t reserved_21_63:43;
408 uint64_t waitl_com:1; 660 uint64_t waitl_com:1;
409 uint64_t intd:1; 661 uint64_t intd:1;
@@ -421,6 +673,25 @@ union cvmx_npei_ctl_port0 {
421 uint64_t bar2_esx:2; 673 uint64_t bar2_esx:2;
422 uint64_t bar2_cax:1; 674 uint64_t bar2_cax:1;
423 uint64_t wait_com:1; 675 uint64_t wait_com:1;
676#else
677 uint64_t wait_com:1;
678 uint64_t bar2_cax:1;
679 uint64_t bar2_esx:2;
680 uint64_t bar2_enb:1;
681 uint64_t ptlp_ro:1;
682 uint64_t reserved_6_6:1;
683 uint64_t ctlp_ro:1;
684 uint64_t inta_map:2;
685 uint64_t intb_map:2;
686 uint64_t intc_map:2;
687 uint64_t intd_map:2;
688 uint64_t inta:1;
689 uint64_t intb:1;
690 uint64_t intc:1;
691 uint64_t intd:1;
692 uint64_t waitl_com:1;
693 uint64_t reserved_21_63:43;
694#endif
424 } s; 695 } s;
425 struct cvmx_npei_ctl_port0_s cn52xx; 696 struct cvmx_npei_ctl_port0_s cn52xx;
426 struct cvmx_npei_ctl_port0_s cn52xxp1; 697 struct cvmx_npei_ctl_port0_s cn52xxp1;
@@ -431,6 +702,7 @@ union cvmx_npei_ctl_port0 {
431union cvmx_npei_ctl_port1 { 702union cvmx_npei_ctl_port1 {
432 uint64_t u64; 703 uint64_t u64;
433 struct cvmx_npei_ctl_port1_s { 704 struct cvmx_npei_ctl_port1_s {
705#ifdef __BIG_ENDIAN_BITFIELD
434 uint64_t reserved_21_63:43; 706 uint64_t reserved_21_63:43;
435 uint64_t waitl_com:1; 707 uint64_t waitl_com:1;
436 uint64_t intd:1; 708 uint64_t intd:1;
@@ -448,6 +720,25 @@ union cvmx_npei_ctl_port1 {
448 uint64_t bar2_esx:2; 720 uint64_t bar2_esx:2;
449 uint64_t bar2_cax:1; 721 uint64_t bar2_cax:1;
450 uint64_t wait_com:1; 722 uint64_t wait_com:1;
723#else
724 uint64_t wait_com:1;
725 uint64_t bar2_cax:1;
726 uint64_t bar2_esx:2;
727 uint64_t bar2_enb:1;
728 uint64_t ptlp_ro:1;
729 uint64_t reserved_6_6:1;
730 uint64_t ctlp_ro:1;
731 uint64_t inta_map:2;
732 uint64_t intb_map:2;
733 uint64_t intc_map:2;
734 uint64_t intd_map:2;
735 uint64_t inta:1;
736 uint64_t intb:1;
737 uint64_t intc:1;
738 uint64_t intd:1;
739 uint64_t waitl_com:1;
740 uint64_t reserved_21_63:43;
741#endif
451 } s; 742 } s;
452 struct cvmx_npei_ctl_port1_s cn52xx; 743 struct cvmx_npei_ctl_port1_s cn52xx;
453 struct cvmx_npei_ctl_port1_s cn52xxp1; 744 struct cvmx_npei_ctl_port1_s cn52xxp1;
@@ -458,6 +749,7 @@ union cvmx_npei_ctl_port1 {
458union cvmx_npei_ctl_status { 749union cvmx_npei_ctl_status {
459 uint64_t u64; 750 uint64_t u64;
460 struct cvmx_npei_ctl_status_s { 751 struct cvmx_npei_ctl_status_s {
752#ifdef __BIG_ENDIAN_BITFIELD
461 uint64_t reserved_44_63:20; 753 uint64_t reserved_44_63:20;
462 uint64_t p1_ntags:6; 754 uint64_t p1_ntags:6;
463 uint64_t p0_ntags:6; 755 uint64_t p0_ntags:6;
@@ -468,9 +760,22 @@ union cvmx_npei_ctl_status {
468 uint64_t pkt_bp:4; 760 uint64_t pkt_bp:4;
469 uint64_t host_mode:1; 761 uint64_t host_mode:1;
470 uint64_t chip_rev:8; 762 uint64_t chip_rev:8;
763#else
764 uint64_t chip_rev:8;
765 uint64_t host_mode:1;
766 uint64_t pkt_bp:4;
767 uint64_t arb:1;
768 uint64_t lnk_rst:1;
769 uint64_t ring_en:1;
770 uint64_t cfg_rtry:16;
771 uint64_t p0_ntags:6;
772 uint64_t p1_ntags:6;
773 uint64_t reserved_44_63:20;
774#endif
471 } s; 775 } s;
472 struct cvmx_npei_ctl_status_s cn52xx; 776 struct cvmx_npei_ctl_status_s cn52xx;
473 struct cvmx_npei_ctl_status_cn52xxp1 { 777 struct cvmx_npei_ctl_status_cn52xxp1 {
778#ifdef __BIG_ENDIAN_BITFIELD
474 uint64_t reserved_44_63:20; 779 uint64_t reserved_44_63:20;
475 uint64_t p1_ntags:6; 780 uint64_t p1_ntags:6;
476 uint64_t p0_ntags:6; 781 uint64_t p0_ntags:6;
@@ -481,21 +786,43 @@ union cvmx_npei_ctl_status {
481 uint64_t reserved_9_12:4; 786 uint64_t reserved_9_12:4;
482 uint64_t host_mode:1; 787 uint64_t host_mode:1;
483 uint64_t chip_rev:8; 788 uint64_t chip_rev:8;
789#else
790 uint64_t chip_rev:8;
791 uint64_t host_mode:1;
792 uint64_t reserved_9_12:4;
793 uint64_t arb:1;
794 uint64_t lnk_rst:1;
795 uint64_t reserved_15_15:1;
796 uint64_t cfg_rtry:16;
797 uint64_t p0_ntags:6;
798 uint64_t p1_ntags:6;
799 uint64_t reserved_44_63:20;
800#endif
484 } cn52xxp1; 801 } cn52xxp1;
485 struct cvmx_npei_ctl_status_s cn56xx; 802 struct cvmx_npei_ctl_status_s cn56xx;
486 struct cvmx_npei_ctl_status_cn56xxp1 { 803 struct cvmx_npei_ctl_status_cn56xxp1 {
804#ifdef __BIG_ENDIAN_BITFIELD
487 uint64_t reserved_15_63:49; 805 uint64_t reserved_15_63:49;
488 uint64_t lnk_rst:1; 806 uint64_t lnk_rst:1;
489 uint64_t arb:1; 807 uint64_t arb:1;
490 uint64_t pkt_bp:4; 808 uint64_t pkt_bp:4;
491 uint64_t host_mode:1; 809 uint64_t host_mode:1;
492 uint64_t chip_rev:8; 810 uint64_t chip_rev:8;
811#else
812 uint64_t chip_rev:8;
813 uint64_t host_mode:1;
814 uint64_t pkt_bp:4;
815 uint64_t arb:1;
816 uint64_t lnk_rst:1;
817 uint64_t reserved_15_63:49;
818#endif
493 } cn56xxp1; 819 } cn56xxp1;
494}; 820};
495 821
496union cvmx_npei_ctl_status2 { 822union cvmx_npei_ctl_status2 {
497 uint64_t u64; 823 uint64_t u64;
498 struct cvmx_npei_ctl_status2_s { 824 struct cvmx_npei_ctl_status2_s {
825#ifdef __BIG_ENDIAN_BITFIELD
499 uint64_t reserved_16_63:48; 826 uint64_t reserved_16_63:48;
500 uint64_t mps:1; 827 uint64_t mps:1;
501 uint64_t mrrs:3; 828 uint64_t mrrs:3;
@@ -507,6 +834,19 @@ union cvmx_npei_ctl_status2 {
507 uint64_t c1_b0_d:1; 834 uint64_t c1_b0_d:1;
508 uint64_t c0_wi_d:1; 835 uint64_t c0_wi_d:1;
509 uint64_t c0_b0_d:1; 836 uint64_t c0_b0_d:1;
837#else
838 uint64_t c0_b0_d:1;
839 uint64_t c0_wi_d:1;
840 uint64_t c1_b0_d:1;
841 uint64_t c1_wi_d:1;
842 uint64_t c0_b1_s:3;
843 uint64_t c1_b1_s:3;
844 uint64_t c0_w_flt:1;
845 uint64_t c1_w_flt:1;
846 uint64_t mrrs:3;
847 uint64_t mps:1;
848 uint64_t reserved_16_63:48;
849#endif
510 } s; 850 } s;
511 struct cvmx_npei_ctl_status2_s cn52xx; 851 struct cvmx_npei_ctl_status2_s cn52xx;
512 struct cvmx_npei_ctl_status2_s cn52xxp1; 852 struct cvmx_npei_ctl_status2_s cn52xxp1;
@@ -517,11 +857,19 @@ union cvmx_npei_ctl_status2 {
517union cvmx_npei_data_out_cnt { 857union cvmx_npei_data_out_cnt {
518 uint64_t u64; 858 uint64_t u64;
519 struct cvmx_npei_data_out_cnt_s { 859 struct cvmx_npei_data_out_cnt_s {
860#ifdef __BIG_ENDIAN_BITFIELD
520 uint64_t reserved_44_63:20; 861 uint64_t reserved_44_63:20;
521 uint64_t p1_ucnt:16; 862 uint64_t p1_ucnt:16;
522 uint64_t p1_fcnt:6; 863 uint64_t p1_fcnt:6;
523 uint64_t p0_ucnt:16; 864 uint64_t p0_ucnt:16;
524 uint64_t p0_fcnt:6; 865 uint64_t p0_fcnt:6;
866#else
867 uint64_t p0_fcnt:6;
868 uint64_t p0_ucnt:16;
869 uint64_t p1_fcnt:6;
870 uint64_t p1_ucnt:16;
871 uint64_t reserved_44_63:20;
872#endif
525 } s; 873 } s;
526 struct cvmx_npei_data_out_cnt_s cn52xx; 874 struct cvmx_npei_data_out_cnt_s cn52xx;
527 struct cvmx_npei_data_out_cnt_s cn52xxp1; 875 struct cvmx_npei_data_out_cnt_s cn52xxp1;
@@ -532,6 +880,7 @@ union cvmx_npei_data_out_cnt {
532union cvmx_npei_dbg_data { 880union cvmx_npei_dbg_data {
533 uint64_t u64; 881 uint64_t u64;
534 struct cvmx_npei_dbg_data_s { 882 struct cvmx_npei_dbg_data_s {
883#ifdef __BIG_ENDIAN_BITFIELD
535 uint64_t reserved_28_63:36; 884 uint64_t reserved_28_63:36;
536 uint64_t qlm0_rev_lanes:1; 885 uint64_t qlm0_rev_lanes:1;
537 uint64_t reserved_25_26:2; 886 uint64_t reserved_25_26:2;
@@ -539,8 +888,18 @@ union cvmx_npei_dbg_data {
539 uint64_t c_mul:5; 888 uint64_t c_mul:5;
540 uint64_t dsel_ext:1; 889 uint64_t dsel_ext:1;
541 uint64_t data:17; 890 uint64_t data:17;
891#else
892 uint64_t data:17;
893 uint64_t dsel_ext:1;
894 uint64_t c_mul:5;
895 uint64_t qlm1_spd:2;
896 uint64_t reserved_25_26:2;
897 uint64_t qlm0_rev_lanes:1;
898 uint64_t reserved_28_63:36;
899#endif
542 } s; 900 } s;
543 struct cvmx_npei_dbg_data_cn52xx { 901 struct cvmx_npei_dbg_data_cn52xx {
902#ifdef __BIG_ENDIAN_BITFIELD
544 uint64_t reserved_29_63:35; 903 uint64_t reserved_29_63:35;
545 uint64_t qlm0_link_width:1; 904 uint64_t qlm0_link_width:1;
546 uint64_t qlm0_rev_lanes:1; 905 uint64_t qlm0_rev_lanes:1;
@@ -549,9 +908,20 @@ union cvmx_npei_dbg_data {
549 uint64_t c_mul:5; 908 uint64_t c_mul:5;
550 uint64_t dsel_ext:1; 909 uint64_t dsel_ext:1;
551 uint64_t data:17; 910 uint64_t data:17;
911#else
912 uint64_t data:17;
913 uint64_t dsel_ext:1;
914 uint64_t c_mul:5;
915 uint64_t qlm1_spd:2;
916 uint64_t qlm1_mode:2;
917 uint64_t qlm0_rev_lanes:1;
918 uint64_t qlm0_link_width:1;
919 uint64_t reserved_29_63:35;
920#endif
552 } cn52xx; 921 } cn52xx;
553 struct cvmx_npei_dbg_data_cn52xx cn52xxp1; 922 struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
554 struct cvmx_npei_dbg_data_cn56xx { 923 struct cvmx_npei_dbg_data_cn56xx {
924#ifdef __BIG_ENDIAN_BITFIELD
555 uint64_t reserved_29_63:35; 925 uint64_t reserved_29_63:35;
556 uint64_t qlm2_rev_lanes:1; 926 uint64_t qlm2_rev_lanes:1;
557 uint64_t qlm0_rev_lanes:1; 927 uint64_t qlm0_rev_lanes:1;
@@ -560,6 +930,16 @@ union cvmx_npei_dbg_data {
560 uint64_t c_mul:5; 930 uint64_t c_mul:5;
561 uint64_t dsel_ext:1; 931 uint64_t dsel_ext:1;
562 uint64_t data:17; 932 uint64_t data:17;
933#else
934 uint64_t data:17;
935 uint64_t dsel_ext:1;
936 uint64_t c_mul:5;
937 uint64_t qlm1_spd:2;
938 uint64_t qlm3_spd:2;
939 uint64_t qlm0_rev_lanes:1;
940 uint64_t qlm2_rev_lanes:1;
941 uint64_t reserved_29_63:35;
942#endif
563 } cn56xx; 943 } cn56xx;
564 struct cvmx_npei_dbg_data_cn56xx cn56xxp1; 944 struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
565}; 945};
@@ -567,8 +947,13 @@ union cvmx_npei_dbg_data {
567union cvmx_npei_dbg_select { 947union cvmx_npei_dbg_select {
568 uint64_t u64; 948 uint64_t u64;
569 struct cvmx_npei_dbg_select_s { 949 struct cvmx_npei_dbg_select_s {
950#ifdef __BIG_ENDIAN_BITFIELD
570 uint64_t reserved_16_63:48; 951 uint64_t reserved_16_63:48;
571 uint64_t dbg_sel:16; 952 uint64_t dbg_sel:16;
953#else
954 uint64_t dbg_sel:16;
955 uint64_t reserved_16_63:48;
956#endif
572 } s; 957 } s;
573 struct cvmx_npei_dbg_select_s cn52xx; 958 struct cvmx_npei_dbg_select_s cn52xx;
574 struct cvmx_npei_dbg_select_s cn52xxp1; 959 struct cvmx_npei_dbg_select_s cn52xxp1;
@@ -579,9 +964,15 @@ union cvmx_npei_dbg_select {
579union cvmx_npei_dmax_counts { 964union cvmx_npei_dmax_counts {
580 uint64_t u64; 965 uint64_t u64;
581 struct cvmx_npei_dmax_counts_s { 966 struct cvmx_npei_dmax_counts_s {
967#ifdef __BIG_ENDIAN_BITFIELD
582 uint64_t reserved_39_63:25; 968 uint64_t reserved_39_63:25;
583 uint64_t fcnt:7; 969 uint64_t fcnt:7;
584 uint64_t dbell:32; 970 uint64_t dbell:32;
971#else
972 uint64_t dbell:32;
973 uint64_t fcnt:7;
974 uint64_t reserved_39_63:25;
975#endif
585 } s; 976 } s;
586 struct cvmx_npei_dmax_counts_s cn52xx; 977 struct cvmx_npei_dmax_counts_s cn52xx;
587 struct cvmx_npei_dmax_counts_s cn52xxp1; 978 struct cvmx_npei_dmax_counts_s cn52xxp1;
@@ -592,8 +983,13 @@ union cvmx_npei_dmax_counts {
592union cvmx_npei_dmax_dbell { 983union cvmx_npei_dmax_dbell {
593 uint32_t u32; 984 uint32_t u32;
594 struct cvmx_npei_dmax_dbell_s { 985 struct cvmx_npei_dmax_dbell_s {
986#ifdef __BIG_ENDIAN_BITFIELD
595 uint32_t reserved_16_31:16; 987 uint32_t reserved_16_31:16;
596 uint32_t dbell:16; 988 uint32_t dbell:16;
989#else
990 uint32_t dbell:16;
991 uint32_t reserved_16_31:16;
992#endif
597 } s; 993 } s;
598 struct cvmx_npei_dmax_dbell_s cn52xx; 994 struct cvmx_npei_dmax_dbell_s cn52xx;
599 struct cvmx_npei_dmax_dbell_s cn52xxp1; 995 struct cvmx_npei_dmax_dbell_s cn52xxp1;
@@ -604,16 +1000,29 @@ union cvmx_npei_dmax_dbell {
604union cvmx_npei_dmax_ibuff_saddr { 1000union cvmx_npei_dmax_ibuff_saddr {
605 uint64_t u64; 1001 uint64_t u64;
606 struct cvmx_npei_dmax_ibuff_saddr_s { 1002 struct cvmx_npei_dmax_ibuff_saddr_s {
1003#ifdef __BIG_ENDIAN_BITFIELD
607 uint64_t reserved_37_63:27; 1004 uint64_t reserved_37_63:27;
608 uint64_t idle:1; 1005 uint64_t idle:1;
609 uint64_t saddr:29; 1006 uint64_t saddr:29;
610 uint64_t reserved_0_6:7; 1007 uint64_t reserved_0_6:7;
1008#else
1009 uint64_t reserved_0_6:7;
1010 uint64_t saddr:29;
1011 uint64_t idle:1;
1012 uint64_t reserved_37_63:27;
1013#endif
611 } s; 1014 } s;
612 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx; 1015 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
613 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 { 1016 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
1017#ifdef __BIG_ENDIAN_BITFIELD
614 uint64_t reserved_36_63:28; 1018 uint64_t reserved_36_63:28;
615 uint64_t saddr:29; 1019 uint64_t saddr:29;
616 uint64_t reserved_0_6:7; 1020 uint64_t reserved_0_6:7;
1021#else
1022 uint64_t reserved_0_6:7;
1023 uint64_t saddr:29;
1024 uint64_t reserved_36_63:28;
1025#endif
617 } cn52xxp1; 1026 } cn52xxp1;
618 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; 1027 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
619 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1; 1028 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
@@ -622,8 +1031,13 @@ union cvmx_npei_dmax_ibuff_saddr {
622union cvmx_npei_dmax_naddr { 1031union cvmx_npei_dmax_naddr {
623 uint64_t u64; 1032 uint64_t u64;
624 struct cvmx_npei_dmax_naddr_s { 1033 struct cvmx_npei_dmax_naddr_s {
1034#ifdef __BIG_ENDIAN_BITFIELD
625 uint64_t reserved_36_63:28; 1035 uint64_t reserved_36_63:28;
626 uint64_t addr:36; 1036 uint64_t addr:36;
1037#else
1038 uint64_t addr:36;
1039 uint64_t reserved_36_63:28;
1040#endif
627 } s; 1041 } s;
628 struct cvmx_npei_dmax_naddr_s cn52xx; 1042 struct cvmx_npei_dmax_naddr_s cn52xx;
629 struct cvmx_npei_dmax_naddr_s cn52xxp1; 1043 struct cvmx_npei_dmax_naddr_s cn52xxp1;
@@ -634,8 +1048,13 @@ union cvmx_npei_dmax_naddr {
634union cvmx_npei_dma0_int_level { 1048union cvmx_npei_dma0_int_level {
635 uint64_t u64; 1049 uint64_t u64;
636 struct cvmx_npei_dma0_int_level_s { 1050 struct cvmx_npei_dma0_int_level_s {
1051#ifdef __BIG_ENDIAN_BITFIELD
637 uint64_t time:32; 1052 uint64_t time:32;
638 uint64_t cnt:32; 1053 uint64_t cnt:32;
1054#else
1055 uint64_t cnt:32;
1056 uint64_t time:32;
1057#endif
639 } s; 1058 } s;
640 struct cvmx_npei_dma0_int_level_s cn52xx; 1059 struct cvmx_npei_dma0_int_level_s cn52xx;
641 struct cvmx_npei_dma0_int_level_s cn52xxp1; 1060 struct cvmx_npei_dma0_int_level_s cn52xxp1;
@@ -646,8 +1065,13 @@ union cvmx_npei_dma0_int_level {
646union cvmx_npei_dma1_int_level { 1065union cvmx_npei_dma1_int_level {
647 uint64_t u64; 1066 uint64_t u64;
648 struct cvmx_npei_dma1_int_level_s { 1067 struct cvmx_npei_dma1_int_level_s {
1068#ifdef __BIG_ENDIAN_BITFIELD
649 uint64_t time:32; 1069 uint64_t time:32;
650 uint64_t cnt:32; 1070 uint64_t cnt:32;
1071#else
1072 uint64_t cnt:32;
1073 uint64_t time:32;
1074#endif
651 } s; 1075 } s;
652 struct cvmx_npei_dma1_int_level_s cn52xx; 1076 struct cvmx_npei_dma1_int_level_s cn52xx;
653 struct cvmx_npei_dma1_int_level_s cn52xxp1; 1077 struct cvmx_npei_dma1_int_level_s cn52xxp1;
@@ -658,8 +1082,13 @@ union cvmx_npei_dma1_int_level {
658union cvmx_npei_dma_cnts { 1082union cvmx_npei_dma_cnts {
659 uint64_t u64; 1083 uint64_t u64;
660 struct cvmx_npei_dma_cnts_s { 1084 struct cvmx_npei_dma_cnts_s {
1085#ifdef __BIG_ENDIAN_BITFIELD
661 uint64_t dma1:32; 1086 uint64_t dma1:32;
662 uint64_t dma0:32; 1087 uint64_t dma0:32;
1088#else
1089 uint64_t dma0:32;
1090 uint64_t dma1:32;
1091#endif
663 } s; 1092 } s;
664 struct cvmx_npei_dma_cnts_s cn52xx; 1093 struct cvmx_npei_dma_cnts_s cn52xx;
665 struct cvmx_npei_dma_cnts_s cn52xxp1; 1094 struct cvmx_npei_dma_cnts_s cn52xxp1;
@@ -670,6 +1099,7 @@ union cvmx_npei_dma_cnts {
670union cvmx_npei_dma_control { 1099union cvmx_npei_dma_control {
671 uint64_t u64; 1100 uint64_t u64;
672 struct cvmx_npei_dma_control_s { 1101 struct cvmx_npei_dma_control_s {
1102#ifdef __BIG_ENDIAN_BITFIELD
673 uint64_t reserved_40_63:24; 1103 uint64_t reserved_40_63:24;
674 uint64_t p_32b_m:1; 1104 uint64_t p_32b_m:1;
675 uint64_t dma4_enb:1; 1105 uint64_t dma4_enb:1;
@@ -687,9 +1117,29 @@ union cvmx_npei_dma_control {
687 uint64_t o_es:2; 1117 uint64_t o_es:2;
688 uint64_t o_mode:1; 1118 uint64_t o_mode:1;
689 uint64_t csize:14; 1119 uint64_t csize:14;
1120#else
1121 uint64_t csize:14;
1122 uint64_t o_mode:1;
1123 uint64_t o_es:2;
1124 uint64_t o_ns:1;
1125 uint64_t o_ro:1;
1126 uint64_t o_add1:1;
1127 uint64_t fpa_que:3;
1128 uint64_t dwb_ichk:9;
1129 uint64_t dwb_denb:1;
1130 uint64_t b0_lend:1;
1131 uint64_t dma0_enb:1;
1132 uint64_t dma1_enb:1;
1133 uint64_t dma2_enb:1;
1134 uint64_t dma3_enb:1;
1135 uint64_t dma4_enb:1;
1136 uint64_t p_32b_m:1;
1137 uint64_t reserved_40_63:24;
1138#endif
690 } s; 1139 } s;
691 struct cvmx_npei_dma_control_s cn52xx; 1140 struct cvmx_npei_dma_control_s cn52xx;
692 struct cvmx_npei_dma_control_cn52xxp1 { 1141 struct cvmx_npei_dma_control_cn52xxp1 {
1142#ifdef __BIG_ENDIAN_BITFIELD
693 uint64_t reserved_38_63:26; 1143 uint64_t reserved_38_63:26;
694 uint64_t dma3_enb:1; 1144 uint64_t dma3_enb:1;
695 uint64_t dma2_enb:1; 1145 uint64_t dma2_enb:1;
@@ -705,9 +1155,27 @@ union cvmx_npei_dma_control {
705 uint64_t o_es:2; 1155 uint64_t o_es:2;
706 uint64_t o_mode:1; 1156 uint64_t o_mode:1;
707 uint64_t csize:14; 1157 uint64_t csize:14;
1158#else
1159 uint64_t csize:14;
1160 uint64_t o_mode:1;
1161 uint64_t o_es:2;
1162 uint64_t o_ns:1;
1163 uint64_t o_ro:1;
1164 uint64_t o_add1:1;
1165 uint64_t fpa_que:3;
1166 uint64_t dwb_ichk:9;
1167 uint64_t dwb_denb:1;
1168 uint64_t b0_lend:1;
1169 uint64_t dma0_enb:1;
1170 uint64_t dma1_enb:1;
1171 uint64_t dma2_enb:1;
1172 uint64_t dma3_enb:1;
1173 uint64_t reserved_38_63:26;
1174#endif
708 } cn52xxp1; 1175 } cn52xxp1;
709 struct cvmx_npei_dma_control_s cn56xx; 1176 struct cvmx_npei_dma_control_s cn56xx;
710 struct cvmx_npei_dma_control_cn56xxp1 { 1177 struct cvmx_npei_dma_control_cn56xxp1 {
1178#ifdef __BIG_ENDIAN_BITFIELD
711 uint64_t reserved_39_63:25; 1179 uint64_t reserved_39_63:25;
712 uint64_t dma4_enb:1; 1180 uint64_t dma4_enb:1;
713 uint64_t dma3_enb:1; 1181 uint64_t dma3_enb:1;
@@ -724,12 +1192,31 @@ union cvmx_npei_dma_control {
724 uint64_t o_es:2; 1192 uint64_t o_es:2;
725 uint64_t o_mode:1; 1193 uint64_t o_mode:1;
726 uint64_t csize:14; 1194 uint64_t csize:14;
1195#else
1196 uint64_t csize:14;
1197 uint64_t o_mode:1;
1198 uint64_t o_es:2;
1199 uint64_t o_ns:1;
1200 uint64_t o_ro:1;
1201 uint64_t o_add1:1;
1202 uint64_t fpa_que:3;
1203 uint64_t dwb_ichk:9;
1204 uint64_t dwb_denb:1;
1205 uint64_t b0_lend:1;
1206 uint64_t dma0_enb:1;
1207 uint64_t dma1_enb:1;
1208 uint64_t dma2_enb:1;
1209 uint64_t dma3_enb:1;
1210 uint64_t dma4_enb:1;
1211 uint64_t reserved_39_63:25;
1212#endif
727 } cn56xxp1; 1213 } cn56xxp1;
728}; 1214};
729 1215
730union cvmx_npei_dma_pcie_req_num { 1216union cvmx_npei_dma_pcie_req_num {
731 uint64_t u64; 1217 uint64_t u64;
732 struct cvmx_npei_dma_pcie_req_num_s { 1218 struct cvmx_npei_dma_pcie_req_num_s {
1219#ifdef __BIG_ENDIAN_BITFIELD
733 uint64_t dma_arb:1; 1220 uint64_t dma_arb:1;
734 uint64_t reserved_53_62:10; 1221 uint64_t reserved_53_62:10;
735 uint64_t pkt_cnt:5; 1222 uint64_t pkt_cnt:5;
@@ -745,6 +1232,23 @@ union cvmx_npei_dma_pcie_req_num {
745 uint64_t dma0_cnt:5; 1232 uint64_t dma0_cnt:5;
746 uint64_t reserved_5_7:3; 1233 uint64_t reserved_5_7:3;
747 uint64_t dma_cnt:5; 1234 uint64_t dma_cnt:5;
1235#else
1236 uint64_t dma_cnt:5;
1237 uint64_t reserved_5_7:3;
1238 uint64_t dma0_cnt:5;
1239 uint64_t reserved_13_15:3;
1240 uint64_t dma1_cnt:5;
1241 uint64_t reserved_21_23:3;
1242 uint64_t dma2_cnt:5;
1243 uint64_t reserved_29_31:3;
1244 uint64_t dma3_cnt:5;
1245 uint64_t reserved_37_39:3;
1246 uint64_t dma4_cnt:5;
1247 uint64_t reserved_45_47:3;
1248 uint64_t pkt_cnt:5;
1249 uint64_t reserved_53_62:10;
1250 uint64_t dma_arb:1;
1251#endif
748 } s; 1252 } s;
749 struct cvmx_npei_dma_pcie_req_num_s cn52xx; 1253 struct cvmx_npei_dma_pcie_req_num_s cn52xx;
750 struct cvmx_npei_dma_pcie_req_num_s cn56xx; 1254 struct cvmx_npei_dma_pcie_req_num_s cn56xx;
@@ -753,12 +1257,21 @@ union cvmx_npei_dma_pcie_req_num {
753union cvmx_npei_dma_state1 { 1257union cvmx_npei_dma_state1 {
754 uint64_t u64; 1258 uint64_t u64;
755 struct cvmx_npei_dma_state1_s { 1259 struct cvmx_npei_dma_state1_s {
1260#ifdef __BIG_ENDIAN_BITFIELD
756 uint64_t reserved_40_63:24; 1261 uint64_t reserved_40_63:24;
757 uint64_t d4_dwe:8; 1262 uint64_t d4_dwe:8;
758 uint64_t d3_dwe:8; 1263 uint64_t d3_dwe:8;
759 uint64_t d2_dwe:8; 1264 uint64_t d2_dwe:8;
760 uint64_t d1_dwe:8; 1265 uint64_t d1_dwe:8;
761 uint64_t d0_dwe:8; 1266 uint64_t d0_dwe:8;
1267#else
1268 uint64_t d0_dwe:8;
1269 uint64_t d1_dwe:8;
1270 uint64_t d2_dwe:8;
1271 uint64_t d3_dwe:8;
1272 uint64_t d4_dwe:8;
1273 uint64_t reserved_40_63:24;
1274#endif
762 } s; 1275 } s;
763 struct cvmx_npei_dma_state1_s cn52xx; 1276 struct cvmx_npei_dma_state1_s cn52xx;
764}; 1277};
@@ -766,6 +1279,7 @@ union cvmx_npei_dma_state1 {
766union cvmx_npei_dma_state1_p1 { 1279union cvmx_npei_dma_state1_p1 {
767 uint64_t u64; 1280 uint64_t u64;
768 struct cvmx_npei_dma_state1_p1_s { 1281 struct cvmx_npei_dma_state1_p1_s {
1282#ifdef __BIG_ENDIAN_BITFIELD
769 uint64_t reserved_60_63:4; 1283 uint64_t reserved_60_63:4;
770 uint64_t d0_difst:7; 1284 uint64_t d0_difst:7;
771 uint64_t d1_difst:7; 1285 uint64_t d1_difst:7;
@@ -777,8 +1291,22 @@ union cvmx_npei_dma_state1_p1 {
777 uint64_t d2_reqst:5; 1291 uint64_t d2_reqst:5;
778 uint64_t d3_reqst:5; 1292 uint64_t d3_reqst:5;
779 uint64_t d4_reqst:5; 1293 uint64_t d4_reqst:5;
1294#else
1295 uint64_t d4_reqst:5;
1296 uint64_t d3_reqst:5;
1297 uint64_t d2_reqst:5;
1298 uint64_t d1_reqst:5;
1299 uint64_t d0_reqst:5;
1300 uint64_t d4_difst:7;
1301 uint64_t d3_difst:7;
1302 uint64_t d2_difst:7;
1303 uint64_t d1_difst:7;
1304 uint64_t d0_difst:7;
1305 uint64_t reserved_60_63:4;
1306#endif
780 } s; 1307 } s;
781 struct cvmx_npei_dma_state1_p1_cn52xxp1 { 1308 struct cvmx_npei_dma_state1_p1_cn52xxp1 {
1309#ifdef __BIG_ENDIAN_BITFIELD
782 uint64_t reserved_60_63:4; 1310 uint64_t reserved_60_63:4;
783 uint64_t d0_difst:7; 1311 uint64_t d0_difst:7;
784 uint64_t d1_difst:7; 1312 uint64_t d1_difst:7;
@@ -790,6 +1318,19 @@ union cvmx_npei_dma_state1_p1 {
790 uint64_t d2_reqst:5; 1318 uint64_t d2_reqst:5;
791 uint64_t d3_reqst:5; 1319 uint64_t d3_reqst:5;
792 uint64_t reserved_0_4:5; 1320 uint64_t reserved_0_4:5;
1321#else
1322 uint64_t reserved_0_4:5;
1323 uint64_t d3_reqst:5;
1324 uint64_t d2_reqst:5;
1325 uint64_t d1_reqst:5;
1326 uint64_t d0_reqst:5;
1327 uint64_t reserved_25_31:7;
1328 uint64_t d3_difst:7;
1329 uint64_t d2_difst:7;
1330 uint64_t d1_difst:7;
1331 uint64_t d0_difst:7;
1332 uint64_t reserved_60_63:4;
1333#endif
793 } cn52xxp1; 1334 } cn52xxp1;
794 struct cvmx_npei_dma_state1_p1_s cn56xxp1; 1335 struct cvmx_npei_dma_state1_p1_s cn56xxp1;
795}; 1336};
@@ -797,12 +1338,21 @@ union cvmx_npei_dma_state1_p1 {
797union cvmx_npei_dma_state2 { 1338union cvmx_npei_dma_state2 {
798 uint64_t u64; 1339 uint64_t u64;
799 struct cvmx_npei_dma_state2_s { 1340 struct cvmx_npei_dma_state2_s {
1341#ifdef __BIG_ENDIAN_BITFIELD
800 uint64_t reserved_28_63:36; 1342 uint64_t reserved_28_63:36;
801 uint64_t ndwe:4; 1343 uint64_t ndwe:4;
802 uint64_t reserved_21_23:3; 1344 uint64_t reserved_21_23:3;
803 uint64_t ndre:5; 1345 uint64_t ndre:5;
804 uint64_t reserved_10_15:6; 1346 uint64_t reserved_10_15:6;
805 uint64_t prd:10; 1347 uint64_t prd:10;
1348#else
1349 uint64_t prd:10;
1350 uint64_t reserved_10_15:6;
1351 uint64_t ndre:5;
1352 uint64_t reserved_21_23:3;
1353 uint64_t ndwe:4;
1354 uint64_t reserved_28_63:36;
1355#endif
806 } s; 1356 } s;
807 struct cvmx_npei_dma_state2_s cn52xx; 1357 struct cvmx_npei_dma_state2_s cn52xx;
808}; 1358};
@@ -810,20 +1360,38 @@ union cvmx_npei_dma_state2 {
810union cvmx_npei_dma_state2_p1 { 1360union cvmx_npei_dma_state2_p1 {
811 uint64_t u64; 1361 uint64_t u64;
812 struct cvmx_npei_dma_state2_p1_s { 1362 struct cvmx_npei_dma_state2_p1_s {
1363#ifdef __BIG_ENDIAN_BITFIELD
813 uint64_t reserved_45_63:19; 1364 uint64_t reserved_45_63:19;
814 uint64_t d0_dffst:9; 1365 uint64_t d0_dffst:9;
815 uint64_t d1_dffst:9; 1366 uint64_t d1_dffst:9;
816 uint64_t d2_dffst:9; 1367 uint64_t d2_dffst:9;
817 uint64_t d3_dffst:9; 1368 uint64_t d3_dffst:9;
818 uint64_t d4_dffst:9; 1369 uint64_t d4_dffst:9;
1370#else
1371 uint64_t d4_dffst:9;
1372 uint64_t d3_dffst:9;
1373 uint64_t d2_dffst:9;
1374 uint64_t d1_dffst:9;
1375 uint64_t d0_dffst:9;
1376 uint64_t reserved_45_63:19;
1377#endif
819 } s; 1378 } s;
820 struct cvmx_npei_dma_state2_p1_cn52xxp1 { 1379 struct cvmx_npei_dma_state2_p1_cn52xxp1 {
1380#ifdef __BIG_ENDIAN_BITFIELD
821 uint64_t reserved_45_63:19; 1381 uint64_t reserved_45_63:19;
822 uint64_t d0_dffst:9; 1382 uint64_t d0_dffst:9;
823 uint64_t d1_dffst:9; 1383 uint64_t d1_dffst:9;
824 uint64_t d2_dffst:9; 1384 uint64_t d2_dffst:9;
825 uint64_t d3_dffst:9; 1385 uint64_t d3_dffst:9;
826 uint64_t reserved_0_8:9; 1386 uint64_t reserved_0_8:9;
1387#else
1388 uint64_t reserved_0_8:9;
1389 uint64_t d3_dffst:9;
1390 uint64_t d2_dffst:9;
1391 uint64_t d1_dffst:9;
1392 uint64_t d0_dffst:9;
1393 uint64_t reserved_45_63:19;
1394#endif
827 } cn52xxp1; 1395 } cn52xxp1;
828 struct cvmx_npei_dma_state2_p1_s cn56xxp1; 1396 struct cvmx_npei_dma_state2_p1_s cn56xxp1;
829}; 1397};
@@ -831,11 +1399,19 @@ union cvmx_npei_dma_state2_p1 {
831union cvmx_npei_dma_state3_p1 { 1399union cvmx_npei_dma_state3_p1 {
832 uint64_t u64; 1400 uint64_t u64;
833 struct cvmx_npei_dma_state3_p1_s { 1401 struct cvmx_npei_dma_state3_p1_s {
1402#ifdef __BIG_ENDIAN_BITFIELD
834 uint64_t reserved_60_63:4; 1403 uint64_t reserved_60_63:4;
835 uint64_t d0_drest:15; 1404 uint64_t d0_drest:15;
836 uint64_t d1_drest:15; 1405 uint64_t d1_drest:15;
837 uint64_t d2_drest:15; 1406 uint64_t d2_drest:15;
838 uint64_t d3_drest:15; 1407 uint64_t d3_drest:15;
1408#else
1409 uint64_t d3_drest:15;
1410 uint64_t d2_drest:15;
1411 uint64_t d1_drest:15;
1412 uint64_t d0_drest:15;
1413 uint64_t reserved_60_63:4;
1414#endif
839 } s; 1415 } s;
840 struct cvmx_npei_dma_state3_p1_s cn52xxp1; 1416 struct cvmx_npei_dma_state3_p1_s cn52xxp1;
841 struct cvmx_npei_dma_state3_p1_s cn56xxp1; 1417 struct cvmx_npei_dma_state3_p1_s cn56xxp1;
@@ -844,11 +1420,19 @@ union cvmx_npei_dma_state3_p1 {
844union cvmx_npei_dma_state4_p1 { 1420union cvmx_npei_dma_state4_p1 {
845 uint64_t u64; 1421 uint64_t u64;
846 struct cvmx_npei_dma_state4_p1_s { 1422 struct cvmx_npei_dma_state4_p1_s {
1423#ifdef __BIG_ENDIAN_BITFIELD
847 uint64_t reserved_52_63:12; 1424 uint64_t reserved_52_63:12;
848 uint64_t d0_dwest:13; 1425 uint64_t d0_dwest:13;
849 uint64_t d1_dwest:13; 1426 uint64_t d1_dwest:13;
850 uint64_t d2_dwest:13; 1427 uint64_t d2_dwest:13;
851 uint64_t d3_dwest:13; 1428 uint64_t d3_dwest:13;
1429#else
1430 uint64_t d3_dwest:13;
1431 uint64_t d2_dwest:13;
1432 uint64_t d1_dwest:13;
1433 uint64_t d0_dwest:13;
1434 uint64_t reserved_52_63:12;
1435#endif
852 } s; 1436 } s;
853 struct cvmx_npei_dma_state4_p1_s cn52xxp1; 1437 struct cvmx_npei_dma_state4_p1_s cn52xxp1;
854 struct cvmx_npei_dma_state4_p1_s cn56xxp1; 1438 struct cvmx_npei_dma_state4_p1_s cn56xxp1;
@@ -857,9 +1441,15 @@ union cvmx_npei_dma_state4_p1 {
857union cvmx_npei_dma_state5_p1 { 1441union cvmx_npei_dma_state5_p1 {
858 uint64_t u64; 1442 uint64_t u64;
859 struct cvmx_npei_dma_state5_p1_s { 1443 struct cvmx_npei_dma_state5_p1_s {
1444#ifdef __BIG_ENDIAN_BITFIELD
860 uint64_t reserved_28_63:36; 1445 uint64_t reserved_28_63:36;
861 uint64_t d4_drest:15; 1446 uint64_t d4_drest:15;
862 uint64_t d4_dwest:13; 1447 uint64_t d4_dwest:13;
1448#else
1449 uint64_t d4_dwest:13;
1450 uint64_t d4_drest:15;
1451 uint64_t reserved_28_63:36;
1452#endif
863 } s; 1453 } s;
864 struct cvmx_npei_dma_state5_p1_s cn56xxp1; 1454 struct cvmx_npei_dma_state5_p1_s cn56xxp1;
865}; 1455};
@@ -867,6 +1457,7 @@ union cvmx_npei_dma_state5_p1 {
867union cvmx_npei_int_a_enb { 1457union cvmx_npei_int_a_enb {
868 uint64_t u64; 1458 uint64_t u64;
869 struct cvmx_npei_int_a_enb_s { 1459 struct cvmx_npei_int_a_enb_s {
1460#ifdef __BIG_ENDIAN_BITFIELD
870 uint64_t reserved_10_63:54; 1461 uint64_t reserved_10_63:54;
871 uint64_t pout_err:1; 1462 uint64_t pout_err:1;
872 uint64_t pin_bp:1; 1463 uint64_t pin_bp:1;
@@ -878,12 +1469,31 @@ union cvmx_npei_int_a_enb {
878 uint64_t pins_err:1; 1469 uint64_t pins_err:1;
879 uint64_t dma1_cpl:1; 1470 uint64_t dma1_cpl:1;
880 uint64_t dma0_cpl:1; 1471 uint64_t dma0_cpl:1;
1472#else
1473 uint64_t dma0_cpl:1;
1474 uint64_t dma1_cpl:1;
1475 uint64_t pins_err:1;
1476 uint64_t pop_err:1;
1477 uint64_t pdi_err:1;
1478 uint64_t pgl_err:1;
1479 uint64_t p0_rdlk:1;
1480 uint64_t p1_rdlk:1;
1481 uint64_t pin_bp:1;
1482 uint64_t pout_err:1;
1483 uint64_t reserved_10_63:54;
1484#endif
881 } s; 1485 } s;
882 struct cvmx_npei_int_a_enb_s cn52xx; 1486 struct cvmx_npei_int_a_enb_s cn52xx;
883 struct cvmx_npei_int_a_enb_cn52xxp1 { 1487 struct cvmx_npei_int_a_enb_cn52xxp1 {
1488#ifdef __BIG_ENDIAN_BITFIELD
884 uint64_t reserved_2_63:62; 1489 uint64_t reserved_2_63:62;
885 uint64_t dma1_cpl:1; 1490 uint64_t dma1_cpl:1;
886 uint64_t dma0_cpl:1; 1491 uint64_t dma0_cpl:1;
1492#else
1493 uint64_t dma0_cpl:1;
1494 uint64_t dma1_cpl:1;
1495 uint64_t reserved_2_63:62;
1496#endif
887 } cn52xxp1; 1497 } cn52xxp1;
888 struct cvmx_npei_int_a_enb_s cn56xx; 1498 struct cvmx_npei_int_a_enb_s cn56xx;
889}; 1499};
@@ -891,6 +1501,7 @@ union cvmx_npei_int_a_enb {
891union cvmx_npei_int_a_enb2 { 1501union cvmx_npei_int_a_enb2 {
892 uint64_t u64; 1502 uint64_t u64;
893 struct cvmx_npei_int_a_enb2_s { 1503 struct cvmx_npei_int_a_enb2_s {
1504#ifdef __BIG_ENDIAN_BITFIELD
894 uint64_t reserved_10_63:54; 1505 uint64_t reserved_10_63:54;
895 uint64_t pout_err:1; 1506 uint64_t pout_err:1;
896 uint64_t pin_bp:1; 1507 uint64_t pin_bp:1;
@@ -902,12 +1513,31 @@ union cvmx_npei_int_a_enb2 {
902 uint64_t pins_err:1; 1513 uint64_t pins_err:1;
903 uint64_t dma1_cpl:1; 1514 uint64_t dma1_cpl:1;
904 uint64_t dma0_cpl:1; 1515 uint64_t dma0_cpl:1;
1516#else
1517 uint64_t dma0_cpl:1;
1518 uint64_t dma1_cpl:1;
1519 uint64_t pins_err:1;
1520 uint64_t pop_err:1;
1521 uint64_t pdi_err:1;
1522 uint64_t pgl_err:1;
1523 uint64_t p0_rdlk:1;
1524 uint64_t p1_rdlk:1;
1525 uint64_t pin_bp:1;
1526 uint64_t pout_err:1;
1527 uint64_t reserved_10_63:54;
1528#endif
905 } s; 1529 } s;
906 struct cvmx_npei_int_a_enb2_s cn52xx; 1530 struct cvmx_npei_int_a_enb2_s cn52xx;
907 struct cvmx_npei_int_a_enb2_cn52xxp1 { 1531 struct cvmx_npei_int_a_enb2_cn52xxp1 {
1532#ifdef __BIG_ENDIAN_BITFIELD
908 uint64_t reserved_2_63:62; 1533 uint64_t reserved_2_63:62;
909 uint64_t dma1_cpl:1; 1534 uint64_t dma1_cpl:1;
910 uint64_t dma0_cpl:1; 1535 uint64_t dma0_cpl:1;
1536#else
1537 uint64_t dma0_cpl:1;
1538 uint64_t dma1_cpl:1;
1539 uint64_t reserved_2_63:62;
1540#endif
911 } cn52xxp1; 1541 } cn52xxp1;
912 struct cvmx_npei_int_a_enb2_s cn56xx; 1542 struct cvmx_npei_int_a_enb2_s cn56xx;
913}; 1543};
@@ -915,6 +1545,7 @@ union cvmx_npei_int_a_enb2 {
915union cvmx_npei_int_a_sum { 1545union cvmx_npei_int_a_sum {
916 uint64_t u64; 1546 uint64_t u64;
917 struct cvmx_npei_int_a_sum_s { 1547 struct cvmx_npei_int_a_sum_s {
1548#ifdef __BIG_ENDIAN_BITFIELD
918 uint64_t reserved_10_63:54; 1549 uint64_t reserved_10_63:54;
919 uint64_t pout_err:1; 1550 uint64_t pout_err:1;
920 uint64_t pin_bp:1; 1551 uint64_t pin_bp:1;
@@ -926,12 +1557,31 @@ union cvmx_npei_int_a_sum {
926 uint64_t pins_err:1; 1557 uint64_t pins_err:1;
927 uint64_t dma1_cpl:1; 1558 uint64_t dma1_cpl:1;
928 uint64_t dma0_cpl:1; 1559 uint64_t dma0_cpl:1;
1560#else
1561 uint64_t dma0_cpl:1;
1562 uint64_t dma1_cpl:1;
1563 uint64_t pins_err:1;
1564 uint64_t pop_err:1;
1565 uint64_t pdi_err:1;
1566 uint64_t pgl_err:1;
1567 uint64_t p0_rdlk:1;
1568 uint64_t p1_rdlk:1;
1569 uint64_t pin_bp:1;
1570 uint64_t pout_err:1;
1571 uint64_t reserved_10_63:54;
1572#endif
929 } s; 1573 } s;
930 struct cvmx_npei_int_a_sum_s cn52xx; 1574 struct cvmx_npei_int_a_sum_s cn52xx;
931 struct cvmx_npei_int_a_sum_cn52xxp1 { 1575 struct cvmx_npei_int_a_sum_cn52xxp1 {
1576#ifdef __BIG_ENDIAN_BITFIELD
932 uint64_t reserved_2_63:62; 1577 uint64_t reserved_2_63:62;
933 uint64_t dma1_cpl:1; 1578 uint64_t dma1_cpl:1;
934 uint64_t dma0_cpl:1; 1579 uint64_t dma0_cpl:1;
1580#else
1581 uint64_t dma0_cpl:1;
1582 uint64_t dma1_cpl:1;
1583 uint64_t reserved_2_63:62;
1584#endif
935 } cn52xxp1; 1585 } cn52xxp1;
936 struct cvmx_npei_int_a_sum_s cn56xx; 1586 struct cvmx_npei_int_a_sum_s cn56xx;
937}; 1587};
@@ -939,6 +1589,7 @@ union cvmx_npei_int_a_sum {
939union cvmx_npei_int_enb { 1589union cvmx_npei_int_enb {
940 uint64_t u64; 1590 uint64_t u64;
941 struct cvmx_npei_int_enb_s { 1591 struct cvmx_npei_int_enb_s {
1592#ifdef __BIG_ENDIAN_BITFIELD
942 uint64_t mio_inta:1; 1593 uint64_t mio_inta:1;
943 uint64_t reserved_62_62:1; 1594 uint64_t reserved_62_62:1;
944 uint64_t int_a:1; 1595 uint64_t int_a:1;
@@ -1003,9 +1654,76 @@ union cvmx_npei_int_enb {
1003 uint64_t bar0_to:1; 1654 uint64_t bar0_to:1;
1004 uint64_t rml_wto:1; 1655 uint64_t rml_wto:1;
1005 uint64_t rml_rto:1; 1656 uint64_t rml_rto:1;
1657#else
1658 uint64_t rml_rto:1;
1659 uint64_t rml_wto:1;
1660 uint64_t bar0_to:1;
1661 uint64_t iob2big:1;
1662 uint64_t dma0dbo:1;
1663 uint64_t dma1dbo:1;
1664 uint64_t dma2dbo:1;
1665 uint64_t dma3dbo:1;
1666 uint64_t dma4dbo:1;
1667 uint64_t dma0fi:1;
1668 uint64_t dma1fi:1;
1669 uint64_t dcnt0:1;
1670 uint64_t dcnt1:1;
1671 uint64_t dtime0:1;
1672 uint64_t dtime1:1;
1673 uint64_t psldbof:1;
1674 uint64_t pidbof:1;
1675 uint64_t pcnt:1;
1676 uint64_t ptime:1;
1677 uint64_t c0_aeri:1;
1678 uint64_t crs0_er:1;
1679 uint64_t c0_se:1;
1680 uint64_t crs0_dr:1;
1681 uint64_t c0_wake:1;
1682 uint64_t c0_pmei:1;
1683 uint64_t c0_hpint:1;
1684 uint64_t c1_aeri:1;
1685 uint64_t crs1_er:1;
1686 uint64_t c1_se:1;
1687 uint64_t crs1_dr:1;
1688 uint64_t c1_wake:1;
1689 uint64_t c1_pmei:1;
1690 uint64_t c1_hpint:1;
1691 uint64_t c0_up_b0:1;
1692 uint64_t c0_up_b1:1;
1693 uint64_t c0_up_b2:1;
1694 uint64_t c0_up_wi:1;
1695 uint64_t c0_up_bx:1;
1696 uint64_t c0_un_b0:1;
1697 uint64_t c0_un_b1:1;
1698 uint64_t c0_un_b2:1;
1699 uint64_t c0_un_wi:1;
1700 uint64_t c0_un_bx:1;
1701 uint64_t c1_up_b0:1;
1702 uint64_t c1_up_b1:1;
1703 uint64_t c1_up_b2:1;
1704 uint64_t c1_up_wi:1;
1705 uint64_t c1_up_bx:1;
1706 uint64_t c1_un_b0:1;
1707 uint64_t c1_un_b1:1;
1708 uint64_t c1_un_b2:1;
1709 uint64_t c1_un_wi:1;
1710 uint64_t c1_un_bx:1;
1711 uint64_t c0_un_wf:1;
1712 uint64_t c1_un_wf:1;
1713 uint64_t c0_up_wf:1;
1714 uint64_t c1_up_wf:1;
1715 uint64_t c0_exc:1;
1716 uint64_t c1_exc:1;
1717 uint64_t c0_ldwn:1;
1718 uint64_t c1_ldwn:1;
1719 uint64_t int_a:1;
1720 uint64_t reserved_62_62:1;
1721 uint64_t mio_inta:1;
1722#endif
1006 } s; 1723 } s;
1007 struct cvmx_npei_int_enb_s cn52xx; 1724 struct cvmx_npei_int_enb_s cn52xx;
1008 struct cvmx_npei_int_enb_cn52xxp1 { 1725 struct cvmx_npei_int_enb_cn52xxp1 {
1726#ifdef __BIG_ENDIAN_BITFIELD
1009 uint64_t mio_inta:1; 1727 uint64_t mio_inta:1;
1010 uint64_t reserved_62_62:1; 1728 uint64_t reserved_62_62:1;
1011 uint64_t int_a:1; 1729 uint64_t int_a:1;
@@ -1070,9 +1788,76 @@ union cvmx_npei_int_enb {
1070 uint64_t bar0_to:1; 1788 uint64_t bar0_to:1;
1071 uint64_t rml_wto:1; 1789 uint64_t rml_wto:1;
1072 uint64_t rml_rto:1; 1790 uint64_t rml_rto:1;
1791#else
1792 uint64_t rml_rto:1;
1793 uint64_t rml_wto:1;
1794 uint64_t bar0_to:1;
1795 uint64_t iob2big:1;
1796 uint64_t dma0dbo:1;
1797 uint64_t dma1dbo:1;
1798 uint64_t dma2dbo:1;
1799 uint64_t dma3dbo:1;
1800 uint64_t reserved_8_8:1;
1801 uint64_t dma0fi:1;
1802 uint64_t dma1fi:1;
1803 uint64_t dcnt0:1;
1804 uint64_t dcnt1:1;
1805 uint64_t dtime0:1;
1806 uint64_t dtime1:1;
1807 uint64_t psldbof:1;
1808 uint64_t pidbof:1;
1809 uint64_t pcnt:1;
1810 uint64_t ptime:1;
1811 uint64_t c0_aeri:1;
1812 uint64_t crs0_er:1;
1813 uint64_t c0_se:1;
1814 uint64_t crs0_dr:1;
1815 uint64_t c0_wake:1;
1816 uint64_t c0_pmei:1;
1817 uint64_t c0_hpint:1;
1818 uint64_t c1_aeri:1;
1819 uint64_t crs1_er:1;
1820 uint64_t c1_se:1;
1821 uint64_t crs1_dr:1;
1822 uint64_t c1_wake:1;
1823 uint64_t c1_pmei:1;
1824 uint64_t c1_hpint:1;
1825 uint64_t c0_up_b0:1;
1826 uint64_t c0_up_b1:1;
1827 uint64_t c0_up_b2:1;
1828 uint64_t c0_up_wi:1;
1829 uint64_t c0_up_bx:1;
1830 uint64_t c0_un_b0:1;
1831 uint64_t c0_un_b1:1;
1832 uint64_t c0_un_b2:1;
1833 uint64_t c0_un_wi:1;
1834 uint64_t c0_un_bx:1;
1835 uint64_t c1_up_b0:1;
1836 uint64_t c1_up_b1:1;
1837 uint64_t c1_up_b2:1;
1838 uint64_t c1_up_wi:1;
1839 uint64_t c1_up_bx:1;
1840 uint64_t c1_un_b0:1;
1841 uint64_t c1_un_b1:1;
1842 uint64_t c1_un_b2:1;
1843 uint64_t c1_un_wi:1;
1844 uint64_t c1_un_bx:1;
1845 uint64_t c0_un_wf:1;
1846 uint64_t c1_un_wf:1;
1847 uint64_t c0_up_wf:1;
1848 uint64_t c1_up_wf:1;
1849 uint64_t c0_exc:1;
1850 uint64_t c1_exc:1;
1851 uint64_t c0_ldwn:1;
1852 uint64_t c1_ldwn:1;
1853 uint64_t int_a:1;
1854 uint64_t reserved_62_62:1;
1855 uint64_t mio_inta:1;
1856#endif
1073 } cn52xxp1; 1857 } cn52xxp1;
1074 struct cvmx_npei_int_enb_s cn56xx; 1858 struct cvmx_npei_int_enb_s cn56xx;
1075 struct cvmx_npei_int_enb_cn56xxp1 { 1859 struct cvmx_npei_int_enb_cn56xxp1 {
1860#ifdef __BIG_ENDIAN_BITFIELD
1076 uint64_t mio_inta:1; 1861 uint64_t mio_inta:1;
1077 uint64_t reserved_61_62:2; 1862 uint64_t reserved_61_62:2;
1078 uint64_t c1_ldwn:1; 1863 uint64_t c1_ldwn:1;
@@ -1136,12 +1921,78 @@ union cvmx_npei_int_enb {
1136 uint64_t bar0_to:1; 1921 uint64_t bar0_to:1;
1137 uint64_t rml_wto:1; 1922 uint64_t rml_wto:1;
1138 uint64_t rml_rto:1; 1923 uint64_t rml_rto:1;
1924#else
1925 uint64_t rml_rto:1;
1926 uint64_t rml_wto:1;
1927 uint64_t bar0_to:1;
1928 uint64_t iob2big:1;
1929 uint64_t dma0dbo:1;
1930 uint64_t dma1dbo:1;
1931 uint64_t dma2dbo:1;
1932 uint64_t dma3dbo:1;
1933 uint64_t dma4dbo:1;
1934 uint64_t dma0fi:1;
1935 uint64_t dma1fi:1;
1936 uint64_t dcnt0:1;
1937 uint64_t dcnt1:1;
1938 uint64_t dtime0:1;
1939 uint64_t dtime1:1;
1940 uint64_t psldbof:1;
1941 uint64_t pidbof:1;
1942 uint64_t pcnt:1;
1943 uint64_t ptime:1;
1944 uint64_t c0_aeri:1;
1945 uint64_t reserved_20_20:1;
1946 uint64_t c0_se:1;
1947 uint64_t reserved_22_22:1;
1948 uint64_t c0_wake:1;
1949 uint64_t c0_pmei:1;
1950 uint64_t c0_hpint:1;
1951 uint64_t c1_aeri:1;
1952 uint64_t reserved_27_27:1;
1953 uint64_t c1_se:1;
1954 uint64_t reserved_29_29:1;
1955 uint64_t c1_wake:1;
1956 uint64_t c1_pmei:1;
1957 uint64_t c1_hpint:1;
1958 uint64_t c0_up_b0:1;
1959 uint64_t c0_up_b1:1;
1960 uint64_t c0_up_b2:1;
1961 uint64_t c0_up_wi:1;
1962 uint64_t c0_up_bx:1;
1963 uint64_t c0_un_b0:1;
1964 uint64_t c0_un_b1:1;
1965 uint64_t c0_un_b2:1;
1966 uint64_t c0_un_wi:1;
1967 uint64_t c0_un_bx:1;
1968 uint64_t c1_up_b0:1;
1969 uint64_t c1_up_b1:1;
1970 uint64_t c1_up_b2:1;
1971 uint64_t c1_up_wi:1;
1972 uint64_t c1_up_bx:1;
1973 uint64_t c1_un_b0:1;
1974 uint64_t c1_un_b1:1;
1975 uint64_t c1_un_b2:1;
1976 uint64_t c1_un_wi:1;
1977 uint64_t c1_un_bx:1;
1978 uint64_t c0_un_wf:1;
1979 uint64_t c1_un_wf:1;
1980 uint64_t c0_up_wf:1;
1981 uint64_t c1_up_wf:1;
1982 uint64_t c0_exc:1;
1983 uint64_t c1_exc:1;
1984 uint64_t c0_ldwn:1;
1985 uint64_t c1_ldwn:1;
1986 uint64_t reserved_61_62:2;
1987 uint64_t mio_inta:1;
1988#endif
1139 } cn56xxp1; 1989 } cn56xxp1;
1140}; 1990};
1141 1991
1142union cvmx_npei_int_enb2 { 1992union cvmx_npei_int_enb2 {
1143 uint64_t u64; 1993 uint64_t u64;
1144 struct cvmx_npei_int_enb2_s { 1994 struct cvmx_npei_int_enb2_s {
1995#ifdef __BIG_ENDIAN_BITFIELD
1145 uint64_t reserved_62_63:2; 1996 uint64_t reserved_62_63:2;
1146 uint64_t int_a:1; 1997 uint64_t int_a:1;
1147 uint64_t c1_ldwn:1; 1998 uint64_t c1_ldwn:1;
@@ -1205,9 +2056,75 @@ union cvmx_npei_int_enb2 {
1205 uint64_t bar0_to:1; 2056 uint64_t bar0_to:1;
1206 uint64_t rml_wto:1; 2057 uint64_t rml_wto:1;
1207 uint64_t rml_rto:1; 2058 uint64_t rml_rto:1;
2059#else
2060 uint64_t rml_rto:1;
2061 uint64_t rml_wto:1;
2062 uint64_t bar0_to:1;
2063 uint64_t iob2big:1;
2064 uint64_t dma0dbo:1;
2065 uint64_t dma1dbo:1;
2066 uint64_t dma2dbo:1;
2067 uint64_t dma3dbo:1;
2068 uint64_t dma4dbo:1;
2069 uint64_t dma0fi:1;
2070 uint64_t dma1fi:1;
2071 uint64_t dcnt0:1;
2072 uint64_t dcnt1:1;
2073 uint64_t dtime0:1;
2074 uint64_t dtime1:1;
2075 uint64_t psldbof:1;
2076 uint64_t pidbof:1;
2077 uint64_t pcnt:1;
2078 uint64_t ptime:1;
2079 uint64_t c0_aeri:1;
2080 uint64_t crs0_er:1;
2081 uint64_t c0_se:1;
2082 uint64_t crs0_dr:1;
2083 uint64_t c0_wake:1;
2084 uint64_t c0_pmei:1;
2085 uint64_t c0_hpint:1;
2086 uint64_t c1_aeri:1;
2087 uint64_t crs1_er:1;
2088 uint64_t c1_se:1;
2089 uint64_t crs1_dr:1;
2090 uint64_t c1_wake:1;
2091 uint64_t c1_pmei:1;
2092 uint64_t c1_hpint:1;
2093 uint64_t c0_up_b0:1;
2094 uint64_t c0_up_b1:1;
2095 uint64_t c0_up_b2:1;
2096 uint64_t c0_up_wi:1;
2097 uint64_t c0_up_bx:1;
2098 uint64_t c0_un_b0:1;
2099 uint64_t c0_un_b1:1;
2100 uint64_t c0_un_b2:1;
2101 uint64_t c0_un_wi:1;
2102 uint64_t c0_un_bx:1;
2103 uint64_t c1_up_b0:1;
2104 uint64_t c1_up_b1:1;
2105 uint64_t c1_up_b2:1;
2106 uint64_t c1_up_wi:1;
2107 uint64_t c1_up_bx:1;
2108 uint64_t c1_un_b0:1;
2109 uint64_t c1_un_b1:1;
2110 uint64_t c1_un_b2:1;
2111 uint64_t c1_un_wi:1;
2112 uint64_t c1_un_bx:1;
2113 uint64_t c0_un_wf:1;
2114 uint64_t c1_un_wf:1;
2115 uint64_t c0_up_wf:1;
2116 uint64_t c1_up_wf:1;
2117 uint64_t c0_exc:1;
2118 uint64_t c1_exc:1;
2119 uint64_t c0_ldwn:1;
2120 uint64_t c1_ldwn:1;
2121 uint64_t int_a:1;
2122 uint64_t reserved_62_63:2;
2123#endif
1208 } s; 2124 } s;
1209 struct cvmx_npei_int_enb2_s cn52xx; 2125 struct cvmx_npei_int_enb2_s cn52xx;
1210 struct cvmx_npei_int_enb2_cn52xxp1 { 2126 struct cvmx_npei_int_enb2_cn52xxp1 {
2127#ifdef __BIG_ENDIAN_BITFIELD
1211 uint64_t reserved_62_63:2; 2128 uint64_t reserved_62_63:2;
1212 uint64_t int_a:1; 2129 uint64_t int_a:1;
1213 uint64_t c1_ldwn:1; 2130 uint64_t c1_ldwn:1;
@@ -1271,9 +2188,75 @@ union cvmx_npei_int_enb2 {
1271 uint64_t bar0_to:1; 2188 uint64_t bar0_to:1;
1272 uint64_t rml_wto:1; 2189 uint64_t rml_wto:1;
1273 uint64_t rml_rto:1; 2190 uint64_t rml_rto:1;
2191#else
2192 uint64_t rml_rto:1;
2193 uint64_t rml_wto:1;
2194 uint64_t bar0_to:1;
2195 uint64_t iob2big:1;
2196 uint64_t dma0dbo:1;
2197 uint64_t dma1dbo:1;
2198 uint64_t dma2dbo:1;
2199 uint64_t dma3dbo:1;
2200 uint64_t reserved_8_8:1;
2201 uint64_t dma0fi:1;
2202 uint64_t dma1fi:1;
2203 uint64_t dcnt0:1;
2204 uint64_t dcnt1:1;
2205 uint64_t dtime0:1;
2206 uint64_t dtime1:1;
2207 uint64_t psldbof:1;
2208 uint64_t pidbof:1;
2209 uint64_t pcnt:1;
2210 uint64_t ptime:1;
2211 uint64_t c0_aeri:1;
2212 uint64_t crs0_er:1;
2213 uint64_t c0_se:1;
2214 uint64_t crs0_dr:1;
2215 uint64_t c0_wake:1;
2216 uint64_t c0_pmei:1;
2217 uint64_t c0_hpint:1;
2218 uint64_t c1_aeri:1;
2219 uint64_t crs1_er:1;
2220 uint64_t c1_se:1;
2221 uint64_t crs1_dr:1;
2222 uint64_t c1_wake:1;
2223 uint64_t c1_pmei:1;
2224 uint64_t c1_hpint:1;
2225 uint64_t c0_up_b0:1;
2226 uint64_t c0_up_b1:1;
2227 uint64_t c0_up_b2:1;
2228 uint64_t c0_up_wi:1;
2229 uint64_t c0_up_bx:1;
2230 uint64_t c0_un_b0:1;
2231 uint64_t c0_un_b1:1;
2232 uint64_t c0_un_b2:1;
2233 uint64_t c0_un_wi:1;
2234 uint64_t c0_un_bx:1;
2235 uint64_t c1_up_b0:1;
2236 uint64_t c1_up_b1:1;
2237 uint64_t c1_up_b2:1;
2238 uint64_t c1_up_wi:1;
2239 uint64_t c1_up_bx:1;
2240 uint64_t c1_un_b0:1;
2241 uint64_t c1_un_b1:1;
2242 uint64_t c1_un_b2:1;
2243 uint64_t c1_un_wi:1;
2244 uint64_t c1_un_bx:1;
2245 uint64_t c0_un_wf:1;
2246 uint64_t c1_un_wf:1;
2247 uint64_t c0_up_wf:1;
2248 uint64_t c1_up_wf:1;
2249 uint64_t c0_exc:1;
2250 uint64_t c1_exc:1;
2251 uint64_t c0_ldwn:1;
2252 uint64_t c1_ldwn:1;
2253 uint64_t int_a:1;
2254 uint64_t reserved_62_63:2;
2255#endif
1274 } cn52xxp1; 2256 } cn52xxp1;
1275 struct cvmx_npei_int_enb2_s cn56xx; 2257 struct cvmx_npei_int_enb2_s cn56xx;
1276 struct cvmx_npei_int_enb2_cn56xxp1 { 2258 struct cvmx_npei_int_enb2_cn56xxp1 {
2259#ifdef __BIG_ENDIAN_BITFIELD
1277 uint64_t reserved_61_63:3; 2260 uint64_t reserved_61_63:3;
1278 uint64_t c1_ldwn:1; 2261 uint64_t c1_ldwn:1;
1279 uint64_t c0_ldwn:1; 2262 uint64_t c0_ldwn:1;
@@ -1336,15 +2319,85 @@ union cvmx_npei_int_enb2 {
1336 uint64_t bar0_to:1; 2319 uint64_t bar0_to:1;
1337 uint64_t rml_wto:1; 2320 uint64_t rml_wto:1;
1338 uint64_t rml_rto:1; 2321 uint64_t rml_rto:1;
2322#else
2323 uint64_t rml_rto:1;
2324 uint64_t rml_wto:1;
2325 uint64_t bar0_to:1;
2326 uint64_t iob2big:1;
2327 uint64_t dma0dbo:1;
2328 uint64_t dma1dbo:1;
2329 uint64_t dma2dbo:1;
2330 uint64_t dma3dbo:1;
2331 uint64_t dma4dbo:1;
2332 uint64_t dma0fi:1;
2333 uint64_t dma1fi:1;
2334 uint64_t dcnt0:1;
2335 uint64_t dcnt1:1;
2336 uint64_t dtime0:1;
2337 uint64_t dtime1:1;
2338 uint64_t psldbof:1;
2339 uint64_t pidbof:1;
2340 uint64_t pcnt:1;
2341 uint64_t ptime:1;
2342 uint64_t c0_aeri:1;
2343 uint64_t reserved_20_20:1;
2344 uint64_t c0_se:1;
2345 uint64_t reserved_22_22:1;
2346 uint64_t c0_wake:1;
2347 uint64_t c0_pmei:1;
2348 uint64_t c0_hpint:1;
2349 uint64_t c1_aeri:1;
2350 uint64_t reserved_27_27:1;
2351 uint64_t c1_se:1;
2352 uint64_t reserved_29_29:1;
2353 uint64_t c1_wake:1;
2354 uint64_t c1_pmei:1;
2355 uint64_t c1_hpint:1;
2356 uint64_t c0_up_b0:1;
2357 uint64_t c0_up_b1:1;
2358 uint64_t c0_up_b2:1;
2359 uint64_t c0_up_wi:1;
2360 uint64_t c0_up_bx:1;
2361 uint64_t c0_un_b0:1;
2362 uint64_t c0_un_b1:1;
2363 uint64_t c0_un_b2:1;
2364 uint64_t c0_un_wi:1;
2365 uint64_t c0_un_bx:1;
2366 uint64_t c1_up_b0:1;
2367 uint64_t c1_up_b1:1;
2368 uint64_t c1_up_b2:1;
2369 uint64_t c1_up_wi:1;
2370 uint64_t c1_up_bx:1;
2371 uint64_t c1_un_b0:1;
2372 uint64_t c1_un_b1:1;
2373 uint64_t c1_un_b2:1;
2374 uint64_t c1_un_wi:1;
2375 uint64_t c1_un_bx:1;
2376 uint64_t c0_un_wf:1;
2377 uint64_t c1_un_wf:1;
2378 uint64_t c0_up_wf:1;
2379 uint64_t c1_up_wf:1;
2380 uint64_t c0_exc:1;
2381 uint64_t c1_exc:1;
2382 uint64_t c0_ldwn:1;
2383 uint64_t c1_ldwn:1;
2384 uint64_t reserved_61_63:3;
2385#endif
1339 } cn56xxp1; 2386 } cn56xxp1;
1340}; 2387};
1341 2388
1342union cvmx_npei_int_info { 2389union cvmx_npei_int_info {
1343 uint64_t u64; 2390 uint64_t u64;
1344 struct cvmx_npei_int_info_s { 2391 struct cvmx_npei_int_info_s {
2392#ifdef __BIG_ENDIAN_BITFIELD
1345 uint64_t reserved_12_63:52; 2393 uint64_t reserved_12_63:52;
1346 uint64_t pidbof:6; 2394 uint64_t pidbof:6;
1347 uint64_t psldbof:6; 2395 uint64_t psldbof:6;
2396#else
2397 uint64_t psldbof:6;
2398 uint64_t pidbof:6;
2399 uint64_t reserved_12_63:52;
2400#endif
1348 } s; 2401 } s;
1349 struct cvmx_npei_int_info_s cn52xx; 2402 struct cvmx_npei_int_info_s cn52xx;
1350 struct cvmx_npei_int_info_s cn56xx; 2403 struct cvmx_npei_int_info_s cn56xx;
@@ -1354,6 +2407,7 @@ union cvmx_npei_int_info {
1354union cvmx_npei_int_sum { 2407union cvmx_npei_int_sum {
1355 uint64_t u64; 2408 uint64_t u64;
1356 struct cvmx_npei_int_sum_s { 2409 struct cvmx_npei_int_sum_s {
2410#ifdef __BIG_ENDIAN_BITFIELD
1357 uint64_t mio_inta:1; 2411 uint64_t mio_inta:1;
1358 uint64_t reserved_62_62:1; 2412 uint64_t reserved_62_62:1;
1359 uint64_t int_a:1; 2413 uint64_t int_a:1;
@@ -1418,9 +2472,76 @@ union cvmx_npei_int_sum {
1418 uint64_t bar0_to:1; 2472 uint64_t bar0_to:1;
1419 uint64_t rml_wto:1; 2473 uint64_t rml_wto:1;
1420 uint64_t rml_rto:1; 2474 uint64_t rml_rto:1;
2475#else
2476 uint64_t rml_rto:1;
2477 uint64_t rml_wto:1;
2478 uint64_t bar0_to:1;
2479 uint64_t iob2big:1;
2480 uint64_t dma0dbo:1;
2481 uint64_t dma1dbo:1;
2482 uint64_t dma2dbo:1;
2483 uint64_t dma3dbo:1;
2484 uint64_t dma4dbo:1;
2485 uint64_t dma0fi:1;
2486 uint64_t dma1fi:1;
2487 uint64_t dcnt0:1;
2488 uint64_t dcnt1:1;
2489 uint64_t dtime0:1;
2490 uint64_t dtime1:1;
2491 uint64_t psldbof:1;
2492 uint64_t pidbof:1;
2493 uint64_t pcnt:1;
2494 uint64_t ptime:1;
2495 uint64_t c0_aeri:1;
2496 uint64_t crs0_er:1;
2497 uint64_t c0_se:1;
2498 uint64_t crs0_dr:1;
2499 uint64_t c0_wake:1;
2500 uint64_t c0_pmei:1;
2501 uint64_t c0_hpint:1;
2502 uint64_t c1_aeri:1;
2503 uint64_t crs1_er:1;
2504 uint64_t c1_se:1;
2505 uint64_t crs1_dr:1;
2506 uint64_t c1_wake:1;
2507 uint64_t c1_pmei:1;
2508 uint64_t c1_hpint:1;
2509 uint64_t c0_up_b0:1;
2510 uint64_t c0_up_b1:1;
2511 uint64_t c0_up_b2:1;
2512 uint64_t c0_up_wi:1;
2513 uint64_t c0_up_bx:1;
2514 uint64_t c0_un_b0:1;
2515 uint64_t c0_un_b1:1;
2516 uint64_t c0_un_b2:1;
2517 uint64_t c0_un_wi:1;
2518 uint64_t c0_un_bx:1;
2519 uint64_t c1_up_b0:1;
2520 uint64_t c1_up_b1:1;
2521 uint64_t c1_up_b2:1;
2522 uint64_t c1_up_wi:1;
2523 uint64_t c1_up_bx:1;
2524 uint64_t c1_un_b0:1;
2525 uint64_t c1_un_b1:1;
2526 uint64_t c1_un_b2:1;
2527 uint64_t c1_un_wi:1;
2528 uint64_t c1_un_bx:1;
2529 uint64_t c0_un_wf:1;
2530 uint64_t c1_un_wf:1;
2531 uint64_t c0_up_wf:1;
2532 uint64_t c1_up_wf:1;
2533 uint64_t c0_exc:1;
2534 uint64_t c1_exc:1;
2535 uint64_t c0_ldwn:1;
2536 uint64_t c1_ldwn:1;
2537 uint64_t int_a:1;
2538 uint64_t reserved_62_62:1;
2539 uint64_t mio_inta:1;
2540#endif
1421 } s; 2541 } s;
1422 struct cvmx_npei_int_sum_s cn52xx; 2542 struct cvmx_npei_int_sum_s cn52xx;
1423 struct cvmx_npei_int_sum_cn52xxp1 { 2543 struct cvmx_npei_int_sum_cn52xxp1 {
2544#ifdef __BIG_ENDIAN_BITFIELD
1424 uint64_t mio_inta:1; 2545 uint64_t mio_inta:1;
1425 uint64_t reserved_62_62:1; 2546 uint64_t reserved_62_62:1;
1426 uint64_t int_a:1; 2547 uint64_t int_a:1;
@@ -1482,9 +2603,73 @@ union cvmx_npei_int_sum {
1482 uint64_t bar0_to:1; 2603 uint64_t bar0_to:1;
1483 uint64_t rml_wto:1; 2604 uint64_t rml_wto:1;
1484 uint64_t rml_rto:1; 2605 uint64_t rml_rto:1;
2606#else
2607 uint64_t rml_rto:1;
2608 uint64_t rml_wto:1;
2609 uint64_t bar0_to:1;
2610 uint64_t iob2big:1;
2611 uint64_t dma0dbo:1;
2612 uint64_t dma1dbo:1;
2613 uint64_t dma2dbo:1;
2614 uint64_t dma3dbo:1;
2615 uint64_t reserved_8_8:1;
2616 uint64_t dma0fi:1;
2617 uint64_t dma1fi:1;
2618 uint64_t dcnt0:1;
2619 uint64_t dcnt1:1;
2620 uint64_t dtime0:1;
2621 uint64_t dtime1:1;
2622 uint64_t reserved_15_18:4;
2623 uint64_t c0_aeri:1;
2624 uint64_t crs0_er:1;
2625 uint64_t c0_se:1;
2626 uint64_t crs0_dr:1;
2627 uint64_t c0_wake:1;
2628 uint64_t c0_pmei:1;
2629 uint64_t c0_hpint:1;
2630 uint64_t c1_aeri:1;
2631 uint64_t crs1_er:1;
2632 uint64_t c1_se:1;
2633 uint64_t crs1_dr:1;
2634 uint64_t c1_wake:1;
2635 uint64_t c1_pmei:1;
2636 uint64_t c1_hpint:1;
2637 uint64_t c0_up_b0:1;
2638 uint64_t c0_up_b1:1;
2639 uint64_t c0_up_b2:1;
2640 uint64_t c0_up_wi:1;
2641 uint64_t c0_up_bx:1;
2642 uint64_t c0_un_b0:1;
2643 uint64_t c0_un_b1:1;
2644 uint64_t c0_un_b2:1;
2645 uint64_t c0_un_wi:1;
2646 uint64_t c0_un_bx:1;
2647 uint64_t c1_up_b0:1;
2648 uint64_t c1_up_b1:1;
2649 uint64_t c1_up_b2:1;
2650 uint64_t c1_up_wi:1;
2651 uint64_t c1_up_bx:1;
2652 uint64_t c1_un_b0:1;
2653 uint64_t c1_un_b1:1;
2654 uint64_t c1_un_b2:1;
2655 uint64_t c1_un_wi:1;
2656 uint64_t c1_un_bx:1;
2657 uint64_t c0_un_wf:1;
2658 uint64_t c1_un_wf:1;
2659 uint64_t c0_up_wf:1;
2660 uint64_t c1_up_wf:1;
2661 uint64_t c0_exc:1;
2662 uint64_t c1_exc:1;
2663 uint64_t c0_ldwn:1;
2664 uint64_t c1_ldwn:1;
2665 uint64_t int_a:1;
2666 uint64_t reserved_62_62:1;
2667 uint64_t mio_inta:1;
2668#endif
1485 } cn52xxp1; 2669 } cn52xxp1;
1486 struct cvmx_npei_int_sum_s cn56xx; 2670 struct cvmx_npei_int_sum_s cn56xx;
1487 struct cvmx_npei_int_sum_cn56xxp1 { 2671 struct cvmx_npei_int_sum_cn56xxp1 {
2672#ifdef __BIG_ENDIAN_BITFIELD
1488 uint64_t mio_inta:1; 2673 uint64_t mio_inta:1;
1489 uint64_t reserved_61_62:2; 2674 uint64_t reserved_61_62:2;
1490 uint64_t c1_ldwn:1; 2675 uint64_t c1_ldwn:1;
@@ -1545,12 +2730,75 @@ union cvmx_npei_int_sum {
1545 uint64_t bar0_to:1; 2730 uint64_t bar0_to:1;
1546 uint64_t rml_wto:1; 2731 uint64_t rml_wto:1;
1547 uint64_t rml_rto:1; 2732 uint64_t rml_rto:1;
2733#else
2734 uint64_t rml_rto:1;
2735 uint64_t rml_wto:1;
2736 uint64_t bar0_to:1;
2737 uint64_t iob2big:1;
2738 uint64_t dma0dbo:1;
2739 uint64_t dma1dbo:1;
2740 uint64_t dma2dbo:1;
2741 uint64_t dma3dbo:1;
2742 uint64_t dma4dbo:1;
2743 uint64_t dma0fi:1;
2744 uint64_t dma1fi:1;
2745 uint64_t dcnt0:1;
2746 uint64_t dcnt1:1;
2747 uint64_t dtime0:1;
2748 uint64_t dtime1:1;
2749 uint64_t reserved_15_18:4;
2750 uint64_t c0_aeri:1;
2751 uint64_t reserved_20_20:1;
2752 uint64_t c0_se:1;
2753 uint64_t reserved_22_22:1;
2754 uint64_t c0_wake:1;
2755 uint64_t c0_pmei:1;
2756 uint64_t c0_hpint:1;
2757 uint64_t c1_aeri:1;
2758 uint64_t reserved_27_27:1;
2759 uint64_t c1_se:1;
2760 uint64_t reserved_29_29:1;
2761 uint64_t c1_wake:1;
2762 uint64_t c1_pmei:1;
2763 uint64_t c1_hpint:1;
2764 uint64_t c0_up_b0:1;
2765 uint64_t c0_up_b1:1;
2766 uint64_t c0_up_b2:1;
2767 uint64_t c0_up_wi:1;
2768 uint64_t c0_up_bx:1;
2769 uint64_t c0_un_b0:1;
2770 uint64_t c0_un_b1:1;
2771 uint64_t c0_un_b2:1;
2772 uint64_t c0_un_wi:1;
2773 uint64_t c0_un_bx:1;
2774 uint64_t c1_up_b0:1;
2775 uint64_t c1_up_b1:1;
2776 uint64_t c1_up_b2:1;
2777 uint64_t c1_up_wi:1;
2778 uint64_t c1_up_bx:1;
2779 uint64_t c1_un_b0:1;
2780 uint64_t c1_un_b1:1;
2781 uint64_t c1_un_b2:1;
2782 uint64_t c1_un_wi:1;
2783 uint64_t c1_un_bx:1;
2784 uint64_t c0_un_wf:1;
2785 uint64_t c1_un_wf:1;
2786 uint64_t c0_up_wf:1;
2787 uint64_t c1_up_wf:1;
2788 uint64_t c0_exc:1;
2789 uint64_t c1_exc:1;
2790 uint64_t c0_ldwn:1;
2791 uint64_t c1_ldwn:1;
2792 uint64_t reserved_61_62:2;
2793 uint64_t mio_inta:1;
2794#endif
1548 } cn56xxp1; 2795 } cn56xxp1;
1549}; 2796};
1550 2797
1551union cvmx_npei_int_sum2 { 2798union cvmx_npei_int_sum2 {
1552 uint64_t u64; 2799 uint64_t u64;
1553 struct cvmx_npei_int_sum2_s { 2800 struct cvmx_npei_int_sum2_s {
2801#ifdef __BIG_ENDIAN_BITFIELD
1554 uint64_t mio_inta:1; 2802 uint64_t mio_inta:1;
1555 uint64_t reserved_62_62:1; 2803 uint64_t reserved_62_62:1;
1556 uint64_t int_a:1; 2804 uint64_t int_a:1;
@@ -1612,6 +2860,69 @@ union cvmx_npei_int_sum2 {
1612 uint64_t bar0_to:1; 2860 uint64_t bar0_to:1;
1613 uint64_t rml_wto:1; 2861 uint64_t rml_wto:1;
1614 uint64_t rml_rto:1; 2862 uint64_t rml_rto:1;
2863#else
2864 uint64_t rml_rto:1;
2865 uint64_t rml_wto:1;
2866 uint64_t bar0_to:1;
2867 uint64_t iob2big:1;
2868 uint64_t dma0dbo:1;
2869 uint64_t dma1dbo:1;
2870 uint64_t dma2dbo:1;
2871 uint64_t dma3dbo:1;
2872 uint64_t reserved_8_8:1;
2873 uint64_t dma0fi:1;
2874 uint64_t dma1fi:1;
2875 uint64_t dcnt0:1;
2876 uint64_t dcnt1:1;
2877 uint64_t dtime0:1;
2878 uint64_t dtime1:1;
2879 uint64_t reserved_15_18:4;
2880 uint64_t c0_aeri:1;
2881 uint64_t crs0_er:1;
2882 uint64_t c0_se:1;
2883 uint64_t crs0_dr:1;
2884 uint64_t c0_wake:1;
2885 uint64_t c0_pmei:1;
2886 uint64_t c0_hpint:1;
2887 uint64_t c1_aeri:1;
2888 uint64_t crs1_er:1;
2889 uint64_t c1_se:1;
2890 uint64_t crs1_dr:1;
2891 uint64_t c1_wake:1;
2892 uint64_t c1_pmei:1;
2893 uint64_t c1_hpint:1;
2894 uint64_t c0_up_b0:1;
2895 uint64_t c0_up_b1:1;
2896 uint64_t c0_up_b2:1;
2897 uint64_t c0_up_wi:1;
2898 uint64_t c0_up_bx:1;
2899 uint64_t c0_un_b0:1;
2900 uint64_t c0_un_b1:1;
2901 uint64_t c0_un_b2:1;
2902 uint64_t c0_un_wi:1;
2903 uint64_t c0_un_bx:1;
2904 uint64_t c1_up_b0:1;
2905 uint64_t c1_up_b1:1;
2906 uint64_t c1_up_b2:1;
2907 uint64_t c1_up_wi:1;
2908 uint64_t c1_up_bx:1;
2909 uint64_t c1_un_b0:1;
2910 uint64_t c1_un_b1:1;
2911 uint64_t c1_un_b2:1;
2912 uint64_t c1_un_wi:1;
2913 uint64_t c1_un_bx:1;
2914 uint64_t c0_un_wf:1;
2915 uint64_t c1_un_wf:1;
2916 uint64_t c0_up_wf:1;
2917 uint64_t c1_up_wf:1;
2918 uint64_t c0_exc:1;
2919 uint64_t c1_exc:1;
2920 uint64_t c0_ldwn:1;
2921 uint64_t c1_ldwn:1;
2922 uint64_t int_a:1;
2923 uint64_t reserved_62_62:1;
2924 uint64_t mio_inta:1;
2925#endif
1615 } s; 2926 } s;
1616 struct cvmx_npei_int_sum2_s cn52xx; 2927 struct cvmx_npei_int_sum2_s cn52xx;
1617 struct cvmx_npei_int_sum2_s cn52xxp1; 2928 struct cvmx_npei_int_sum2_s cn52xxp1;
@@ -1621,7 +2932,11 @@ union cvmx_npei_int_sum2 {
1621union cvmx_npei_last_win_rdata0 { 2932union cvmx_npei_last_win_rdata0 {
1622 uint64_t u64; 2933 uint64_t u64;
1623 struct cvmx_npei_last_win_rdata0_s { 2934 struct cvmx_npei_last_win_rdata0_s {
2935#ifdef __BIG_ENDIAN_BITFIELD
1624 uint64_t data:64; 2936 uint64_t data:64;
2937#else
2938 uint64_t data:64;
2939#endif
1625 } s; 2940 } s;
1626 struct cvmx_npei_last_win_rdata0_s cn52xx; 2941 struct cvmx_npei_last_win_rdata0_s cn52xx;
1627 struct cvmx_npei_last_win_rdata0_s cn52xxp1; 2942 struct cvmx_npei_last_win_rdata0_s cn52xxp1;
@@ -1632,7 +2947,11 @@ union cvmx_npei_last_win_rdata0 {
1632union cvmx_npei_last_win_rdata1 { 2947union cvmx_npei_last_win_rdata1 {
1633 uint64_t u64; 2948 uint64_t u64;
1634 struct cvmx_npei_last_win_rdata1_s { 2949 struct cvmx_npei_last_win_rdata1_s {
2950#ifdef __BIG_ENDIAN_BITFIELD
2951 uint64_t data:64;
2952#else
1635 uint64_t data:64; 2953 uint64_t data:64;
2954#endif
1636 } s; 2955 } s;
1637 struct cvmx_npei_last_win_rdata1_s cn52xx; 2956 struct cvmx_npei_last_win_rdata1_s cn52xx;
1638 struct cvmx_npei_last_win_rdata1_s cn52xxp1; 2957 struct cvmx_npei_last_win_rdata1_s cn52xxp1;
@@ -1643,9 +2962,15 @@ union cvmx_npei_last_win_rdata1 {
1643union cvmx_npei_mem_access_ctl { 2962union cvmx_npei_mem_access_ctl {
1644 uint64_t u64; 2963 uint64_t u64;
1645 struct cvmx_npei_mem_access_ctl_s { 2964 struct cvmx_npei_mem_access_ctl_s {
2965#ifdef __BIG_ENDIAN_BITFIELD
1646 uint64_t reserved_14_63:50; 2966 uint64_t reserved_14_63:50;
1647 uint64_t max_word:4; 2967 uint64_t max_word:4;
1648 uint64_t timer:10; 2968 uint64_t timer:10;
2969#else
2970 uint64_t timer:10;
2971 uint64_t max_word:4;
2972 uint64_t reserved_14_63:50;
2973#endif
1649 } s; 2974 } s;
1650 struct cvmx_npei_mem_access_ctl_s cn52xx; 2975 struct cvmx_npei_mem_access_ctl_s cn52xx;
1651 struct cvmx_npei_mem_access_ctl_s cn52xxp1; 2976 struct cvmx_npei_mem_access_ctl_s cn52xxp1;
@@ -1656,6 +2981,7 @@ union cvmx_npei_mem_access_ctl {
1656union cvmx_npei_mem_access_subidx { 2981union cvmx_npei_mem_access_subidx {
1657 uint64_t u64; 2982 uint64_t u64;
1658 struct cvmx_npei_mem_access_subidx_s { 2983 struct cvmx_npei_mem_access_subidx_s {
2984#ifdef __BIG_ENDIAN_BITFIELD
1659 uint64_t reserved_42_63:22; 2985 uint64_t reserved_42_63:22;
1660 uint64_t zero:1; 2986 uint64_t zero:1;
1661 uint64_t port:2; 2987 uint64_t port:2;
@@ -1667,6 +2993,19 @@ union cvmx_npei_mem_access_subidx {
1667 uint64_t ror:1; 2993 uint64_t ror:1;
1668 uint64_t row:1; 2994 uint64_t row:1;
1669 uint64_t ba:30; 2995 uint64_t ba:30;
2996#else
2997 uint64_t ba:30;
2998 uint64_t row:1;
2999 uint64_t ror:1;
3000 uint64_t nsw:1;
3001 uint64_t nsr:1;
3002 uint64_t esw:2;
3003 uint64_t esr:2;
3004 uint64_t nmerge:1;
3005 uint64_t port:2;
3006 uint64_t zero:1;
3007 uint64_t reserved_42_63:22;
3008#endif
1670 } s; 3009 } s;
1671 struct cvmx_npei_mem_access_subidx_s cn52xx; 3010 struct cvmx_npei_mem_access_subidx_s cn52xx;
1672 struct cvmx_npei_mem_access_subidx_s cn52xxp1; 3011 struct cvmx_npei_mem_access_subidx_s cn52xxp1;
@@ -1677,7 +3016,11 @@ union cvmx_npei_mem_access_subidx {
1677union cvmx_npei_msi_enb0 { 3016union cvmx_npei_msi_enb0 {
1678 uint64_t u64; 3017 uint64_t u64;
1679 struct cvmx_npei_msi_enb0_s { 3018 struct cvmx_npei_msi_enb0_s {
3019#ifdef __BIG_ENDIAN_BITFIELD
1680 uint64_t enb:64; 3020 uint64_t enb:64;
3021#else
3022 uint64_t enb:64;
3023#endif
1681 } s; 3024 } s;
1682 struct cvmx_npei_msi_enb0_s cn52xx; 3025 struct cvmx_npei_msi_enb0_s cn52xx;
1683 struct cvmx_npei_msi_enb0_s cn52xxp1; 3026 struct cvmx_npei_msi_enb0_s cn52xxp1;
@@ -1688,7 +3031,11 @@ union cvmx_npei_msi_enb0 {
1688union cvmx_npei_msi_enb1 { 3031union cvmx_npei_msi_enb1 {
1689 uint64_t u64; 3032 uint64_t u64;
1690 struct cvmx_npei_msi_enb1_s { 3033 struct cvmx_npei_msi_enb1_s {
3034#ifdef __BIG_ENDIAN_BITFIELD
3035 uint64_t enb:64;
3036#else
1691 uint64_t enb:64; 3037 uint64_t enb:64;
3038#endif
1692 } s; 3039 } s;
1693 struct cvmx_npei_msi_enb1_s cn52xx; 3040 struct cvmx_npei_msi_enb1_s cn52xx;
1694 struct cvmx_npei_msi_enb1_s cn52xxp1; 3041 struct cvmx_npei_msi_enb1_s cn52xxp1;
@@ -1699,7 +3046,11 @@ union cvmx_npei_msi_enb1 {
1699union cvmx_npei_msi_enb2 { 3046union cvmx_npei_msi_enb2 {
1700 uint64_t u64; 3047 uint64_t u64;
1701 struct cvmx_npei_msi_enb2_s { 3048 struct cvmx_npei_msi_enb2_s {
3049#ifdef __BIG_ENDIAN_BITFIELD
3050 uint64_t enb:64;
3051#else
1702 uint64_t enb:64; 3052 uint64_t enb:64;
3053#endif
1703 } s; 3054 } s;
1704 struct cvmx_npei_msi_enb2_s cn52xx; 3055 struct cvmx_npei_msi_enb2_s cn52xx;
1705 struct cvmx_npei_msi_enb2_s cn52xxp1; 3056 struct cvmx_npei_msi_enb2_s cn52xxp1;
@@ -1710,7 +3061,11 @@ union cvmx_npei_msi_enb2 {
1710union cvmx_npei_msi_enb3 { 3061union cvmx_npei_msi_enb3 {
1711 uint64_t u64; 3062 uint64_t u64;
1712 struct cvmx_npei_msi_enb3_s { 3063 struct cvmx_npei_msi_enb3_s {
3064#ifdef __BIG_ENDIAN_BITFIELD
1713 uint64_t enb:64; 3065 uint64_t enb:64;
3066#else
3067 uint64_t enb:64;
3068#endif
1714 } s; 3069 } s;
1715 struct cvmx_npei_msi_enb3_s cn52xx; 3070 struct cvmx_npei_msi_enb3_s cn52xx;
1716 struct cvmx_npei_msi_enb3_s cn52xxp1; 3071 struct cvmx_npei_msi_enb3_s cn52xxp1;
@@ -1721,7 +3076,11 @@ union cvmx_npei_msi_enb3 {
1721union cvmx_npei_msi_rcv0 { 3076union cvmx_npei_msi_rcv0 {
1722 uint64_t u64; 3077 uint64_t u64;
1723 struct cvmx_npei_msi_rcv0_s { 3078 struct cvmx_npei_msi_rcv0_s {
3079#ifdef __BIG_ENDIAN_BITFIELD
1724 uint64_t intr:64; 3080 uint64_t intr:64;
3081#else
3082 uint64_t intr:64;
3083#endif
1725 } s; 3084 } s;
1726 struct cvmx_npei_msi_rcv0_s cn52xx; 3085 struct cvmx_npei_msi_rcv0_s cn52xx;
1727 struct cvmx_npei_msi_rcv0_s cn52xxp1; 3086 struct cvmx_npei_msi_rcv0_s cn52xxp1;
@@ -1732,7 +3091,11 @@ union cvmx_npei_msi_rcv0 {
1732union cvmx_npei_msi_rcv1 { 3091union cvmx_npei_msi_rcv1 {
1733 uint64_t u64; 3092 uint64_t u64;
1734 struct cvmx_npei_msi_rcv1_s { 3093 struct cvmx_npei_msi_rcv1_s {
3094#ifdef __BIG_ENDIAN_BITFIELD
3095 uint64_t intr:64;
3096#else
1735 uint64_t intr:64; 3097 uint64_t intr:64;
3098#endif
1736 } s; 3099 } s;
1737 struct cvmx_npei_msi_rcv1_s cn52xx; 3100 struct cvmx_npei_msi_rcv1_s cn52xx;
1738 struct cvmx_npei_msi_rcv1_s cn52xxp1; 3101 struct cvmx_npei_msi_rcv1_s cn52xxp1;
@@ -1743,7 +3106,11 @@ union cvmx_npei_msi_rcv1 {
1743union cvmx_npei_msi_rcv2 { 3106union cvmx_npei_msi_rcv2 {
1744 uint64_t u64; 3107 uint64_t u64;
1745 struct cvmx_npei_msi_rcv2_s { 3108 struct cvmx_npei_msi_rcv2_s {
3109#ifdef __BIG_ENDIAN_BITFIELD
3110 uint64_t intr:64;
3111#else
1746 uint64_t intr:64; 3112 uint64_t intr:64;
3113#endif
1747 } s; 3114 } s;
1748 struct cvmx_npei_msi_rcv2_s cn52xx; 3115 struct cvmx_npei_msi_rcv2_s cn52xx;
1749 struct cvmx_npei_msi_rcv2_s cn52xxp1; 3116 struct cvmx_npei_msi_rcv2_s cn52xxp1;
@@ -1754,7 +3121,11 @@ union cvmx_npei_msi_rcv2 {
1754union cvmx_npei_msi_rcv3 { 3121union cvmx_npei_msi_rcv3 {
1755 uint64_t u64; 3122 uint64_t u64;
1756 struct cvmx_npei_msi_rcv3_s { 3123 struct cvmx_npei_msi_rcv3_s {
3124#ifdef __BIG_ENDIAN_BITFIELD
1757 uint64_t intr:64; 3125 uint64_t intr:64;
3126#else
3127 uint64_t intr:64;
3128#endif
1758 } s; 3129 } s;
1759 struct cvmx_npei_msi_rcv3_s cn52xx; 3130 struct cvmx_npei_msi_rcv3_s cn52xx;
1760 struct cvmx_npei_msi_rcv3_s cn52xxp1; 3131 struct cvmx_npei_msi_rcv3_s cn52xxp1;
@@ -1765,9 +3136,15 @@ union cvmx_npei_msi_rcv3 {
1765union cvmx_npei_msi_rd_map { 3136union cvmx_npei_msi_rd_map {
1766 uint64_t u64; 3137 uint64_t u64;
1767 struct cvmx_npei_msi_rd_map_s { 3138 struct cvmx_npei_msi_rd_map_s {
3139#ifdef __BIG_ENDIAN_BITFIELD
1768 uint64_t reserved_16_63:48; 3140 uint64_t reserved_16_63:48;
1769 uint64_t rd_int:8; 3141 uint64_t rd_int:8;
1770 uint64_t msi_int:8; 3142 uint64_t msi_int:8;
3143#else
3144 uint64_t msi_int:8;
3145 uint64_t rd_int:8;
3146 uint64_t reserved_16_63:48;
3147#endif
1771 } s; 3148 } s;
1772 struct cvmx_npei_msi_rd_map_s cn52xx; 3149 struct cvmx_npei_msi_rd_map_s cn52xx;
1773 struct cvmx_npei_msi_rd_map_s cn52xxp1; 3150 struct cvmx_npei_msi_rd_map_s cn52xxp1;
@@ -1778,7 +3155,11 @@ union cvmx_npei_msi_rd_map {
1778union cvmx_npei_msi_w1c_enb0 { 3155union cvmx_npei_msi_w1c_enb0 {
1779 uint64_t u64; 3156 uint64_t u64;
1780 struct cvmx_npei_msi_w1c_enb0_s { 3157 struct cvmx_npei_msi_w1c_enb0_s {
3158#ifdef __BIG_ENDIAN_BITFIELD
1781 uint64_t clr:64; 3159 uint64_t clr:64;
3160#else
3161 uint64_t clr:64;
3162#endif
1782 } s; 3163 } s;
1783 struct cvmx_npei_msi_w1c_enb0_s cn52xx; 3164 struct cvmx_npei_msi_w1c_enb0_s cn52xx;
1784 struct cvmx_npei_msi_w1c_enb0_s cn56xx; 3165 struct cvmx_npei_msi_w1c_enb0_s cn56xx;
@@ -1787,7 +3168,11 @@ union cvmx_npei_msi_w1c_enb0 {
1787union cvmx_npei_msi_w1c_enb1 { 3168union cvmx_npei_msi_w1c_enb1 {
1788 uint64_t u64; 3169 uint64_t u64;
1789 struct cvmx_npei_msi_w1c_enb1_s { 3170 struct cvmx_npei_msi_w1c_enb1_s {
3171#ifdef __BIG_ENDIAN_BITFIELD
3172 uint64_t clr:64;
3173#else
1790 uint64_t clr:64; 3174 uint64_t clr:64;
3175#endif
1791 } s; 3176 } s;
1792 struct cvmx_npei_msi_w1c_enb1_s cn52xx; 3177 struct cvmx_npei_msi_w1c_enb1_s cn52xx;
1793 struct cvmx_npei_msi_w1c_enb1_s cn56xx; 3178 struct cvmx_npei_msi_w1c_enb1_s cn56xx;
@@ -1796,7 +3181,11 @@ union cvmx_npei_msi_w1c_enb1 {
1796union cvmx_npei_msi_w1c_enb2 { 3181union cvmx_npei_msi_w1c_enb2 {
1797 uint64_t u64; 3182 uint64_t u64;
1798 struct cvmx_npei_msi_w1c_enb2_s { 3183 struct cvmx_npei_msi_w1c_enb2_s {
3184#ifdef __BIG_ENDIAN_BITFIELD
3185 uint64_t clr:64;
3186#else
1799 uint64_t clr:64; 3187 uint64_t clr:64;
3188#endif
1800 } s; 3189 } s;
1801 struct cvmx_npei_msi_w1c_enb2_s cn52xx; 3190 struct cvmx_npei_msi_w1c_enb2_s cn52xx;
1802 struct cvmx_npei_msi_w1c_enb2_s cn56xx; 3191 struct cvmx_npei_msi_w1c_enb2_s cn56xx;
@@ -1805,7 +3194,11 @@ union cvmx_npei_msi_w1c_enb2 {
1805union cvmx_npei_msi_w1c_enb3 { 3194union cvmx_npei_msi_w1c_enb3 {
1806 uint64_t u64; 3195 uint64_t u64;
1807 struct cvmx_npei_msi_w1c_enb3_s { 3196 struct cvmx_npei_msi_w1c_enb3_s {
3197#ifdef __BIG_ENDIAN_BITFIELD
1808 uint64_t clr:64; 3198 uint64_t clr:64;
3199#else
3200 uint64_t clr:64;
3201#endif
1809 } s; 3202 } s;
1810 struct cvmx_npei_msi_w1c_enb3_s cn52xx; 3203 struct cvmx_npei_msi_w1c_enb3_s cn52xx;
1811 struct cvmx_npei_msi_w1c_enb3_s cn56xx; 3204 struct cvmx_npei_msi_w1c_enb3_s cn56xx;
@@ -1814,7 +3207,11 @@ union cvmx_npei_msi_w1c_enb3 {
1814union cvmx_npei_msi_w1s_enb0 { 3207union cvmx_npei_msi_w1s_enb0 {
1815 uint64_t u64; 3208 uint64_t u64;
1816 struct cvmx_npei_msi_w1s_enb0_s { 3209 struct cvmx_npei_msi_w1s_enb0_s {
3210#ifdef __BIG_ENDIAN_BITFIELD
3211 uint64_t set:64;
3212#else
1817 uint64_t set:64; 3213 uint64_t set:64;
3214#endif
1818 } s; 3215 } s;
1819 struct cvmx_npei_msi_w1s_enb0_s cn52xx; 3216 struct cvmx_npei_msi_w1s_enb0_s cn52xx;
1820 struct cvmx_npei_msi_w1s_enb0_s cn56xx; 3217 struct cvmx_npei_msi_w1s_enb0_s cn56xx;
@@ -1823,7 +3220,11 @@ union cvmx_npei_msi_w1s_enb0 {
1823union cvmx_npei_msi_w1s_enb1 { 3220union cvmx_npei_msi_w1s_enb1 {
1824 uint64_t u64; 3221 uint64_t u64;
1825 struct cvmx_npei_msi_w1s_enb1_s { 3222 struct cvmx_npei_msi_w1s_enb1_s {
3223#ifdef __BIG_ENDIAN_BITFIELD
3224 uint64_t set:64;
3225#else
1826 uint64_t set:64; 3226 uint64_t set:64;
3227#endif
1827 } s; 3228 } s;
1828 struct cvmx_npei_msi_w1s_enb1_s cn52xx; 3229 struct cvmx_npei_msi_w1s_enb1_s cn52xx;
1829 struct cvmx_npei_msi_w1s_enb1_s cn56xx; 3230 struct cvmx_npei_msi_w1s_enb1_s cn56xx;
@@ -1832,7 +3233,11 @@ union cvmx_npei_msi_w1s_enb1 {
1832union cvmx_npei_msi_w1s_enb2 { 3233union cvmx_npei_msi_w1s_enb2 {
1833 uint64_t u64; 3234 uint64_t u64;
1834 struct cvmx_npei_msi_w1s_enb2_s { 3235 struct cvmx_npei_msi_w1s_enb2_s {
3236#ifdef __BIG_ENDIAN_BITFIELD
3237 uint64_t set:64;
3238#else
1835 uint64_t set:64; 3239 uint64_t set:64;
3240#endif
1836 } s; 3241 } s;
1837 struct cvmx_npei_msi_w1s_enb2_s cn52xx; 3242 struct cvmx_npei_msi_w1s_enb2_s cn52xx;
1838 struct cvmx_npei_msi_w1s_enb2_s cn56xx; 3243 struct cvmx_npei_msi_w1s_enb2_s cn56xx;
@@ -1841,7 +3246,11 @@ union cvmx_npei_msi_w1s_enb2 {
1841union cvmx_npei_msi_w1s_enb3 { 3246union cvmx_npei_msi_w1s_enb3 {
1842 uint64_t u64; 3247 uint64_t u64;
1843 struct cvmx_npei_msi_w1s_enb3_s { 3248 struct cvmx_npei_msi_w1s_enb3_s {
3249#ifdef __BIG_ENDIAN_BITFIELD
1844 uint64_t set:64; 3250 uint64_t set:64;
3251#else
3252 uint64_t set:64;
3253#endif
1845 } s; 3254 } s;
1846 struct cvmx_npei_msi_w1s_enb3_s cn52xx; 3255 struct cvmx_npei_msi_w1s_enb3_s cn52xx;
1847 struct cvmx_npei_msi_w1s_enb3_s cn56xx; 3256 struct cvmx_npei_msi_w1s_enb3_s cn56xx;
@@ -1850,9 +3259,15 @@ union cvmx_npei_msi_w1s_enb3 {
1850union cvmx_npei_msi_wr_map { 3259union cvmx_npei_msi_wr_map {
1851 uint64_t u64; 3260 uint64_t u64;
1852 struct cvmx_npei_msi_wr_map_s { 3261 struct cvmx_npei_msi_wr_map_s {
3262#ifdef __BIG_ENDIAN_BITFIELD
1853 uint64_t reserved_16_63:48; 3263 uint64_t reserved_16_63:48;
1854 uint64_t ciu_int:8; 3264 uint64_t ciu_int:8;
1855 uint64_t msi_int:8; 3265 uint64_t msi_int:8;
3266#else
3267 uint64_t msi_int:8;
3268 uint64_t ciu_int:8;
3269 uint64_t reserved_16_63:48;
3270#endif
1856 } s; 3271 } s;
1857 struct cvmx_npei_msi_wr_map_s cn52xx; 3272 struct cvmx_npei_msi_wr_map_s cn52xx;
1858 struct cvmx_npei_msi_wr_map_s cn52xxp1; 3273 struct cvmx_npei_msi_wr_map_s cn52xxp1;
@@ -1863,6 +3278,7 @@ union cvmx_npei_msi_wr_map {
1863union cvmx_npei_pcie_credit_cnt { 3278union cvmx_npei_pcie_credit_cnt {
1864 uint64_t u64; 3279 uint64_t u64;
1865 struct cvmx_npei_pcie_credit_cnt_s { 3280 struct cvmx_npei_pcie_credit_cnt_s {
3281#ifdef __BIG_ENDIAN_BITFIELD
1866 uint64_t reserved_48_63:16; 3282 uint64_t reserved_48_63:16;
1867 uint64_t p1_ccnt:8; 3283 uint64_t p1_ccnt:8;
1868 uint64_t p1_ncnt:8; 3284 uint64_t p1_ncnt:8;
@@ -1870,6 +3286,15 @@ union cvmx_npei_pcie_credit_cnt {
1870 uint64_t p0_ccnt:8; 3286 uint64_t p0_ccnt:8;
1871 uint64_t p0_ncnt:8; 3287 uint64_t p0_ncnt:8;
1872 uint64_t p0_pcnt:8; 3288 uint64_t p0_pcnt:8;
3289#else
3290 uint64_t p0_pcnt:8;
3291 uint64_t p0_ncnt:8;
3292 uint64_t p0_ccnt:8;
3293 uint64_t p1_pcnt:8;
3294 uint64_t p1_ncnt:8;
3295 uint64_t p1_ccnt:8;
3296 uint64_t reserved_48_63:16;
3297#endif
1873 } s; 3298 } s;
1874 struct cvmx_npei_pcie_credit_cnt_s cn52xx; 3299 struct cvmx_npei_pcie_credit_cnt_s cn52xx;
1875 struct cvmx_npei_pcie_credit_cnt_s cn56xx; 3300 struct cvmx_npei_pcie_credit_cnt_s cn56xx;
@@ -1878,8 +3303,13 @@ union cvmx_npei_pcie_credit_cnt {
1878union cvmx_npei_pcie_msi_rcv { 3303union cvmx_npei_pcie_msi_rcv {
1879 uint64_t u64; 3304 uint64_t u64;
1880 struct cvmx_npei_pcie_msi_rcv_s { 3305 struct cvmx_npei_pcie_msi_rcv_s {
3306#ifdef __BIG_ENDIAN_BITFIELD
1881 uint64_t reserved_8_63:56; 3307 uint64_t reserved_8_63:56;
1882 uint64_t intr:8; 3308 uint64_t intr:8;
3309#else
3310 uint64_t intr:8;
3311 uint64_t reserved_8_63:56;
3312#endif
1883 } s; 3313 } s;
1884 struct cvmx_npei_pcie_msi_rcv_s cn52xx; 3314 struct cvmx_npei_pcie_msi_rcv_s cn52xx;
1885 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1; 3315 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
@@ -1890,9 +3320,15 @@ union cvmx_npei_pcie_msi_rcv {
1890union cvmx_npei_pcie_msi_rcv_b1 { 3320union cvmx_npei_pcie_msi_rcv_b1 {
1891 uint64_t u64; 3321 uint64_t u64;
1892 struct cvmx_npei_pcie_msi_rcv_b1_s { 3322 struct cvmx_npei_pcie_msi_rcv_b1_s {
3323#ifdef __BIG_ENDIAN_BITFIELD
1893 uint64_t reserved_16_63:48; 3324 uint64_t reserved_16_63:48;
1894 uint64_t intr:8; 3325 uint64_t intr:8;
1895 uint64_t reserved_0_7:8; 3326 uint64_t reserved_0_7:8;
3327#else
3328 uint64_t reserved_0_7:8;
3329 uint64_t intr:8;
3330 uint64_t reserved_16_63:48;
3331#endif
1896 } s; 3332 } s;
1897 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx; 3333 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
1898 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1; 3334 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
@@ -1903,9 +3339,15 @@ union cvmx_npei_pcie_msi_rcv_b1 {
1903union cvmx_npei_pcie_msi_rcv_b2 { 3339union cvmx_npei_pcie_msi_rcv_b2 {
1904 uint64_t u64; 3340 uint64_t u64;
1905 struct cvmx_npei_pcie_msi_rcv_b2_s { 3341 struct cvmx_npei_pcie_msi_rcv_b2_s {
3342#ifdef __BIG_ENDIAN_BITFIELD
1906 uint64_t reserved_24_63:40; 3343 uint64_t reserved_24_63:40;
1907 uint64_t intr:8; 3344 uint64_t intr:8;
1908 uint64_t reserved_0_15:16; 3345 uint64_t reserved_0_15:16;
3346#else
3347 uint64_t reserved_0_15:16;
3348 uint64_t intr:8;
3349 uint64_t reserved_24_63:40;
3350#endif
1909 } s; 3351 } s;
1910 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx; 3352 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
1911 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1; 3353 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
@@ -1916,9 +3358,15 @@ union cvmx_npei_pcie_msi_rcv_b2 {
1916union cvmx_npei_pcie_msi_rcv_b3 { 3358union cvmx_npei_pcie_msi_rcv_b3 {
1917 uint64_t u64; 3359 uint64_t u64;
1918 struct cvmx_npei_pcie_msi_rcv_b3_s { 3360 struct cvmx_npei_pcie_msi_rcv_b3_s {
3361#ifdef __BIG_ENDIAN_BITFIELD
1919 uint64_t reserved_32_63:32; 3362 uint64_t reserved_32_63:32;
1920 uint64_t intr:8; 3363 uint64_t intr:8;
1921 uint64_t reserved_0_23:24; 3364 uint64_t reserved_0_23:24;
3365#else
3366 uint64_t reserved_0_23:24;
3367 uint64_t intr:8;
3368 uint64_t reserved_32_63:32;
3369#endif
1922 } s; 3370 } s;
1923 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx; 3371 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
1924 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1; 3372 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
@@ -1929,9 +3377,15 @@ union cvmx_npei_pcie_msi_rcv_b3 {
1929union cvmx_npei_pktx_cnts { 3377union cvmx_npei_pktx_cnts {
1930 uint64_t u64; 3378 uint64_t u64;
1931 struct cvmx_npei_pktx_cnts_s { 3379 struct cvmx_npei_pktx_cnts_s {
3380#ifdef __BIG_ENDIAN_BITFIELD
1932 uint64_t reserved_54_63:10; 3381 uint64_t reserved_54_63:10;
1933 uint64_t timer:22; 3382 uint64_t timer:22;
1934 uint64_t cnt:32; 3383 uint64_t cnt:32;
3384#else
3385 uint64_t cnt:32;
3386 uint64_t timer:22;
3387 uint64_t reserved_54_63:10;
3388#endif
1935 } s; 3389 } s;
1936 struct cvmx_npei_pktx_cnts_s cn52xx; 3390 struct cvmx_npei_pktx_cnts_s cn52xx;
1937 struct cvmx_npei_pktx_cnts_s cn56xx; 3391 struct cvmx_npei_pktx_cnts_s cn56xx;
@@ -1940,8 +3394,13 @@ union cvmx_npei_pktx_cnts {
1940union cvmx_npei_pktx_in_bp { 3394union cvmx_npei_pktx_in_bp {
1941 uint64_t u64; 3395 uint64_t u64;
1942 struct cvmx_npei_pktx_in_bp_s { 3396 struct cvmx_npei_pktx_in_bp_s {
3397#ifdef __BIG_ENDIAN_BITFIELD
1943 uint64_t wmark:32; 3398 uint64_t wmark:32;
1944 uint64_t cnt:32; 3399 uint64_t cnt:32;
3400#else
3401 uint64_t cnt:32;
3402 uint64_t wmark:32;
3403#endif
1945 } s; 3404 } s;
1946 struct cvmx_npei_pktx_in_bp_s cn52xx; 3405 struct cvmx_npei_pktx_in_bp_s cn52xx;
1947 struct cvmx_npei_pktx_in_bp_s cn56xx; 3406 struct cvmx_npei_pktx_in_bp_s cn56xx;
@@ -1950,8 +3409,13 @@ union cvmx_npei_pktx_in_bp {
1950union cvmx_npei_pktx_instr_baddr { 3409union cvmx_npei_pktx_instr_baddr {
1951 uint64_t u64; 3410 uint64_t u64;
1952 struct cvmx_npei_pktx_instr_baddr_s { 3411 struct cvmx_npei_pktx_instr_baddr_s {
3412#ifdef __BIG_ENDIAN_BITFIELD
1953 uint64_t addr:61; 3413 uint64_t addr:61;
1954 uint64_t reserved_0_2:3; 3414 uint64_t reserved_0_2:3;
3415#else
3416 uint64_t reserved_0_2:3;
3417 uint64_t addr:61;
3418#endif
1955 } s; 3419 } s;
1956 struct cvmx_npei_pktx_instr_baddr_s cn52xx; 3420 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
1957 struct cvmx_npei_pktx_instr_baddr_s cn56xx; 3421 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
@@ -1960,8 +3424,13 @@ union cvmx_npei_pktx_instr_baddr {
1960union cvmx_npei_pktx_instr_baoff_dbell { 3424union cvmx_npei_pktx_instr_baoff_dbell {
1961 uint64_t u64; 3425 uint64_t u64;
1962 struct cvmx_npei_pktx_instr_baoff_dbell_s { 3426 struct cvmx_npei_pktx_instr_baoff_dbell_s {
3427#ifdef __BIG_ENDIAN_BITFIELD
1963 uint64_t aoff:32; 3428 uint64_t aoff:32;
1964 uint64_t dbell:32; 3429 uint64_t dbell:32;
3430#else
3431 uint64_t dbell:32;
3432 uint64_t aoff:32;
3433#endif
1965 } s; 3434 } s;
1966 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; 3435 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
1967 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; 3436 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
@@ -1970,11 +3439,19 @@ union cvmx_npei_pktx_instr_baoff_dbell {
1970union cvmx_npei_pktx_instr_fifo_rsize { 3439union cvmx_npei_pktx_instr_fifo_rsize {
1971 uint64_t u64; 3440 uint64_t u64;
1972 struct cvmx_npei_pktx_instr_fifo_rsize_s { 3441 struct cvmx_npei_pktx_instr_fifo_rsize_s {
3442#ifdef __BIG_ENDIAN_BITFIELD
1973 uint64_t max:9; 3443 uint64_t max:9;
1974 uint64_t rrp:9; 3444 uint64_t rrp:9;
1975 uint64_t wrp:9; 3445 uint64_t wrp:9;
1976 uint64_t fcnt:5; 3446 uint64_t fcnt:5;
1977 uint64_t rsize:32; 3447 uint64_t rsize:32;
3448#else
3449 uint64_t rsize:32;
3450 uint64_t fcnt:5;
3451 uint64_t wrp:9;
3452 uint64_t rrp:9;
3453 uint64_t max:9;
3454#endif
1978 } s; 3455 } s;
1979 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; 3456 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
1980 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; 3457 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
@@ -1983,6 +3460,7 @@ union cvmx_npei_pktx_instr_fifo_rsize {
1983union cvmx_npei_pktx_instr_header { 3460union cvmx_npei_pktx_instr_header {
1984 uint64_t u64; 3461 uint64_t u64;
1985 struct cvmx_npei_pktx_instr_header_s { 3462 struct cvmx_npei_pktx_instr_header_s {
3463#ifdef __BIG_ENDIAN_BITFIELD
1986 uint64_t reserved_44_63:20; 3464 uint64_t reserved_44_63:20;
1987 uint64_t pbp:1; 3465 uint64_t pbp:1;
1988 uint64_t reserved_38_42:5; 3466 uint64_t reserved_38_42:5;
@@ -1996,6 +3474,21 @@ union cvmx_npei_pktx_instr_header {
1996 uint64_t reserved_13_13:1; 3474 uint64_t reserved_13_13:1;
1997 uint64_t skp_len:7; 3475 uint64_t skp_len:7;
1998 uint64_t reserved_0_5:6; 3476 uint64_t reserved_0_5:6;
3477#else
3478 uint64_t reserved_0_5:6;
3479 uint64_t skp_len:7;
3480 uint64_t reserved_13_13:1;
3481 uint64_t par_mode:2;
3482 uint64_t reserved_16_20:5;
3483 uint64_t use_ihdr:1;
3484 uint64_t reserved_22_27:6;
3485 uint64_t rskp_len:7;
3486 uint64_t reserved_35_35:1;
3487 uint64_t rparmode:2;
3488 uint64_t reserved_38_42:5;
3489 uint64_t pbp:1;
3490 uint64_t reserved_44_63:20;
3491#endif
1999 } s; 3492 } s;
2000 struct cvmx_npei_pktx_instr_header_s cn52xx; 3493 struct cvmx_npei_pktx_instr_header_s cn52xx;
2001 struct cvmx_npei_pktx_instr_header_s cn56xx; 3494 struct cvmx_npei_pktx_instr_header_s cn56xx;
@@ -2004,8 +3497,13 @@ union cvmx_npei_pktx_instr_header {
2004union cvmx_npei_pktx_slist_baddr { 3497union cvmx_npei_pktx_slist_baddr {
2005 uint64_t u64; 3498 uint64_t u64;
2006 struct cvmx_npei_pktx_slist_baddr_s { 3499 struct cvmx_npei_pktx_slist_baddr_s {
3500#ifdef __BIG_ENDIAN_BITFIELD
2007 uint64_t addr:60; 3501 uint64_t addr:60;
2008 uint64_t reserved_0_3:4; 3502 uint64_t reserved_0_3:4;
3503#else
3504 uint64_t reserved_0_3:4;
3505 uint64_t addr:60;
3506#endif
2009 } s; 3507 } s;
2010 struct cvmx_npei_pktx_slist_baddr_s cn52xx; 3508 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2011 struct cvmx_npei_pktx_slist_baddr_s cn56xx; 3509 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
@@ -2014,8 +3512,13 @@ union cvmx_npei_pktx_slist_baddr {
2014union cvmx_npei_pktx_slist_baoff_dbell { 3512union cvmx_npei_pktx_slist_baoff_dbell {
2015 uint64_t u64; 3513 uint64_t u64;
2016 struct cvmx_npei_pktx_slist_baoff_dbell_s { 3514 struct cvmx_npei_pktx_slist_baoff_dbell_s {
3515#ifdef __BIG_ENDIAN_BITFIELD
2017 uint64_t aoff:32; 3516 uint64_t aoff:32;
2018 uint64_t dbell:32; 3517 uint64_t dbell:32;
3518#else
3519 uint64_t dbell:32;
3520 uint64_t aoff:32;
3521#endif
2019 } s; 3522 } s;
2020 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; 3523 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2021 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; 3524 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
@@ -2024,8 +3527,13 @@ union cvmx_npei_pktx_slist_baoff_dbell {
2024union cvmx_npei_pktx_slist_fifo_rsize { 3527union cvmx_npei_pktx_slist_fifo_rsize {
2025 uint64_t u64; 3528 uint64_t u64;
2026 struct cvmx_npei_pktx_slist_fifo_rsize_s { 3529 struct cvmx_npei_pktx_slist_fifo_rsize_s {
3530#ifdef __BIG_ENDIAN_BITFIELD
2027 uint64_t reserved_32_63:32; 3531 uint64_t reserved_32_63:32;
2028 uint64_t rsize:32; 3532 uint64_t rsize:32;
3533#else
3534 uint64_t rsize:32;
3535 uint64_t reserved_32_63:32;
3536#endif
2029 } s; 3537 } s;
2030 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; 3538 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2031 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; 3539 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
@@ -2034,8 +3542,13 @@ union cvmx_npei_pktx_slist_fifo_rsize {
2034union cvmx_npei_pkt_cnt_int { 3542union cvmx_npei_pkt_cnt_int {
2035 uint64_t u64; 3543 uint64_t u64;
2036 struct cvmx_npei_pkt_cnt_int_s { 3544 struct cvmx_npei_pkt_cnt_int_s {
3545#ifdef __BIG_ENDIAN_BITFIELD
2037 uint64_t reserved_32_63:32; 3546 uint64_t reserved_32_63:32;
2038 uint64_t port:32; 3547 uint64_t port:32;
3548#else
3549 uint64_t port:32;
3550 uint64_t reserved_32_63:32;
3551#endif
2039 } s; 3552 } s;
2040 struct cvmx_npei_pkt_cnt_int_s cn52xx; 3553 struct cvmx_npei_pkt_cnt_int_s cn52xx;
2041 struct cvmx_npei_pkt_cnt_int_s cn56xx; 3554 struct cvmx_npei_pkt_cnt_int_s cn56xx;
@@ -2044,8 +3557,13 @@ union cvmx_npei_pkt_cnt_int {
2044union cvmx_npei_pkt_cnt_int_enb { 3557union cvmx_npei_pkt_cnt_int_enb {
2045 uint64_t u64; 3558 uint64_t u64;
2046 struct cvmx_npei_pkt_cnt_int_enb_s { 3559 struct cvmx_npei_pkt_cnt_int_enb_s {
3560#ifdef __BIG_ENDIAN_BITFIELD
2047 uint64_t reserved_32_63:32; 3561 uint64_t reserved_32_63:32;
2048 uint64_t port:32; 3562 uint64_t port:32;
3563#else
3564 uint64_t port:32;
3565 uint64_t reserved_32_63:32;
3566#endif
2049 } s; 3567 } s;
2050 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; 3568 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2051 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; 3569 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
@@ -2054,7 +3572,11 @@ union cvmx_npei_pkt_cnt_int_enb {
2054union cvmx_npei_pkt_data_out_es { 3572union cvmx_npei_pkt_data_out_es {
2055 uint64_t u64; 3573 uint64_t u64;
2056 struct cvmx_npei_pkt_data_out_es_s { 3574 struct cvmx_npei_pkt_data_out_es_s {
3575#ifdef __BIG_ENDIAN_BITFIELD
3576 uint64_t es:64;
3577#else
2057 uint64_t es:64; 3578 uint64_t es:64;
3579#endif
2058 } s; 3580 } s;
2059 struct cvmx_npei_pkt_data_out_es_s cn52xx; 3581 struct cvmx_npei_pkt_data_out_es_s cn52xx;
2060 struct cvmx_npei_pkt_data_out_es_s cn56xx; 3582 struct cvmx_npei_pkt_data_out_es_s cn56xx;
@@ -2063,8 +3585,13 @@ union cvmx_npei_pkt_data_out_es {
2063union cvmx_npei_pkt_data_out_ns { 3585union cvmx_npei_pkt_data_out_ns {
2064 uint64_t u64; 3586 uint64_t u64;
2065 struct cvmx_npei_pkt_data_out_ns_s { 3587 struct cvmx_npei_pkt_data_out_ns_s {
3588#ifdef __BIG_ENDIAN_BITFIELD
2066 uint64_t reserved_32_63:32; 3589 uint64_t reserved_32_63:32;
2067 uint64_t nsr:32; 3590 uint64_t nsr:32;
3591#else
3592 uint64_t nsr:32;
3593 uint64_t reserved_32_63:32;
3594#endif
2068 } s; 3595 } s;
2069 struct cvmx_npei_pkt_data_out_ns_s cn52xx; 3596 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2070 struct cvmx_npei_pkt_data_out_ns_s cn56xx; 3597 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
@@ -2073,8 +3600,13 @@ union cvmx_npei_pkt_data_out_ns {
2073union cvmx_npei_pkt_data_out_ror { 3600union cvmx_npei_pkt_data_out_ror {
2074 uint64_t u64; 3601 uint64_t u64;
2075 struct cvmx_npei_pkt_data_out_ror_s { 3602 struct cvmx_npei_pkt_data_out_ror_s {
3603#ifdef __BIG_ENDIAN_BITFIELD
2076 uint64_t reserved_32_63:32; 3604 uint64_t reserved_32_63:32;
2077 uint64_t ror:32; 3605 uint64_t ror:32;
3606#else
3607 uint64_t ror:32;
3608 uint64_t reserved_32_63:32;
3609#endif
2078 } s; 3610 } s;
2079 struct cvmx_npei_pkt_data_out_ror_s cn52xx; 3611 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2080 struct cvmx_npei_pkt_data_out_ror_s cn56xx; 3612 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
@@ -2083,8 +3615,13 @@ union cvmx_npei_pkt_data_out_ror {
2083union cvmx_npei_pkt_dpaddr { 3615union cvmx_npei_pkt_dpaddr {
2084 uint64_t u64; 3616 uint64_t u64;
2085 struct cvmx_npei_pkt_dpaddr_s { 3617 struct cvmx_npei_pkt_dpaddr_s {
3618#ifdef __BIG_ENDIAN_BITFIELD
2086 uint64_t reserved_32_63:32; 3619 uint64_t reserved_32_63:32;
2087 uint64_t dptr:32; 3620 uint64_t dptr:32;
3621#else
3622 uint64_t dptr:32;
3623 uint64_t reserved_32_63:32;
3624#endif
2088 } s; 3625 } s;
2089 struct cvmx_npei_pkt_dpaddr_s cn52xx; 3626 struct cvmx_npei_pkt_dpaddr_s cn52xx;
2090 struct cvmx_npei_pkt_dpaddr_s cn56xx; 3627 struct cvmx_npei_pkt_dpaddr_s cn56xx;
@@ -2093,8 +3630,13 @@ union cvmx_npei_pkt_dpaddr {
2093union cvmx_npei_pkt_in_bp { 3630union cvmx_npei_pkt_in_bp {
2094 uint64_t u64; 3631 uint64_t u64;
2095 struct cvmx_npei_pkt_in_bp_s { 3632 struct cvmx_npei_pkt_in_bp_s {
3633#ifdef __BIG_ENDIAN_BITFIELD
2096 uint64_t reserved_32_63:32; 3634 uint64_t reserved_32_63:32;
2097 uint64_t bp:32; 3635 uint64_t bp:32;
3636#else
3637 uint64_t bp:32;
3638 uint64_t reserved_32_63:32;
3639#endif
2098 } s; 3640 } s;
2099 struct cvmx_npei_pkt_in_bp_s cn52xx; 3641 struct cvmx_npei_pkt_in_bp_s cn52xx;
2100 struct cvmx_npei_pkt_in_bp_s cn56xx; 3642 struct cvmx_npei_pkt_in_bp_s cn56xx;
@@ -2103,8 +3645,13 @@ union cvmx_npei_pkt_in_bp {
2103union cvmx_npei_pkt_in_donex_cnts { 3645union cvmx_npei_pkt_in_donex_cnts {
2104 uint64_t u64; 3646 uint64_t u64;
2105 struct cvmx_npei_pkt_in_donex_cnts_s { 3647 struct cvmx_npei_pkt_in_donex_cnts_s {
3648#ifdef __BIG_ENDIAN_BITFIELD
2106 uint64_t reserved_32_63:32; 3649 uint64_t reserved_32_63:32;
2107 uint64_t cnt:32; 3650 uint64_t cnt:32;
3651#else
3652 uint64_t cnt:32;
3653 uint64_t reserved_32_63:32;
3654#endif
2108 } s; 3655 } s;
2109 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; 3656 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2110 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; 3657 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
@@ -2113,8 +3660,13 @@ union cvmx_npei_pkt_in_donex_cnts {
2113union cvmx_npei_pkt_in_instr_counts { 3660union cvmx_npei_pkt_in_instr_counts {
2114 uint64_t u64; 3661 uint64_t u64;
2115 struct cvmx_npei_pkt_in_instr_counts_s { 3662 struct cvmx_npei_pkt_in_instr_counts_s {
3663#ifdef __BIG_ENDIAN_BITFIELD
2116 uint64_t wr_cnt:32; 3664 uint64_t wr_cnt:32;
2117 uint64_t rd_cnt:32; 3665 uint64_t rd_cnt:32;
3666#else
3667 uint64_t rd_cnt:32;
3668 uint64_t wr_cnt:32;
3669#endif
2118 } s; 3670 } s;
2119 struct cvmx_npei_pkt_in_instr_counts_s cn52xx; 3671 struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
2120 struct cvmx_npei_pkt_in_instr_counts_s cn56xx; 3672 struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
@@ -2123,7 +3675,11 @@ union cvmx_npei_pkt_in_instr_counts {
2123union cvmx_npei_pkt_in_pcie_port { 3675union cvmx_npei_pkt_in_pcie_port {
2124 uint64_t u64; 3676 uint64_t u64;
2125 struct cvmx_npei_pkt_in_pcie_port_s { 3677 struct cvmx_npei_pkt_in_pcie_port_s {
3678#ifdef __BIG_ENDIAN_BITFIELD
3679 uint64_t pp:64;
3680#else
2126 uint64_t pp:64; 3681 uint64_t pp:64;
3682#endif
2127 } s; 3683 } s;
2128 struct cvmx_npei_pkt_in_pcie_port_s cn52xx; 3684 struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
2129 struct cvmx_npei_pkt_in_pcie_port_s cn56xx; 3685 struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
@@ -2132,6 +3688,7 @@ union cvmx_npei_pkt_in_pcie_port {
2132union cvmx_npei_pkt_input_control { 3688union cvmx_npei_pkt_input_control {
2133 uint64_t u64; 3689 uint64_t u64;
2134 struct cvmx_npei_pkt_input_control_s { 3690 struct cvmx_npei_pkt_input_control_s {
3691#ifdef __BIG_ENDIAN_BITFIELD
2135 uint64_t reserved_23_63:41; 3692 uint64_t reserved_23_63:41;
2136 uint64_t pkt_rr:1; 3693 uint64_t pkt_rr:1;
2137 uint64_t pbp_dhi:13; 3694 uint64_t pbp_dhi:13;
@@ -2142,6 +3699,18 @@ union cvmx_npei_pkt_input_control {
2142 uint64_t nsr:1; 3699 uint64_t nsr:1;
2143 uint64_t esr:2; 3700 uint64_t esr:2;
2144 uint64_t ror:1; 3701 uint64_t ror:1;
3702#else
3703 uint64_t ror:1;
3704 uint64_t esr:2;
3705 uint64_t nsr:1;
3706 uint64_t use_csr:1;
3707 uint64_t d_ror:1;
3708 uint64_t d_esr:2;
3709 uint64_t d_nsr:1;
3710 uint64_t pbp_dhi:13;
3711 uint64_t pkt_rr:1;
3712 uint64_t reserved_23_63:41;
3713#endif
2145 } s; 3714 } s;
2146 struct cvmx_npei_pkt_input_control_s cn52xx; 3715 struct cvmx_npei_pkt_input_control_s cn52xx;
2147 struct cvmx_npei_pkt_input_control_s cn56xx; 3716 struct cvmx_npei_pkt_input_control_s cn56xx;
@@ -2150,8 +3719,13 @@ union cvmx_npei_pkt_input_control {
2150union cvmx_npei_pkt_instr_enb { 3719union cvmx_npei_pkt_instr_enb {
2151 uint64_t u64; 3720 uint64_t u64;
2152 struct cvmx_npei_pkt_instr_enb_s { 3721 struct cvmx_npei_pkt_instr_enb_s {
3722#ifdef __BIG_ENDIAN_BITFIELD
2153 uint64_t reserved_32_63:32; 3723 uint64_t reserved_32_63:32;
2154 uint64_t enb:32; 3724 uint64_t enb:32;
3725#else
3726 uint64_t enb:32;
3727 uint64_t reserved_32_63:32;
3728#endif
2155 } s; 3729 } s;
2156 struct cvmx_npei_pkt_instr_enb_s cn52xx; 3730 struct cvmx_npei_pkt_instr_enb_s cn52xx;
2157 struct cvmx_npei_pkt_instr_enb_s cn56xx; 3731 struct cvmx_npei_pkt_instr_enb_s cn56xx;
@@ -2160,7 +3734,11 @@ union cvmx_npei_pkt_instr_enb {
2160union cvmx_npei_pkt_instr_rd_size { 3734union cvmx_npei_pkt_instr_rd_size {
2161 uint64_t u64; 3735 uint64_t u64;
2162 struct cvmx_npei_pkt_instr_rd_size_s { 3736 struct cvmx_npei_pkt_instr_rd_size_s {
3737#ifdef __BIG_ENDIAN_BITFIELD
2163 uint64_t rdsize:64; 3738 uint64_t rdsize:64;
3739#else
3740 uint64_t rdsize:64;
3741#endif
2164 } s; 3742 } s;
2165 struct cvmx_npei_pkt_instr_rd_size_s cn52xx; 3743 struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
2166 struct cvmx_npei_pkt_instr_rd_size_s cn56xx; 3744 struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
@@ -2169,8 +3747,13 @@ union cvmx_npei_pkt_instr_rd_size {
2169union cvmx_npei_pkt_instr_size { 3747union cvmx_npei_pkt_instr_size {
2170 uint64_t u64; 3748 uint64_t u64;
2171 struct cvmx_npei_pkt_instr_size_s { 3749 struct cvmx_npei_pkt_instr_size_s {
3750#ifdef __BIG_ENDIAN_BITFIELD
2172 uint64_t reserved_32_63:32; 3751 uint64_t reserved_32_63:32;
2173 uint64_t is_64b:32; 3752 uint64_t is_64b:32;
3753#else
3754 uint64_t is_64b:32;
3755 uint64_t reserved_32_63:32;
3756#endif
2174 } s; 3757 } s;
2175 struct cvmx_npei_pkt_instr_size_s cn52xx; 3758 struct cvmx_npei_pkt_instr_size_s cn52xx;
2176 struct cvmx_npei_pkt_instr_size_s cn56xx; 3759 struct cvmx_npei_pkt_instr_size_s cn56xx;
@@ -2179,9 +3762,15 @@ union cvmx_npei_pkt_instr_size {
2179union cvmx_npei_pkt_int_levels { 3762union cvmx_npei_pkt_int_levels {
2180 uint64_t u64; 3763 uint64_t u64;
2181 struct cvmx_npei_pkt_int_levels_s { 3764 struct cvmx_npei_pkt_int_levels_s {
3765#ifdef __BIG_ENDIAN_BITFIELD
2182 uint64_t reserved_54_63:10; 3766 uint64_t reserved_54_63:10;
2183 uint64_t time:22; 3767 uint64_t time:22;
2184 uint64_t cnt:32; 3768 uint64_t cnt:32;
3769#else
3770 uint64_t cnt:32;
3771 uint64_t time:22;
3772 uint64_t reserved_54_63:10;
3773#endif
2185 } s; 3774 } s;
2186 struct cvmx_npei_pkt_int_levels_s cn52xx; 3775 struct cvmx_npei_pkt_int_levels_s cn52xx;
2187 struct cvmx_npei_pkt_int_levels_s cn56xx; 3776 struct cvmx_npei_pkt_int_levels_s cn56xx;
@@ -2190,8 +3779,13 @@ union cvmx_npei_pkt_int_levels {
2190union cvmx_npei_pkt_iptr { 3779union cvmx_npei_pkt_iptr {
2191 uint64_t u64; 3780 uint64_t u64;
2192 struct cvmx_npei_pkt_iptr_s { 3781 struct cvmx_npei_pkt_iptr_s {
3782#ifdef __BIG_ENDIAN_BITFIELD
2193 uint64_t reserved_32_63:32; 3783 uint64_t reserved_32_63:32;
2194 uint64_t iptr:32; 3784 uint64_t iptr:32;
3785#else
3786 uint64_t iptr:32;
3787 uint64_t reserved_32_63:32;
3788#endif
2195 } s; 3789 } s;
2196 struct cvmx_npei_pkt_iptr_s cn52xx; 3790 struct cvmx_npei_pkt_iptr_s cn52xx;
2197 struct cvmx_npei_pkt_iptr_s cn56xx; 3791 struct cvmx_npei_pkt_iptr_s cn56xx;
@@ -2200,8 +3794,13 @@ union cvmx_npei_pkt_iptr {
2200union cvmx_npei_pkt_out_bmode { 3794union cvmx_npei_pkt_out_bmode {
2201 uint64_t u64; 3795 uint64_t u64;
2202 struct cvmx_npei_pkt_out_bmode_s { 3796 struct cvmx_npei_pkt_out_bmode_s {
3797#ifdef __BIG_ENDIAN_BITFIELD
2203 uint64_t reserved_32_63:32; 3798 uint64_t reserved_32_63:32;
2204 uint64_t bmode:32; 3799 uint64_t bmode:32;
3800#else
3801 uint64_t bmode:32;
3802 uint64_t reserved_32_63:32;
3803#endif
2205 } s; 3804 } s;
2206 struct cvmx_npei_pkt_out_bmode_s cn52xx; 3805 struct cvmx_npei_pkt_out_bmode_s cn52xx;
2207 struct cvmx_npei_pkt_out_bmode_s cn56xx; 3806 struct cvmx_npei_pkt_out_bmode_s cn56xx;
@@ -2210,8 +3809,13 @@ union cvmx_npei_pkt_out_bmode {
2210union cvmx_npei_pkt_out_enb { 3809union cvmx_npei_pkt_out_enb {
2211 uint64_t u64; 3810 uint64_t u64;
2212 struct cvmx_npei_pkt_out_enb_s { 3811 struct cvmx_npei_pkt_out_enb_s {
3812#ifdef __BIG_ENDIAN_BITFIELD
2213 uint64_t reserved_32_63:32; 3813 uint64_t reserved_32_63:32;
2214 uint64_t enb:32; 3814 uint64_t enb:32;
3815#else
3816 uint64_t enb:32;
3817 uint64_t reserved_32_63:32;
3818#endif
2215 } s; 3819 } s;
2216 struct cvmx_npei_pkt_out_enb_s cn52xx; 3820 struct cvmx_npei_pkt_out_enb_s cn52xx;
2217 struct cvmx_npei_pkt_out_enb_s cn56xx; 3821 struct cvmx_npei_pkt_out_enb_s cn56xx;
@@ -2220,8 +3824,13 @@ union cvmx_npei_pkt_out_enb {
2220union cvmx_npei_pkt_output_wmark { 3824union cvmx_npei_pkt_output_wmark {
2221 uint64_t u64; 3825 uint64_t u64;
2222 struct cvmx_npei_pkt_output_wmark_s { 3826 struct cvmx_npei_pkt_output_wmark_s {
3827#ifdef __BIG_ENDIAN_BITFIELD
2223 uint64_t reserved_32_63:32; 3828 uint64_t reserved_32_63:32;
2224 uint64_t wmark:32; 3829 uint64_t wmark:32;
3830#else
3831 uint64_t wmark:32;
3832 uint64_t reserved_32_63:32;
3833#endif
2225 } s; 3834 } s;
2226 struct cvmx_npei_pkt_output_wmark_s cn52xx; 3835 struct cvmx_npei_pkt_output_wmark_s cn52xx;
2227 struct cvmx_npei_pkt_output_wmark_s cn56xx; 3836 struct cvmx_npei_pkt_output_wmark_s cn56xx;
@@ -2230,7 +3839,11 @@ union cvmx_npei_pkt_output_wmark {
2230union cvmx_npei_pkt_pcie_port { 3839union cvmx_npei_pkt_pcie_port {
2231 uint64_t u64; 3840 uint64_t u64;
2232 struct cvmx_npei_pkt_pcie_port_s { 3841 struct cvmx_npei_pkt_pcie_port_s {
3842#ifdef __BIG_ENDIAN_BITFIELD
2233 uint64_t pp:64; 3843 uint64_t pp:64;
3844#else
3845 uint64_t pp:64;
3846#endif
2234 } s; 3847 } s;
2235 struct cvmx_npei_pkt_pcie_port_s cn52xx; 3848 struct cvmx_npei_pkt_pcie_port_s cn52xx;
2236 struct cvmx_npei_pkt_pcie_port_s cn56xx; 3849 struct cvmx_npei_pkt_pcie_port_s cn56xx;
@@ -2239,8 +3852,13 @@ union cvmx_npei_pkt_pcie_port {
2239union cvmx_npei_pkt_port_in_rst { 3852union cvmx_npei_pkt_port_in_rst {
2240 uint64_t u64; 3853 uint64_t u64;
2241 struct cvmx_npei_pkt_port_in_rst_s { 3854 struct cvmx_npei_pkt_port_in_rst_s {
3855#ifdef __BIG_ENDIAN_BITFIELD
2242 uint64_t in_rst:32; 3856 uint64_t in_rst:32;
2243 uint64_t out_rst:32; 3857 uint64_t out_rst:32;
3858#else
3859 uint64_t out_rst:32;
3860 uint64_t in_rst:32;
3861#endif
2244 } s; 3862 } s;
2245 struct cvmx_npei_pkt_port_in_rst_s cn52xx; 3863 struct cvmx_npei_pkt_port_in_rst_s cn52xx;
2246 struct cvmx_npei_pkt_port_in_rst_s cn56xx; 3864 struct cvmx_npei_pkt_port_in_rst_s cn56xx;
@@ -2249,7 +3867,11 @@ union cvmx_npei_pkt_port_in_rst {
2249union cvmx_npei_pkt_slist_es { 3867union cvmx_npei_pkt_slist_es {
2250 uint64_t u64; 3868 uint64_t u64;
2251 struct cvmx_npei_pkt_slist_es_s { 3869 struct cvmx_npei_pkt_slist_es_s {
3870#ifdef __BIG_ENDIAN_BITFIELD
2252 uint64_t es:64; 3871 uint64_t es:64;
3872#else
3873 uint64_t es:64;
3874#endif
2253 } s; 3875 } s;
2254 struct cvmx_npei_pkt_slist_es_s cn52xx; 3876 struct cvmx_npei_pkt_slist_es_s cn52xx;
2255 struct cvmx_npei_pkt_slist_es_s cn56xx; 3877 struct cvmx_npei_pkt_slist_es_s cn56xx;
@@ -2258,9 +3880,15 @@ union cvmx_npei_pkt_slist_es {
2258union cvmx_npei_pkt_slist_id_size { 3880union cvmx_npei_pkt_slist_id_size {
2259 uint64_t u64; 3881 uint64_t u64;
2260 struct cvmx_npei_pkt_slist_id_size_s { 3882 struct cvmx_npei_pkt_slist_id_size_s {
3883#ifdef __BIG_ENDIAN_BITFIELD
2261 uint64_t reserved_23_63:41; 3884 uint64_t reserved_23_63:41;
2262 uint64_t isize:7; 3885 uint64_t isize:7;
2263 uint64_t bsize:16; 3886 uint64_t bsize:16;
3887#else
3888 uint64_t bsize:16;
3889 uint64_t isize:7;
3890 uint64_t reserved_23_63:41;
3891#endif
2264 } s; 3892 } s;
2265 struct cvmx_npei_pkt_slist_id_size_s cn52xx; 3893 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2266 struct cvmx_npei_pkt_slist_id_size_s cn56xx; 3894 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
@@ -2269,8 +3897,13 @@ union cvmx_npei_pkt_slist_id_size {
2269union cvmx_npei_pkt_slist_ns { 3897union cvmx_npei_pkt_slist_ns {
2270 uint64_t u64; 3898 uint64_t u64;
2271 struct cvmx_npei_pkt_slist_ns_s { 3899 struct cvmx_npei_pkt_slist_ns_s {
3900#ifdef __BIG_ENDIAN_BITFIELD
2272 uint64_t reserved_32_63:32; 3901 uint64_t reserved_32_63:32;
2273 uint64_t nsr:32; 3902 uint64_t nsr:32;
3903#else
3904 uint64_t nsr:32;
3905 uint64_t reserved_32_63:32;
3906#endif
2274 } s; 3907 } s;
2275 struct cvmx_npei_pkt_slist_ns_s cn52xx; 3908 struct cvmx_npei_pkt_slist_ns_s cn52xx;
2276 struct cvmx_npei_pkt_slist_ns_s cn56xx; 3909 struct cvmx_npei_pkt_slist_ns_s cn56xx;
@@ -2279,8 +3912,13 @@ union cvmx_npei_pkt_slist_ns {
2279union cvmx_npei_pkt_slist_ror { 3912union cvmx_npei_pkt_slist_ror {
2280 uint64_t u64; 3913 uint64_t u64;
2281 struct cvmx_npei_pkt_slist_ror_s { 3914 struct cvmx_npei_pkt_slist_ror_s {
3915#ifdef __BIG_ENDIAN_BITFIELD
2282 uint64_t reserved_32_63:32; 3916 uint64_t reserved_32_63:32;
2283 uint64_t ror:32; 3917 uint64_t ror:32;
3918#else
3919 uint64_t ror:32;
3920 uint64_t reserved_32_63:32;
3921#endif
2284 } s; 3922 } s;
2285 struct cvmx_npei_pkt_slist_ror_s cn52xx; 3923 struct cvmx_npei_pkt_slist_ror_s cn52xx;
2286 struct cvmx_npei_pkt_slist_ror_s cn56xx; 3924 struct cvmx_npei_pkt_slist_ror_s cn56xx;
@@ -2289,8 +3927,13 @@ union cvmx_npei_pkt_slist_ror {
2289union cvmx_npei_pkt_time_int { 3927union cvmx_npei_pkt_time_int {
2290 uint64_t u64; 3928 uint64_t u64;
2291 struct cvmx_npei_pkt_time_int_s { 3929 struct cvmx_npei_pkt_time_int_s {
3930#ifdef __BIG_ENDIAN_BITFIELD
2292 uint64_t reserved_32_63:32; 3931 uint64_t reserved_32_63:32;
2293 uint64_t port:32; 3932 uint64_t port:32;
3933#else
3934 uint64_t port:32;
3935 uint64_t reserved_32_63:32;
3936#endif
2294 } s; 3937 } s;
2295 struct cvmx_npei_pkt_time_int_s cn52xx; 3938 struct cvmx_npei_pkt_time_int_s cn52xx;
2296 struct cvmx_npei_pkt_time_int_s cn56xx; 3939 struct cvmx_npei_pkt_time_int_s cn56xx;
@@ -2299,8 +3942,13 @@ union cvmx_npei_pkt_time_int {
2299union cvmx_npei_pkt_time_int_enb { 3942union cvmx_npei_pkt_time_int_enb {
2300 uint64_t u64; 3943 uint64_t u64;
2301 struct cvmx_npei_pkt_time_int_enb_s { 3944 struct cvmx_npei_pkt_time_int_enb_s {
3945#ifdef __BIG_ENDIAN_BITFIELD
2302 uint64_t reserved_32_63:32; 3946 uint64_t reserved_32_63:32;
2303 uint64_t port:32; 3947 uint64_t port:32;
3948#else
3949 uint64_t port:32;
3950 uint64_t reserved_32_63:32;
3951#endif
2304 } s; 3952 } s;
2305 struct cvmx_npei_pkt_time_int_enb_s cn52xx; 3953 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2306 struct cvmx_npei_pkt_time_int_enb_s cn56xx; 3954 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
@@ -2309,6 +3957,7 @@ union cvmx_npei_pkt_time_int_enb {
2309union cvmx_npei_rsl_int_blocks { 3957union cvmx_npei_rsl_int_blocks {
2310 uint64_t u64; 3958 uint64_t u64;
2311 struct cvmx_npei_rsl_int_blocks_s { 3959 struct cvmx_npei_rsl_int_blocks_s {
3960#ifdef __BIG_ENDIAN_BITFIELD
2312 uint64_t reserved_31_63:33; 3961 uint64_t reserved_31_63:33;
2313 uint64_t iob:1; 3962 uint64_t iob:1;
2314 uint64_t lmc1:1; 3963 uint64_t lmc1:1;
@@ -2338,6 +3987,37 @@ union cvmx_npei_rsl_int_blocks {
2338 uint64_t gmx1:1; 3987 uint64_t gmx1:1;
2339 uint64_t gmx0:1; 3988 uint64_t gmx0:1;
2340 uint64_t mio:1; 3989 uint64_t mio:1;
3990#else
3991 uint64_t mio:1;
3992 uint64_t gmx0:1;
3993 uint64_t gmx1:1;
3994 uint64_t npei:1;
3995 uint64_t key:1;
3996 uint64_t fpa:1;
3997 uint64_t dfa:1;
3998 uint64_t zip:1;
3999 uint64_t reserved_8_8:1;
4000 uint64_t ipd:1;
4001 uint64_t pko:1;
4002 uint64_t tim:1;
4003 uint64_t pow:1;
4004 uint64_t usb:1;
4005 uint64_t rad:1;
4006 uint64_t usb1:1;
4007 uint64_t l2c:1;
4008 uint64_t lmc0:1;
4009 uint64_t spx0:1;
4010 uint64_t spx1:1;
4011 uint64_t pip:1;
4012 uint64_t reserved_21_21:1;
4013 uint64_t asxpcs0:1;
4014 uint64_t asxpcs1:1;
4015 uint64_t reserved_24_27:4;
4016 uint64_t agl:1;
4017 uint64_t lmc1:1;
4018 uint64_t iob:1;
4019 uint64_t reserved_31_63:33;
4020#endif
2341 } s; 4021 } s;
2342 struct cvmx_npei_rsl_int_blocks_s cn52xx; 4022 struct cvmx_npei_rsl_int_blocks_s cn52xx;
2343 struct cvmx_npei_rsl_int_blocks_s cn52xxp1; 4023 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
@@ -2348,7 +4028,11 @@ union cvmx_npei_rsl_int_blocks {
2348union cvmx_npei_scratch_1 { 4028union cvmx_npei_scratch_1 {
2349 uint64_t u64; 4029 uint64_t u64;
2350 struct cvmx_npei_scratch_1_s { 4030 struct cvmx_npei_scratch_1_s {
4031#ifdef __BIG_ENDIAN_BITFIELD
4032 uint64_t data:64;
4033#else
2351 uint64_t data:64; 4034 uint64_t data:64;
4035#endif
2352 } s; 4036 } s;
2353 struct cvmx_npei_scratch_1_s cn52xx; 4037 struct cvmx_npei_scratch_1_s cn52xx;
2354 struct cvmx_npei_scratch_1_s cn52xxp1; 4038 struct cvmx_npei_scratch_1_s cn52xxp1;
@@ -2359,10 +4043,17 @@ union cvmx_npei_scratch_1 {
2359union cvmx_npei_state1 { 4043union cvmx_npei_state1 {
2360 uint64_t u64; 4044 uint64_t u64;
2361 struct cvmx_npei_state1_s { 4045 struct cvmx_npei_state1_s {
4046#ifdef __BIG_ENDIAN_BITFIELD
2362 uint64_t cpl1:12; 4047 uint64_t cpl1:12;
2363 uint64_t cpl0:12; 4048 uint64_t cpl0:12;
2364 uint64_t arb:1; 4049 uint64_t arb:1;
2365 uint64_t csr:39; 4050 uint64_t csr:39;
4051#else
4052 uint64_t csr:39;
4053 uint64_t arb:1;
4054 uint64_t cpl0:12;
4055 uint64_t cpl1:12;
4056#endif
2366 } s; 4057 } s;
2367 struct cvmx_npei_state1_s cn52xx; 4058 struct cvmx_npei_state1_s cn52xx;
2368 struct cvmx_npei_state1_s cn52xxp1; 4059 struct cvmx_npei_state1_s cn52xxp1;
@@ -2373,6 +4064,7 @@ union cvmx_npei_state1 {
2373union cvmx_npei_state2 { 4064union cvmx_npei_state2 {
2374 uint64_t u64; 4065 uint64_t u64;
2375 struct cvmx_npei_state2_s { 4066 struct cvmx_npei_state2_s {
4067#ifdef __BIG_ENDIAN_BITFIELD
2376 uint64_t reserved_48_63:16; 4068 uint64_t reserved_48_63:16;
2377 uint64_t npei:1; 4069 uint64_t npei:1;
2378 uint64_t rac:1; 4070 uint64_t rac:1;
@@ -2380,6 +4072,15 @@ union cvmx_npei_state2 {
2380 uint64_t csm0:15; 4072 uint64_t csm0:15;
2381 uint64_t nnp0:8; 4073 uint64_t nnp0:8;
2382 uint64_t nnd:8; 4074 uint64_t nnd:8;
4075#else
4076 uint64_t nnd:8;
4077 uint64_t nnp0:8;
4078 uint64_t csm0:15;
4079 uint64_t csm1:15;
4080 uint64_t rac:1;
4081 uint64_t npei:1;
4082 uint64_t reserved_48_63:16;
4083#endif
2383 } s; 4084 } s;
2384 struct cvmx_npei_state2_s cn52xx; 4085 struct cvmx_npei_state2_s cn52xx;
2385 struct cvmx_npei_state2_s cn52xxp1; 4086 struct cvmx_npei_state2_s cn52xxp1;
@@ -2390,11 +4091,19 @@ union cvmx_npei_state2 {
2390union cvmx_npei_state3 { 4091union cvmx_npei_state3 {
2391 uint64_t u64; 4092 uint64_t u64;
2392 struct cvmx_npei_state3_s { 4093 struct cvmx_npei_state3_s {
4094#ifdef __BIG_ENDIAN_BITFIELD
2393 uint64_t reserved_56_63:8; 4095 uint64_t reserved_56_63:8;
2394 uint64_t psm1:15; 4096 uint64_t psm1:15;
2395 uint64_t psm0:15; 4097 uint64_t psm0:15;
2396 uint64_t nsm1:13; 4098 uint64_t nsm1:13;
2397 uint64_t nsm0:13; 4099 uint64_t nsm0:13;
4100#else
4101 uint64_t nsm0:13;
4102 uint64_t nsm1:13;
4103 uint64_t psm0:15;
4104 uint64_t psm1:15;
4105 uint64_t reserved_56_63:8;
4106#endif
2398 } s; 4107 } s;
2399 struct cvmx_npei_state3_s cn52xx; 4108 struct cvmx_npei_state3_s cn52xx;
2400 struct cvmx_npei_state3_s cn52xxp1; 4109 struct cvmx_npei_state3_s cn52xxp1;
@@ -2405,10 +4114,17 @@ union cvmx_npei_state3 {
2405union cvmx_npei_win_rd_addr { 4114union cvmx_npei_win_rd_addr {
2406 uint64_t u64; 4115 uint64_t u64;
2407 struct cvmx_npei_win_rd_addr_s { 4116 struct cvmx_npei_win_rd_addr_s {
4117#ifdef __BIG_ENDIAN_BITFIELD
2408 uint64_t reserved_51_63:13; 4118 uint64_t reserved_51_63:13;
2409 uint64_t ld_cmd:2; 4119 uint64_t ld_cmd:2;
2410 uint64_t iobit:1; 4120 uint64_t iobit:1;
2411 uint64_t rd_addr:48; 4121 uint64_t rd_addr:48;
4122#else
4123 uint64_t rd_addr:48;
4124 uint64_t iobit:1;
4125 uint64_t ld_cmd:2;
4126 uint64_t reserved_51_63:13;
4127#endif
2412 } s; 4128 } s;
2413 struct cvmx_npei_win_rd_addr_s cn52xx; 4129 struct cvmx_npei_win_rd_addr_s cn52xx;
2414 struct cvmx_npei_win_rd_addr_s cn52xxp1; 4130 struct cvmx_npei_win_rd_addr_s cn52xxp1;
@@ -2419,7 +4135,11 @@ union cvmx_npei_win_rd_addr {
2419union cvmx_npei_win_rd_data { 4135union cvmx_npei_win_rd_data {
2420 uint64_t u64; 4136 uint64_t u64;
2421 struct cvmx_npei_win_rd_data_s { 4137 struct cvmx_npei_win_rd_data_s {
4138#ifdef __BIG_ENDIAN_BITFIELD
4139 uint64_t rd_data:64;
4140#else
2422 uint64_t rd_data:64; 4141 uint64_t rd_data:64;
4142#endif
2423 } s; 4143 } s;
2424 struct cvmx_npei_win_rd_data_s cn52xx; 4144 struct cvmx_npei_win_rd_data_s cn52xx;
2425 struct cvmx_npei_win_rd_data_s cn52xxp1; 4145 struct cvmx_npei_win_rd_data_s cn52xxp1;
@@ -2430,10 +4150,17 @@ union cvmx_npei_win_rd_data {
2430union cvmx_npei_win_wr_addr { 4150union cvmx_npei_win_wr_addr {
2431 uint64_t u64; 4151 uint64_t u64;
2432 struct cvmx_npei_win_wr_addr_s { 4152 struct cvmx_npei_win_wr_addr_s {
4153#ifdef __BIG_ENDIAN_BITFIELD
2433 uint64_t reserved_49_63:15; 4154 uint64_t reserved_49_63:15;
2434 uint64_t iobit:1; 4155 uint64_t iobit:1;
2435 uint64_t wr_addr:46; 4156 uint64_t wr_addr:46;
2436 uint64_t reserved_0_1:2; 4157 uint64_t reserved_0_1:2;
4158#else
4159 uint64_t reserved_0_1:2;
4160 uint64_t wr_addr:46;
4161 uint64_t iobit:1;
4162 uint64_t reserved_49_63:15;
4163#endif
2437 } s; 4164 } s;
2438 struct cvmx_npei_win_wr_addr_s cn52xx; 4165 struct cvmx_npei_win_wr_addr_s cn52xx;
2439 struct cvmx_npei_win_wr_addr_s cn52xxp1; 4166 struct cvmx_npei_win_wr_addr_s cn52xxp1;
@@ -2444,7 +4171,11 @@ union cvmx_npei_win_wr_addr {
2444union cvmx_npei_win_wr_data { 4171union cvmx_npei_win_wr_data {
2445 uint64_t u64; 4172 uint64_t u64;
2446 struct cvmx_npei_win_wr_data_s { 4173 struct cvmx_npei_win_wr_data_s {
4174#ifdef __BIG_ENDIAN_BITFIELD
2447 uint64_t wr_data:64; 4175 uint64_t wr_data:64;
4176#else
4177 uint64_t wr_data:64;
4178#endif
2448 } s; 4179 } s;
2449 struct cvmx_npei_win_wr_data_s cn52xx; 4180 struct cvmx_npei_win_wr_data_s cn52xx;
2450 struct cvmx_npei_win_wr_data_s cn52xxp1; 4181 struct cvmx_npei_win_wr_data_s cn52xxp1;
@@ -2455,8 +4186,13 @@ union cvmx_npei_win_wr_data {
2455union cvmx_npei_win_wr_mask { 4186union cvmx_npei_win_wr_mask {
2456 uint64_t u64; 4187 uint64_t u64;
2457 struct cvmx_npei_win_wr_mask_s { 4188 struct cvmx_npei_win_wr_mask_s {
4189#ifdef __BIG_ENDIAN_BITFIELD
2458 uint64_t reserved_8_63:56; 4190 uint64_t reserved_8_63:56;
2459 uint64_t wr_mask:8; 4191 uint64_t wr_mask:8;
4192#else
4193 uint64_t wr_mask:8;
4194 uint64_t reserved_8_63:56;
4195#endif
2460 } s; 4196 } s;
2461 struct cvmx_npei_win_wr_mask_s cn52xx; 4197 struct cvmx_npei_win_wr_mask_s cn52xx;
2462 struct cvmx_npei_win_wr_mask_s cn52xxp1; 4198 struct cvmx_npei_win_wr_mask_s cn52xxp1;
@@ -2467,8 +4203,13 @@ union cvmx_npei_win_wr_mask {
2467union cvmx_npei_window_ctl { 4203union cvmx_npei_window_ctl {
2468 uint64_t u64; 4204 uint64_t u64;
2469 struct cvmx_npei_window_ctl_s { 4205 struct cvmx_npei_window_ctl_s {
4206#ifdef __BIG_ENDIAN_BITFIELD
2470 uint64_t reserved_32_63:32; 4207 uint64_t reserved_32_63:32;
2471 uint64_t time:32; 4208 uint64_t time:32;
4209#else
4210 uint64_t time:32;
4211 uint64_t reserved_32_63:32;
4212#endif
2472 } s; 4213 } s;
2473 struct cvmx_npei_window_ctl_s cn52xx; 4214 struct cvmx_npei_window_ctl_s cn52xx;
2474 struct cvmx_npei_window_ctl_s cn52xxp1; 4215 struct cvmx_npei_window_ctl_s cn52xxp1;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 17:34:02 -0400