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Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-asm.h')
-rw-r--r--arch/mips/include/asm/octeon/cvmx-asm.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
index b21d3fc1ef91..5de5de95311b 100644
--- a/arch/mips/include/asm/octeon/cvmx-asm.h
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -114,6 +114,17 @@
114#define CVMX_DCACHE_INVALIDATE \ 114#define CVMX_DCACHE_INVALIDATE \
115 { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } 115 { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
116 116
117#define CVMX_CACHE(op, address, offset) \
118 asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
119 : : [rbase] "d" (address) )
120/* fetch and lock the state. */
121#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset)
122/* unlock the state. */
123#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset)
124/* invalidate the cache block and clear the USED bits for the block */
125#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset)
126/* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
127#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset)
117 128
118#define CVMX_POP(result, input) \ 129#define CVMX_POP(result, input) \
119 asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) 130 asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))