diff options
Diffstat (limited to 'arch/mips/include/asm/mach-pb1x00/pb1200.h')
-rw-r--r-- | arch/mips/include/asm/mach-pb1x00/pb1200.h | 122 |
1 files changed, 2 insertions, 120 deletions
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index c8618df88cb5..962eb55dc880 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h | |||
@@ -25,6 +25,7 @@ | |||
25 | #define __ASM_PB1200_H | 25 | #define __ASM_PB1200_H |
26 | 26 | ||
27 | #include <linux/types.h> | 27 | #include <linux/types.h> |
28 | #include <asm/mach-au1x00/au1000.h> | ||
28 | #include <asm/mach-au1x00/au1xxx_psc.h> | 29 | #include <asm/mach-au1x00/au1xxx_psc.h> |
29 | 30 | ||
30 | #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX | 31 | #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX |
@@ -43,113 +44,8 @@ | |||
43 | * Refer to board documentation. | 44 | * Refer to board documentation. |
44 | */ | 45 | */ |
45 | #define AC97_PSC_BASE PSC1_BASE_ADDR | 46 | #define AC97_PSC_BASE PSC1_BASE_ADDR |
46 | #define I2S_PSC_BASE PSC1_BASE_ADDR | 47 | #define I2S_PSC_BASE PSC1_BASE_ADDR |
47 | 48 | ||
48 | #define BCSR_KSEG1_ADDR 0xAD800000 | ||
49 | |||
50 | typedef volatile struct | ||
51 | { | ||
52 | /*00*/ u16 whoami; | ||
53 | u16 reserved0; | ||
54 | /*04*/ u16 status; | ||
55 | u16 reserved1; | ||
56 | /*08*/ u16 switches; | ||
57 | u16 reserved2; | ||
58 | /*0C*/ u16 resets; | ||
59 | u16 reserved3; | ||
60 | |||
61 | /*10*/ u16 pcmcia; | ||
62 | u16 reserved4; | ||
63 | /*14*/ u16 board; | ||
64 | u16 reserved5; | ||
65 | /*18*/ u16 disk_leds; | ||
66 | u16 reserved6; | ||
67 | /*1C*/ u16 system; | ||
68 | u16 reserved7; | ||
69 | |||
70 | /*20*/ u16 intclr; | ||
71 | u16 reserved8; | ||
72 | /*24*/ u16 intset; | ||
73 | u16 reserved9; | ||
74 | /*28*/ u16 intclr_mask; | ||
75 | u16 reserved10; | ||
76 | /*2C*/ u16 intset_mask; | ||
77 | u16 reserved11; | ||
78 | |||
79 | /*30*/ u16 sig_status; | ||
80 | u16 reserved12; | ||
81 | /*34*/ u16 int_status; | ||
82 | u16 reserved13; | ||
83 | /*38*/ u16 reserved14; | ||
84 | u16 reserved15; | ||
85 | /*3C*/ u16 reserved16; | ||
86 | u16 reserved17; | ||
87 | |||
88 | } BCSR; | ||
89 | |||
90 | static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; | ||
91 | |||
92 | /* | ||
93 | * Register bit definitions for the BCSRs | ||
94 | */ | ||
95 | #define BCSR_WHOAMI_DCID 0x000F | ||
96 | #define BCSR_WHOAMI_CPLD 0x00F0 | ||
97 | #define BCSR_WHOAMI_BOARD 0x0F00 | ||
98 | |||
99 | #define BCSR_STATUS_PCMCIA0VS 0x0003 | ||
100 | #define BCSR_STATUS_PCMCIA1VS 0x000C | ||
101 | #define BCSR_STATUS_SWAPBOOT 0x0040 | ||
102 | #define BCSR_STATUS_FLASHBUSY 0x0100 | ||
103 | #define BCSR_STATUS_IDECBLID 0x0200 | ||
104 | #define BCSR_STATUS_SD0WP 0x0400 | ||
105 | #define BCSR_STATUS_SD1WP 0x0800 | ||
106 | #define BCSR_STATUS_U0RXD 0x1000 | ||
107 | #define BCSR_STATUS_U1RXD 0x2000 | ||
108 | |||
109 | #define BCSR_SWITCHES_OCTAL 0x00FF | ||
110 | #define BCSR_SWITCHES_DIP_1 0x0080 | ||
111 | #define BCSR_SWITCHES_DIP_2 0x0040 | ||
112 | #define BCSR_SWITCHES_DIP_3 0x0020 | ||
113 | #define BCSR_SWITCHES_DIP_4 0x0010 | ||
114 | #define BCSR_SWITCHES_DIP_5 0x0008 | ||
115 | #define BCSR_SWITCHES_DIP_6 0x0004 | ||
116 | #define BCSR_SWITCHES_DIP_7 0x0002 | ||
117 | #define BCSR_SWITCHES_DIP_8 0x0001 | ||
118 | #define BCSR_SWITCHES_ROTARY 0x0F00 | ||
119 | |||
120 | #define BCSR_RESETS_ETH 0x0001 | ||
121 | #define BCSR_RESETS_CAMERA 0x0002 | ||
122 | #define BCSR_RESETS_DC 0x0004 | ||
123 | #define BCSR_RESETS_IDE 0x0008 | ||
124 | /* not resets but in the same register */ | ||
125 | #define BCSR_RESETS_WSCFSM 0x0800 | ||
126 | #define BCSR_RESETS_PCS0MUX 0x1000 | ||
127 | #define BCSR_RESETS_PCS1MUX 0x2000 | ||
128 | #define BCSR_RESETS_SPISEL 0x4000 | ||
129 | #define BCSR_RESETS_SD1MUX 0x8000 | ||
130 | |||
131 | #define BCSR_PCMCIA_PC0VPP 0x0003 | ||
132 | #define BCSR_PCMCIA_PC0VCC 0x000C | ||
133 | #define BCSR_PCMCIA_PC0DRVEN 0x0010 | ||
134 | #define BCSR_PCMCIA_PC0RST 0x0080 | ||
135 | #define BCSR_PCMCIA_PC1VPP 0x0300 | ||
136 | #define BCSR_PCMCIA_PC1VCC 0x0C00 | ||
137 | #define BCSR_PCMCIA_PC1DRVEN 0x1000 | ||
138 | #define BCSR_PCMCIA_PC1RST 0x8000 | ||
139 | |||
140 | #define BCSR_BOARD_LCDVEE 0x0001 | ||
141 | #define BCSR_BOARD_LCDVDD 0x0002 | ||
142 | #define BCSR_BOARD_LCDBL 0x0004 | ||
143 | #define BCSR_BOARD_CAMSNAP 0x0010 | ||
144 | #define BCSR_BOARD_CAMPWR 0x0020 | ||
145 | #define BCSR_BOARD_SD0PWR 0x0040 | ||
146 | #define BCSR_BOARD_SD1PWR 0x0080 | ||
147 | |||
148 | #define BCSR_LEDS_DECIMALS 0x00FF | ||
149 | #define BCSR_LEDS_LED0 0x0100 | ||
150 | #define BCSR_LEDS_LED1 0x0200 | ||
151 | #define BCSR_LEDS_LED2 0x0400 | ||
152 | #define BCSR_LEDS_LED3 0x0800 | ||
153 | 49 | ||
154 | #define BCSR_SYSTEM_VDDI 0x001F | 50 | #define BCSR_SYSTEM_VDDI 0x001F |
155 | #define BCSR_SYSTEM_POWEROFF 0x4000 | 51 | #define BCSR_SYSTEM_POWEROFF 0x4000 |
@@ -239,20 +135,6 @@ enum external_pb1200_ints { | |||
239 | PB1200_INT_END = PB1200_INT_BEGIN + 15 | 135 | PB1200_INT_END = PB1200_INT_BEGIN + 15 |
240 | }; | 136 | }; |
241 | 137 | ||
242 | /* | ||
243 | * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c | ||
244 | */ | ||
245 | #define PCMCIA_MAX_SOCK 1 | ||
246 | #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) | ||
247 | |||
248 | /* VPP/VCC */ | ||
249 | #define SET_VCC_VPP(VCC, VPP, SLOT) \ | ||
250 | ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) | ||
251 | |||
252 | #define BOARD_PC0_INT PB1200_PC0_INT | ||
253 | #define BOARD_PC1_INT PB1200_PC1_INT | ||
254 | #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) | ||
255 | |||
256 | /* NAND chip select */ | 138 | /* NAND chip select */ |
257 | #define NAND_CS 1 | 139 | #define NAND_CS 1 |
258 | 140 | ||