1 files changed, 35 insertions, 8 deletions

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0a2121abb1a6..eff7ca7d12b0 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -727,6 +727,8 @@
 /*************************************************************************
  * _REG relative to RSET_ENETDMA
  *************************************************************************/
+#define ENETDMA_CHAN_WIDTH              0x10
+#define ENETDMA_6345_CHAN_WIDTH         0x40
 
 /* Controller Configuration Register */
 #define ENETDMA_CFG_REG                 (0x0)
@@ -782,31 +784,56 @@
 /* State Ram Word 4 */
 #define ENETDMA_SRAM4_REG(x)            (0x20c + (x) * 0x10)
 
+/* Broadcom 6345 ENET DMA definitions */
+#define ENETDMA_6345_CHANCFG_REG        (0x00)
+
+#define ENETDMA_6345_MAXBURST_REG       (0x40)
+
+#define ENETDMA_6345_RSTART_REG         (0x08)
+
+#define ENETDMA_6345_LEN_REG            (0x0C)
+
+#define ENETDMA_6345_IR_REG             (0x14)
+
+#define ENETDMA_6345_IRMASK_REG         (0x18)
+
+#define ENETDMA_6345_FC_REG             (0x1C)
+
+#define ENETDMA_6345_BUFALLOC_REG       (0x20)
+
+/* Shift down for EOP, SOP and WRAP bits */
+#define ENETDMA_6345_DESC_SHIFT         (3)
 
 /*************************************************************************
  * _REG relative to RSET_ENETDMAC
  *************************************************************************/
 
 /* Channel Configuration register */
-#define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
+#define ENETDMAC_CHANCFG_REG            (0x0)
 #define ENETDMAC_CHANCFG_EN_SHIFT       0
 #define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
 #define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
 #define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
+#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
+#define ENETDMAC_CHANCFG_CHAINING_MASK  (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
+#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT  3
+#define ENETDMAC_CHANCFG_WRAP_EN_MASK   (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
+#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
+#define ENETDMAC_CHANCFG_FLOWC_EN_MASK  (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
 
 /* Interrupt Control/Status register */
-#define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
+#define ENETDMAC_IR_REG                 (0x4)
 #define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
 #define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
 #define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
 
 /* Interrupt Mask register */
-#define ENETDMAC_IRMASK_REG(x)          (0x8 + (x) * 0x10)
+#define ENETDMAC_IRMASK_REG             (0x8)
 
 /* Maximum Burst Length */
-#define ENETDMAC_MAXBURST_REG(x)        (0xc + (x) * 0x10)
+#define ENETDMAC_MAXBURST_REG           (0xc)
 
 
 /*************************************************************************
@@ -814,16 +841,16 @@
  *************************************************************************/
 
 /* Ring Start Address register */
-#define ENETDMAS_RSTART_REG(x)          ((x) * 0x10)
+#define ENETDMAS_RSTART_REG             (0x0)
 
 /* State Ram Word 2 */
-#define ENETDMAS_SRAM2_REG(x)           (0x4 + (x) * 0x10)
+#define ENETDMAS_SRAM2_REG              (0x4)
 
 /* State Ram Word 3 */
-#define ENETDMAS_SRAM3_REG(x)           (0x8 + (x) * 0x10)
+#define ENETDMAS_SRAM3_REG              (0x8)
 
 /* State Ram Word 4 */
-#define ENETDMAS_SRAM4_REG(x)           (0xc + (x) * 0x10)
+#define ENETDMAS_SRAM4_REG              (0xc)
 
 
 /*************************************************************************