diff options
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/gpio-au1000.h')
-rw-r--r-- | arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 56 |
1 files changed, 26 insertions, 30 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 796afd051c35..9785e4ebb450 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h | |||
@@ -25,20 +25,20 @@ | |||
25 | #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) | 25 | #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) |
26 | 26 | ||
27 | /* GPIO1 registers within SYS_ area */ | 27 | /* GPIO1 registers within SYS_ area */ |
28 | #define SYS_TRIOUTRD 0x100 | 28 | #define AU1000_SYS_TRIOUTRD 0x100 |
29 | #define SYS_TRIOUTCLR 0x100 | 29 | #define AU1000_SYS_TRIOUTCLR 0x100 |
30 | #define SYS_OUTPUTRD 0x108 | 30 | #define AU1000_SYS_OUTPUTRD 0x108 |
31 | #define SYS_OUTPUTSET 0x108 | 31 | #define AU1000_SYS_OUTPUTSET 0x108 |
32 | #define SYS_OUTPUTCLR 0x10C | 32 | #define AU1000_SYS_OUTPUTCLR 0x10C |
33 | #define SYS_PINSTATERD 0x110 | 33 | #define AU1000_SYS_PINSTATERD 0x110 |
34 | #define SYS_PININPUTEN 0x110 | 34 | #define AU1000_SYS_PININPUTEN 0x110 |
35 | 35 | ||
36 | /* register offsets within GPIO2 block */ | 36 | /* register offsets within GPIO2 block */ |
37 | #define GPIO2_DIR 0x00 | 37 | #define AU1000_GPIO2_DIR 0x00 |
38 | #define GPIO2_OUTPUT 0x08 | 38 | #define AU1000_GPIO2_OUTPUT 0x08 |
39 | #define GPIO2_PINSTATE 0x0C | 39 | #define AU1000_GPIO2_PINSTATE 0x0C |
40 | #define GPIO2_INTENABLE 0x10 | 40 | #define AU1000_GPIO2_INTENABLE 0x10 |
41 | #define GPIO2_ENABLE 0x14 | 41 | #define AU1000_GPIO2_ENABLE 0x14 |
42 | 42 | ||
43 | struct gpio; | 43 | struct gpio; |
44 | 44 | ||
@@ -217,26 +217,21 @@ static inline int au1200_irq_to_gpio(int irq) | |||
217 | */ | 217 | */ |
218 | static inline void alchemy_gpio1_set_value(int gpio, int v) | 218 | static inline void alchemy_gpio1_set_value(int gpio, int v) |
219 | { | 219 | { |
220 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); | ||
221 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); | 220 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); |
222 | unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; | 221 | unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR; |
223 | __raw_writel(mask, base + r); | 222 | alchemy_wrsys(mask, r); |
224 | wmb(); | ||
225 | } | 223 | } |
226 | 224 | ||
227 | static inline int alchemy_gpio1_get_value(int gpio) | 225 | static inline int alchemy_gpio1_get_value(int gpio) |
228 | { | 226 | { |
229 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); | ||
230 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); | 227 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); |
231 | return __raw_readl(base + SYS_PINSTATERD) & mask; | 228 | return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask; |
232 | } | 229 | } |
233 | 230 | ||
234 | static inline int alchemy_gpio1_direction_input(int gpio) | 231 | static inline int alchemy_gpio1_direction_input(int gpio) |
235 | { | 232 | { |
236 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); | ||
237 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); | 233 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); |
238 | __raw_writel(mask, base + SYS_TRIOUTCLR); | 234 | alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR); |
239 | wmb(); | ||
240 | return 0; | 235 | return 0; |
241 | } | 236 | } |
242 | 237 | ||
@@ -279,13 +274,13 @@ static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) | |||
279 | { | 274 | { |
280 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); | 275 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
281 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); | 276 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); |
282 | unsigned long d = __raw_readl(base + GPIO2_DIR); | 277 | unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR); |
283 | 278 | ||
284 | if (to_out) | 279 | if (to_out) |
285 | d |= mask; | 280 | d |= mask; |
286 | else | 281 | else |
287 | d &= ~mask; | 282 | d &= ~mask; |
288 | __raw_writel(d, base + GPIO2_DIR); | 283 | __raw_writel(d, base + AU1000_GPIO2_DIR); |
289 | wmb(); | 284 | wmb(); |
290 | } | 285 | } |
291 | 286 | ||
@@ -294,14 +289,15 @@ static inline void alchemy_gpio2_set_value(int gpio, int v) | |||
294 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); | 289 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
295 | unsigned long mask; | 290 | unsigned long mask; |
296 | mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); | 291 | mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); |
297 | __raw_writel(mask, base + GPIO2_OUTPUT); | 292 | __raw_writel(mask, base + AU1000_GPIO2_OUTPUT); |
298 | wmb(); | 293 | wmb(); |
299 | } | 294 | } |
300 | 295 | ||
301 | static inline int alchemy_gpio2_get_value(int gpio) | 296 | static inline int alchemy_gpio2_get_value(int gpio) |
302 | { | 297 | { |
303 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); | 298 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
304 | return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); | 299 | return __raw_readl(base + AU1000_GPIO2_PINSTATE) & |
300 | (1 << (gpio - ALCHEMY_GPIO2_BASE)); | ||
305 | } | 301 | } |
306 | 302 | ||
307 | static inline int alchemy_gpio2_direction_input(int gpio) | 303 | static inline int alchemy_gpio2_direction_input(int gpio) |
@@ -352,12 +348,12 @@ static inline int alchemy_gpio2_to_irq(int gpio) | |||
352 | static inline void __alchemy_gpio2_mod_int(int gpio2, int en) | 348 | static inline void __alchemy_gpio2_mod_int(int gpio2, int en) |
353 | { | 349 | { |
354 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); | 350 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
355 | unsigned long r = __raw_readl(base + GPIO2_INTENABLE); | 351 | unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE); |
356 | if (en) | 352 | if (en) |
357 | r |= 1 << gpio2; | 353 | r |= 1 << gpio2; |
358 | else | 354 | else |
359 | r &= ~(1 << gpio2); | 355 | r &= ~(1 << gpio2); |
360 | __raw_writel(r, base + GPIO2_INTENABLE); | 356 | __raw_writel(r, base + AU1000_GPIO2_INTENABLE); |
361 | wmb(); | 357 | wmb(); |
362 | } | 358 | } |
363 | 359 | ||
@@ -434,9 +430,9 @@ static inline void alchemy_gpio2_disable_int(int gpio2) | |||
434 | static inline void alchemy_gpio2_enable(void) | 430 | static inline void alchemy_gpio2_enable(void) |
435 | { | 431 | { |
436 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); | 432 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
437 | __raw_writel(3, base + GPIO2_ENABLE); /* reset, clock enabled */ | 433 | __raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */ |
438 | wmb(); | 434 | wmb(); |
439 | __raw_writel(1, base + GPIO2_ENABLE); /* clock enabled */ | 435 | __raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */ |
440 | wmb(); | 436 | wmb(); |
441 | } | 437 | } |
442 | 438 | ||
@@ -448,7 +444,7 @@ static inline void alchemy_gpio2_enable(void) | |||
448 | static inline void alchemy_gpio2_disable(void) | 444 | static inline void alchemy_gpio2_disable(void) |
449 | { | 445 | { |
450 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); | 446 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
451 | __raw_writel(2, base + GPIO2_ENABLE); /* reset, clock disabled */ | 447 | __raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */ |
452 | wmb(); | 448 | wmb(); |
453 | } | 449 | } |
454 | 450 | ||