aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/au1xxx_ide.h')
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_ide.h194
1 files changed, 194 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
new file mode 100644
index 000000000000..60638b8969ba
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
@@ -0,0 +1,194 @@
1/*
2 * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
3 *
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
6 *
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
8 *
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
12 * version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
31 */
32
33#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
34#define DMA_WAIT_TIMEOUT 100
35#define NUM_DESCRIPTORS PRD_ENTRIES
36#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
37#define NUM_DESCRIPTORS 2
38#endif
39
40#ifndef AU1XXX_ATA_RQSIZE
41#define AU1XXX_ATA_RQSIZE 128
42#endif
43
44/* Disable Burstable-Support for DBDMA */
45#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
46#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
47#endif
48
49#ifdef CONFIG_PM
50/*
51 * This will enable the device to be powered up when write() or read()
52 * is called. If this is not defined, the driver will return -EBUSY.
53 */
54#define WAKE_ON_ACCESS 1
55
56typedef struct {
57 spinlock_t lock; /* Used to block on state transitions */
58 au1xxx_power_dev_t *dev; /* Power Managers device structure */
59 unsigned stopped; /* Used to signal device is stopped */
60} pm_state;
61#endif
62
63typedef struct {
64 u32 tx_dev_id, rx_dev_id, target_dev_id;
65 u32 tx_chan, rx_chan;
66 void *tx_desc_head, *rx_desc_head;
67 ide_hwif_t *hwif;
68#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
69 ide_drive_t *drive;
70 struct dbdma_cmd *dma_table_cpu;
71 dma_addr_t dma_table_dma;
72#endif
73 int irq;
74 u32 regbase;
75#ifdef CONFIG_PM
76 pm_state pm;
77#endif
78} _auide_hwif;
79
80/******************************************************************************/
81/* PIO Mode timing calculation : */
82/* */
83/* Static Bus Spec ATA Spec */
84/* Tcsoe = t1 */
85/* Toecs = t9 */
86/* Twcs = t9 */
87/* Tcsh = t2i | t2 */
88/* Tcsoff = t2i | t2 */
89/* Twp = t2 */
90/* Tcsw = t1 */
91/* Tpm = 0 */
92/* Ta = t1+t2 */
93/******************************************************************************/
94
95#define TCSOE_MASK (0x07 << 29)
96#define TOECS_MASK (0x07 << 26)
97#define TWCS_MASK (0x07 << 28)
98#define TCSH_MASK (0x0F << 24)
99#define TCSOFF_MASK (0x07 << 20)
100#define TWP_MASK (0x3F << 14)
101#define TCSW_MASK (0x0F << 10)
102#define TPM_MASK (0x0F << 6)
103#define TA_MASK (0x3F << 0)
104#define TS_MASK (1 << 8)
105
106/* Timing parameters PIO mode 0 */
107#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
108#define SBC_IDE_PIO0_TOECS (0x01 << 26)
109#define SBC_IDE_PIO0_TWCS (0x02 << 28)
110#define SBC_IDE_PIO0_TCSH (0x08 << 24)
111#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
112#define SBC_IDE_PIO0_TWP (0x10 << 14)
113#define SBC_IDE_PIO0_TCSW (0x04 << 10)
114#define SBC_IDE_PIO0_TPM (0x00 << 6)
115#define SBC_IDE_PIO0_TA (0x15 << 0)
116/* Timing parameters PIO mode 1 */
117#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
118#define SBC_IDE_PIO1_TOECS (0x01 << 26)
119#define SBC_IDE_PIO1_TWCS (0x01 << 28)
120#define SBC_IDE_PIO1_TCSH (0x06 << 24)
121#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
122#define SBC_IDE_PIO1_TWP (0x08 << 14)
123#define SBC_IDE_PIO1_TCSW (0x03 << 10)
124#define SBC_IDE_PIO1_TPM (0x00 << 6)
125#define SBC_IDE_PIO1_TA (0x0B << 0)
126/* Timing parameters PIO mode 2 */
127#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
128#define SBC_IDE_PIO2_TOECS (0x01 << 26)
129#define SBC_IDE_PIO2_TWCS (0x01 << 28)
130#define SBC_IDE_PIO2_TCSH (0x07 << 24)
131#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
132#define SBC_IDE_PIO2_TWP (0x1F << 14)
133#define SBC_IDE_PIO2_TCSW (0x05 << 10)
134#define SBC_IDE_PIO2_TPM (0x00 << 6)
135#define SBC_IDE_PIO2_TA (0x22 << 0)
136/* Timing parameters PIO mode 3 */
137#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
138#define SBC_IDE_PIO3_TOECS (0x01 << 26)
139#define SBC_IDE_PIO3_TWCS (0x01 << 28)
140#define SBC_IDE_PIO3_TCSH (0x0D << 24)
141#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
142#define SBC_IDE_PIO3_TWP (0x15 << 14)
143#define SBC_IDE_PIO3_TCSW (0x05 << 10)
144#define SBC_IDE_PIO3_TPM (0x00 << 6)
145#define SBC_IDE_PIO3_TA (0x1A << 0)
146/* Timing parameters PIO mode 4 */
147#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
148#define SBC_IDE_PIO4_TOECS (0x01 << 26)
149#define SBC_IDE_PIO4_TWCS (0x01 << 28)
150#define SBC_IDE_PIO4_TCSH (0x04 << 24)
151#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
152#define SBC_IDE_PIO4_TWP (0x0D << 14)
153#define SBC_IDE_PIO4_TCSW (0x03 << 10)
154#define SBC_IDE_PIO4_TPM (0x00 << 6)
155#define SBC_IDE_PIO4_TA (0x12 << 0)
156/* Timing parameters MDMA mode 0 */
157#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
158#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
159#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
160#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
161#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
162#define SBC_IDE_MDMA0_TWP (0x0C << 14)
163#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
164#define SBC_IDE_MDMA0_TPM (0x00 << 6)
165#define SBC_IDE_MDMA0_TA (0x0F << 0)
166/* Timing parameters MDMA mode 1 */
167#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
168#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
169#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
170#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
171#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
172#define SBC_IDE_MDMA1_TWP (0x0F << 14)
173#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
174#define SBC_IDE_MDMA1_TPM (0x00 << 6)
175#define SBC_IDE_MDMA1_TA (0x15 << 0)
176/* Timing parameters MDMA mode 2 */
177#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
178#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
179#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
180#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
181#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
182#define SBC_IDE_MDMA2_TWP (0x0D << 14)
183#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
184#define SBC_IDE_MDMA2_TPM (0x00 << 6)
185#define SBC_IDE_MDMA2_TA (0x12 << 0)
186
187#define SBC_IDE_TIMING(mode) \
188 (SBC_IDE_##mode##_TWCS | \
189 SBC_IDE_##mode##_TCSH | \
190 SBC_IDE_##mode##_TCSOFF | \
191 SBC_IDE_##mode##_TWP | \
192 SBC_IDE_##mode##_TCSW | \
193 SBC_IDE_##mode##_TPM | \
194 SBC_IDE_##mode##_TA)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 03:04:30 -0500