diff options
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h')
-rw-r--r-- | arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 116 |
1 files changed, 56 insertions, 60 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 2fdacfe85e23..323ce2d145f2 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | |||
@@ -126,66 +126,62 @@ typedef volatile struct au1xxx_ddma_desc { | |||
126 | #define SW_STATUS_INUSE (1 << 0) | 126 | #define SW_STATUS_INUSE (1 << 0) |
127 | 127 | ||
128 | /* Command 0 device IDs. */ | 128 | /* Command 0 device IDs. */ |
129 | #ifdef CONFIG_SOC_AU1550 | 129 | #define AU1550_DSCR_CMD0_UART0_TX 0 |
130 | #define DSCR_CMD0_UART0_TX 0 | 130 | #define AU1550_DSCR_CMD0_UART0_RX 1 |
131 | #define DSCR_CMD0_UART0_RX 1 | 131 | #define AU1550_DSCR_CMD0_UART3_TX 2 |
132 | #define DSCR_CMD0_UART3_TX 2 | 132 | #define AU1550_DSCR_CMD0_UART3_RX 3 |
133 | #define DSCR_CMD0_UART3_RX 3 | 133 | #define AU1550_DSCR_CMD0_DMA_REQ0 4 |
134 | #define DSCR_CMD0_DMA_REQ0 4 | 134 | #define AU1550_DSCR_CMD0_DMA_REQ1 5 |
135 | #define DSCR_CMD0_DMA_REQ1 5 | 135 | #define AU1550_DSCR_CMD0_DMA_REQ2 6 |
136 | #define DSCR_CMD0_DMA_REQ2 6 | 136 | #define AU1550_DSCR_CMD0_DMA_REQ3 7 |
137 | #define DSCR_CMD0_DMA_REQ3 7 | 137 | #define AU1550_DSCR_CMD0_USBDEV_RX0 8 |
138 | #define DSCR_CMD0_USBDEV_RX0 8 | 138 | #define AU1550_DSCR_CMD0_USBDEV_TX0 9 |
139 | #define DSCR_CMD0_USBDEV_TX0 9 | 139 | #define AU1550_DSCR_CMD0_USBDEV_TX1 10 |
140 | #define DSCR_CMD0_USBDEV_TX1 10 | 140 | #define AU1550_DSCR_CMD0_USBDEV_TX2 11 |
141 | #define DSCR_CMD0_USBDEV_TX2 11 | 141 | #define AU1550_DSCR_CMD0_USBDEV_RX3 12 |
142 | #define DSCR_CMD0_USBDEV_RX3 12 | 142 | #define AU1550_DSCR_CMD0_USBDEV_RX4 13 |
143 | #define DSCR_CMD0_USBDEV_RX4 13 | 143 | #define AU1550_DSCR_CMD0_PSC0_TX 14 |
144 | #define DSCR_CMD0_PSC0_TX 14 | 144 | #define AU1550_DSCR_CMD0_PSC0_RX 15 |
145 | #define DSCR_CMD0_PSC0_RX 15 | 145 | #define AU1550_DSCR_CMD0_PSC1_TX 16 |
146 | #define DSCR_CMD0_PSC1_TX 16 | 146 | #define AU1550_DSCR_CMD0_PSC1_RX 17 |
147 | #define DSCR_CMD0_PSC1_RX 17 | 147 | #define AU1550_DSCR_CMD0_PSC2_TX 18 |
148 | #define DSCR_CMD0_PSC2_TX 18 | 148 | #define AU1550_DSCR_CMD0_PSC2_RX 19 |
149 | #define DSCR_CMD0_PSC2_RX 19 | 149 | #define AU1550_DSCR_CMD0_PSC3_TX 20 |
150 | #define DSCR_CMD0_PSC3_TX 20 | 150 | #define AU1550_DSCR_CMD0_PSC3_RX 21 |
151 | #define DSCR_CMD0_PSC3_RX 21 | 151 | #define AU1550_DSCR_CMD0_PCI_WRITE 22 |
152 | #define DSCR_CMD0_PCI_WRITE 22 | 152 | #define AU1550_DSCR_CMD0_NAND_FLASH 23 |
153 | #define DSCR_CMD0_NAND_FLASH 23 | 153 | #define AU1550_DSCR_CMD0_MAC0_RX 24 |
154 | #define DSCR_CMD0_MAC0_RX 24 | 154 | #define AU1550_DSCR_CMD0_MAC0_TX 25 |
155 | #define DSCR_CMD0_MAC0_TX 25 | 155 | #define AU1550_DSCR_CMD0_MAC1_RX 26 |
156 | #define DSCR_CMD0_MAC1_RX 26 | 156 | #define AU1550_DSCR_CMD0_MAC1_TX 27 |
157 | #define DSCR_CMD0_MAC1_TX 27 | 157 | |
158 | #endif /* CONFIG_SOC_AU1550 */ | 158 | #define AU1200_DSCR_CMD0_UART0_TX 0 |
159 | 159 | #define AU1200_DSCR_CMD0_UART0_RX 1 | |
160 | #ifdef CONFIG_SOC_AU1200 | 160 | #define AU1200_DSCR_CMD0_UART1_TX 2 |
161 | #define DSCR_CMD0_UART0_TX 0 | 161 | #define AU1200_DSCR_CMD0_UART1_RX 3 |
162 | #define DSCR_CMD0_UART0_RX 1 | 162 | #define AU1200_DSCR_CMD0_DMA_REQ0 4 |
163 | #define DSCR_CMD0_UART1_TX 2 | 163 | #define AU1200_DSCR_CMD0_DMA_REQ1 5 |
164 | #define DSCR_CMD0_UART1_RX 3 | 164 | #define AU1200_DSCR_CMD0_MAE_BE 6 |
165 | #define DSCR_CMD0_DMA_REQ0 4 | 165 | #define AU1200_DSCR_CMD0_MAE_FE 7 |
166 | #define DSCR_CMD0_DMA_REQ1 5 | 166 | #define AU1200_DSCR_CMD0_SDMS_TX0 8 |
167 | #define DSCR_CMD0_MAE_BE 6 | 167 | #define AU1200_DSCR_CMD0_SDMS_RX0 9 |
168 | #define DSCR_CMD0_MAE_FE 7 | 168 | #define AU1200_DSCR_CMD0_SDMS_TX1 10 |
169 | #define DSCR_CMD0_SDMS_TX0 8 | 169 | #define AU1200_DSCR_CMD0_SDMS_RX1 11 |
170 | #define DSCR_CMD0_SDMS_RX0 9 | 170 | #define AU1200_DSCR_CMD0_AES_TX 13 |
171 | #define DSCR_CMD0_SDMS_TX1 10 | 171 | #define AU1200_DSCR_CMD0_AES_RX 12 |
172 | #define DSCR_CMD0_SDMS_RX1 11 | 172 | #define AU1200_DSCR_CMD0_PSC0_TX 14 |
173 | #define DSCR_CMD0_AES_TX 13 | 173 | #define AU1200_DSCR_CMD0_PSC0_RX 15 |
174 | #define DSCR_CMD0_AES_RX 12 | 174 | #define AU1200_DSCR_CMD0_PSC1_TX 16 |
175 | #define DSCR_CMD0_PSC0_TX 14 | 175 | #define AU1200_DSCR_CMD0_PSC1_RX 17 |
176 | #define DSCR_CMD0_PSC0_RX 15 | 176 | #define AU1200_DSCR_CMD0_CIM_RXA 18 |
177 | #define DSCR_CMD0_PSC1_TX 16 | 177 | #define AU1200_DSCR_CMD0_CIM_RXB 19 |
178 | #define DSCR_CMD0_PSC1_RX 17 | 178 | #define AU1200_DSCR_CMD0_CIM_RXC 20 |
179 | #define DSCR_CMD0_CIM_RXA 18 | 179 | #define AU1200_DSCR_CMD0_MAE_BOTH 21 |
180 | #define DSCR_CMD0_CIM_RXB 19 | 180 | #define AU1200_DSCR_CMD0_LCD 22 |
181 | #define DSCR_CMD0_CIM_RXC 20 | 181 | #define AU1200_DSCR_CMD0_NAND_FLASH 23 |
182 | #define DSCR_CMD0_MAE_BOTH 21 | 182 | #define AU1200_DSCR_CMD0_PSC0_SYNC 24 |
183 | #define DSCR_CMD0_LCD 22 | 183 | #define AU1200_DSCR_CMD0_PSC1_SYNC 25 |
184 | #define DSCR_CMD0_NAND_FLASH 23 | 184 | #define AU1200_DSCR_CMD0_CIM_SYNC 26 |
185 | #define DSCR_CMD0_PSC0_SYNC 24 | ||
186 | #define DSCR_CMD0_PSC1_SYNC 25 | ||
187 | #define DSCR_CMD0_CIM_SYNC 26 | ||
188 | #endif /* CONFIG_SOC_AU1200 */ | ||
189 | 185 | ||
190 | #define DSCR_CMD0_THROTTLE 30 | 186 | #define DSCR_CMD0_THROTTLE 30 |
191 | #define DSCR_CMD0_ALWAYS 31 | 187 | #define DSCR_CMD0_ALWAYS 31 |