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Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h')
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h12
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 54f9e84db8ac..b4c3ecb17d48 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -1161,18 +1161,6 @@ enum soc_au1200_ints {
1161#define MAC_RX_BUFF3_STATUS 0x30 1161#define MAC_RX_BUFF3_STATUS 0x30
1162#define MAC_RX_BUFF3_ADDR 0x34 1162#define MAC_RX_BUFF3_ADDR 0x34
1163 1163
1164#define UART_RX 0 /* Receive buffer */
1165#define UART_TX 4 /* Transmit buffer */
1166#define UART_IER 8 /* Interrupt Enable Register */
1167#define UART_IIR 0xC /* Interrupt ID Register */
1168#define UART_FCR 0x10 /* FIFO Control Register */
1169#define UART_LCR 0x14 /* Line Control Register */
1170#define UART_MCR 0x18 /* Modem Control Register */
1171#define UART_LSR 0x1C /* Line Status Register */
1172#define UART_MSR 0x20 /* Modem Status Register */
1173#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1174#define UART_MOD_CNTRL 0x100 /* Module Control */
1175
1176/* SSIO */ 1164/* SSIO */
1177#define SSI0_STATUS 0xB1600000 1165#define SSI0_STATUS 0xB1600000
1178# define SSI_STATUS_BF (1 << 4) 1166# define SSI_STATUS_BF (1 << 4)