aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include/asm/mach-au1x00/au1000.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h')
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h913
1 files changed, 417 insertions, 496 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 854e95f1b07c..a6976619160a 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -130,6 +130,56 @@ static inline int au1xxx_cpu_needs_config_od(void)
130 return 0; 130 return 0;
131} 131}
132 132
133#define ALCHEMY_CPU_UNKNOWN -1
134#define ALCHEMY_CPU_AU1000 0
135#define ALCHEMY_CPU_AU1500 1
136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4
139
140static inline int alchemy_get_cputype(void)
141{
142 switch (read_c0_prid() & 0xffff0000) {
143 case 0x00030000:
144 return ALCHEMY_CPU_AU1000;
145 break;
146 case 0x01030000:
147 return ALCHEMY_CPU_AU1500;
148 break;
149 case 0x02030000:
150 return ALCHEMY_CPU_AU1100;
151 break;
152 case 0x03030000:
153 return ALCHEMY_CPU_AU1550;
154 break;
155 case 0x04030000:
156 case 0x05030000:
157 return ALCHEMY_CPU_AU1200;
158 break;
159 }
160
161 return ALCHEMY_CPU_UNKNOWN;
162}
163
164static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
165{
166 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
167 int timeout, i;
168
169 /* check LSR TX_EMPTY bit */
170 timeout = 0xffffff;
171 do {
172 if (__raw_readl(base + 0x1c) & 0x20)
173 break;
174 /* slow down */
175 for (i = 10000; i; i--)
176 asm volatile ("nop");
177 } while (--timeout);
178
179 __raw_writel(c, base + 0x04); /* tx */
180 wmb();
181}
182
133/* arch/mips/au1000/common/clocks.c */ 183/* arch/mips/au1000/common/clocks.c */
134extern void set_au1x00_speed(unsigned int new_freq); 184extern void set_au1x00_speed(unsigned int new_freq);
135extern unsigned int get_au1x00_speed(void); 185extern unsigned int get_au1x00_speed(void);
@@ -138,25 +188,336 @@ extern unsigned long get_au1x00_uart_baud_base(void);
138extern unsigned long au1xxx_calc_clock(void); 188extern unsigned long au1xxx_calc_clock(void);
139 189
140/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ 190/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
141void au1xxx_save_and_sleep(void); 191void alchemy_sleep_au1000(void);
192void alchemy_sleep_au1550(void);
142void au_sleep(void); 193void au_sleep(void);
143void save_au1xxx_intctl(void);
144void restore_au1xxx_intctl(void);
145 194
146/* 195
147 * Every board describes its IRQ mapping with this table. 196/* SOC Interrupt numbers */
148 */ 197
149struct au1xxx_irqmap { 198#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
150 int im_irq; 199#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
151 int im_type; 200#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
152 int im_request; 201#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
202#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
203
204enum soc_au1000_ints {
205 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
206 AU1000_UART0_INT = AU1000_FIRST_INT,
207 AU1000_UART1_INT,
208 AU1000_UART2_INT,
209 AU1000_UART3_INT,
210 AU1000_SSI0_INT,
211 AU1000_SSI1_INT,
212 AU1000_DMA_INT_BASE,
213
214 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
215 AU1000_TOY_MATCH0_INT,
216 AU1000_TOY_MATCH1_INT,
217 AU1000_TOY_MATCH2_INT,
218 AU1000_RTC_INT,
219 AU1000_RTC_MATCH0_INT,
220 AU1000_RTC_MATCH1_INT,
221 AU1000_RTC_MATCH2_INT,
222 AU1000_IRDA_TX_INT,
223 AU1000_IRDA_RX_INT,
224 AU1000_USB_DEV_REQ_INT,
225 AU1000_USB_DEV_SUS_INT,
226 AU1000_USB_HOST_INT,
227 AU1000_ACSYNC_INT,
228 AU1000_MAC0_DMA_INT,
229 AU1000_MAC1_DMA_INT,
230 AU1000_I2S_UO_INT,
231 AU1000_AC97C_INT,
232 AU1000_GPIO0_INT,
233 AU1000_GPIO1_INT,
234 AU1000_GPIO2_INT,
235 AU1000_GPIO3_INT,
236 AU1000_GPIO4_INT,
237 AU1000_GPIO5_INT,
238 AU1000_GPIO6_INT,
239 AU1000_GPIO7_INT,
240 AU1000_GPIO8_INT,
241 AU1000_GPIO9_INT,
242 AU1000_GPIO10_INT,
243 AU1000_GPIO11_INT,
244 AU1000_GPIO12_INT,
245 AU1000_GPIO13_INT,
246 AU1000_GPIO14_INT,
247 AU1000_GPIO15_INT,
248 AU1000_GPIO16_INT,
249 AU1000_GPIO17_INT,
250 AU1000_GPIO18_INT,
251 AU1000_GPIO19_INT,
252 AU1000_GPIO20_INT,
253 AU1000_GPIO21_INT,
254 AU1000_GPIO22_INT,
255 AU1000_GPIO23_INT,
256 AU1000_GPIO24_INT,
257 AU1000_GPIO25_INT,
258 AU1000_GPIO26_INT,
259 AU1000_GPIO27_INT,
260 AU1000_GPIO28_INT,
261 AU1000_GPIO29_INT,
262 AU1000_GPIO30_INT,
263 AU1000_GPIO31_INT,
264};
265
266enum soc_au1100_ints {
267 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
268 AU1100_UART0_INT = AU1100_FIRST_INT,
269 AU1100_UART1_INT,
270 AU1100_SD_INT,
271 AU1100_UART3_INT,
272 AU1100_SSI0_INT,
273 AU1100_SSI1_INT,
274 AU1100_DMA_INT_BASE,
275
276 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
277 AU1100_TOY_MATCH0_INT,
278 AU1100_TOY_MATCH1_INT,
279 AU1100_TOY_MATCH2_INT,
280 AU1100_RTC_INT,
281 AU1100_RTC_MATCH0_INT,
282 AU1100_RTC_MATCH1_INT,
283 AU1100_RTC_MATCH2_INT,
284 AU1100_IRDA_TX_INT,
285 AU1100_IRDA_RX_INT,
286 AU1100_USB_DEV_REQ_INT,
287 AU1100_USB_DEV_SUS_INT,
288 AU1100_USB_HOST_INT,
289 AU1100_ACSYNC_INT,
290 AU1100_MAC0_DMA_INT,
291 AU1100_GPIO208_215_INT,
292 AU1100_LCD_INT,
293 AU1100_AC97C_INT,
294 AU1100_GPIO0_INT,
295 AU1100_GPIO1_INT,
296 AU1100_GPIO2_INT,
297 AU1100_GPIO3_INT,
298 AU1100_GPIO4_INT,
299 AU1100_GPIO5_INT,
300 AU1100_GPIO6_INT,
301 AU1100_GPIO7_INT,
302 AU1100_GPIO8_INT,
303 AU1100_GPIO9_INT,
304 AU1100_GPIO10_INT,
305 AU1100_GPIO11_INT,
306 AU1100_GPIO12_INT,
307 AU1100_GPIO13_INT,
308 AU1100_GPIO14_INT,
309 AU1100_GPIO15_INT,
310 AU1100_GPIO16_INT,
311 AU1100_GPIO17_INT,
312 AU1100_GPIO18_INT,
313 AU1100_GPIO19_INT,
314 AU1100_GPIO20_INT,
315 AU1100_GPIO21_INT,
316 AU1100_GPIO22_INT,
317 AU1100_GPIO23_INT,
318 AU1100_GPIO24_INT,
319 AU1100_GPIO25_INT,
320 AU1100_GPIO26_INT,
321 AU1100_GPIO27_INT,
322 AU1100_GPIO28_INT,
323 AU1100_GPIO29_INT,
324 AU1100_GPIO30_INT,
325 AU1100_GPIO31_INT,
326};
327
328enum soc_au1500_ints {
329 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
330 AU1500_UART0_INT = AU1500_FIRST_INT,
331 AU1500_PCI_INTA,
332 AU1500_PCI_INTB,
333 AU1500_UART3_INT,
334 AU1500_PCI_INTC,
335 AU1500_PCI_INTD,
336 AU1500_DMA_INT_BASE,
337
338 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
339 AU1500_TOY_MATCH0_INT,
340 AU1500_TOY_MATCH1_INT,
341 AU1500_TOY_MATCH2_INT,
342 AU1500_RTC_INT,
343 AU1500_RTC_MATCH0_INT,
344 AU1500_RTC_MATCH1_INT,
345 AU1500_RTC_MATCH2_INT,
346 AU1500_PCI_ERR_INT,
347 AU1500_RESERVED_INT,
348 AU1500_USB_DEV_REQ_INT,
349 AU1500_USB_DEV_SUS_INT,
350 AU1500_USB_HOST_INT,
351 AU1500_ACSYNC_INT,
352 AU1500_MAC0_DMA_INT,
353 AU1500_MAC1_DMA_INT,
354 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
355 AU1500_GPIO0_INT,
356 AU1500_GPIO1_INT,
357 AU1500_GPIO2_INT,
358 AU1500_GPIO3_INT,
359 AU1500_GPIO4_INT,
360 AU1500_GPIO5_INT,
361 AU1500_GPIO6_INT,
362 AU1500_GPIO7_INT,
363 AU1500_GPIO8_INT,
364 AU1500_GPIO9_INT,
365 AU1500_GPIO10_INT,
366 AU1500_GPIO11_INT,
367 AU1500_GPIO12_INT,
368 AU1500_GPIO13_INT,
369 AU1500_GPIO14_INT,
370 AU1500_GPIO15_INT,
371 AU1500_GPIO200_INT,
372 AU1500_GPIO201_INT,
373 AU1500_GPIO202_INT,
374 AU1500_GPIO203_INT,
375 AU1500_GPIO20_INT,
376 AU1500_GPIO204_INT,
377 AU1500_GPIO205_INT,
378 AU1500_GPIO23_INT,
379 AU1500_GPIO24_INT,
380 AU1500_GPIO25_INT,
381 AU1500_GPIO26_INT,
382 AU1500_GPIO27_INT,
383 AU1500_GPIO28_INT,
384 AU1500_GPIO206_INT,
385 AU1500_GPIO207_INT,
386 AU1500_GPIO208_215_INT,
153}; 387};
154 388
155/* core calls this function to let boards initialize other IRQ sources */ 389enum soc_au1550_ints {
156void board_init_irq(void); 390 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
391 AU1550_UART0_INT = AU1550_FIRST_INT,
392 AU1550_PCI_INTA,
393 AU1550_PCI_INTB,
394 AU1550_DDMA_INT,
395 AU1550_CRYPTO_INT,
396 AU1550_PCI_INTC,
397 AU1550_PCI_INTD,
398 AU1550_PCI_RST_INT,
399 AU1550_UART1_INT,
400 AU1550_UART3_INT,
401 AU1550_PSC0_INT,
402 AU1550_PSC1_INT,
403 AU1550_PSC2_INT,
404 AU1550_PSC3_INT,
405 AU1550_TOY_INT,
406 AU1550_TOY_MATCH0_INT,
407 AU1550_TOY_MATCH1_INT,
408 AU1550_TOY_MATCH2_INT,
409 AU1550_RTC_INT,
410 AU1550_RTC_MATCH0_INT,
411 AU1550_RTC_MATCH1_INT,
412 AU1550_RTC_MATCH2_INT,
413
414 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
415 AU1550_USB_DEV_REQ_INT,
416 AU1550_USB_DEV_SUS_INT,
417 AU1550_USB_HOST_INT,
418 AU1550_MAC0_DMA_INT,
419 AU1550_MAC1_DMA_INT,
420 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
421 AU1550_GPIO1_INT,
422 AU1550_GPIO2_INT,
423 AU1550_GPIO3_INT,
424 AU1550_GPIO4_INT,
425 AU1550_GPIO5_INT,
426 AU1550_GPIO6_INT,
427 AU1550_GPIO7_INT,
428 AU1550_GPIO8_INT,
429 AU1550_GPIO9_INT,
430 AU1550_GPIO10_INT,
431 AU1550_GPIO11_INT,
432 AU1550_GPIO12_INT,
433 AU1550_GPIO13_INT,
434 AU1550_GPIO14_INT,
435 AU1550_GPIO15_INT,
436 AU1550_GPIO200_INT,
437 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
438 AU1550_GPIO16_INT,
439 AU1550_GPIO17_INT,
440 AU1550_GPIO20_INT,
441 AU1550_GPIO21_INT,
442 AU1550_GPIO22_INT,
443 AU1550_GPIO23_INT,
444 AU1550_GPIO24_INT,
445 AU1550_GPIO25_INT,
446 AU1550_GPIO26_INT,
447 AU1550_GPIO27_INT,
448 AU1550_GPIO28_INT,
449 AU1550_GPIO206_INT,
450 AU1550_GPIO207_INT,
451 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
452};
157 453
158/* boards call this to register additional (GPIO) interrupts */ 454enum soc_au1200_ints {
159void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); 455 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
456 AU1200_UART0_INT = AU1200_FIRST_INT,
457 AU1200_SWT_INT,
458 AU1200_SD_INT,
459 AU1200_DDMA_INT,
460 AU1200_MAE_BE_INT,
461 AU1200_GPIO200_INT,
462 AU1200_GPIO201_INT,
463 AU1200_GPIO202_INT,
464 AU1200_UART1_INT,
465 AU1200_MAE_FE_INT,
466 AU1200_PSC0_INT,
467 AU1200_PSC1_INT,
468 AU1200_AES_INT,
469 AU1200_CAMERA_INT,
470 AU1200_TOY_INT,
471 AU1200_TOY_MATCH0_INT,
472 AU1200_TOY_MATCH1_INT,
473 AU1200_TOY_MATCH2_INT,
474 AU1200_RTC_INT,
475 AU1200_RTC_MATCH0_INT,
476 AU1200_RTC_MATCH1_INT,
477 AU1200_RTC_MATCH2_INT,
478 AU1200_GPIO203_INT,
479 AU1200_NAND_INT,
480 AU1200_GPIO204_INT,
481 AU1200_GPIO205_INT,
482 AU1200_GPIO206_INT,
483 AU1200_GPIO207_INT,
484 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
485 AU1200_USB_INT,
486 AU1200_LCD_INT,
487 AU1200_MAE_BOTH_INT,
488 AU1200_GPIO0_INT,
489 AU1200_GPIO1_INT,
490 AU1200_GPIO2_INT,
491 AU1200_GPIO3_INT,
492 AU1200_GPIO4_INT,
493 AU1200_GPIO5_INT,
494 AU1200_GPIO6_INT,
495 AU1200_GPIO7_INT,
496 AU1200_GPIO8_INT,
497 AU1200_GPIO9_INT,
498 AU1200_GPIO10_INT,
499 AU1200_GPIO11_INT,
500 AU1200_GPIO12_INT,
501 AU1200_GPIO13_INT,
502 AU1200_GPIO14_INT,
503 AU1200_GPIO15_INT,
504 AU1200_GPIO16_INT,
505 AU1200_GPIO17_INT,
506 AU1200_GPIO18_INT,
507 AU1200_GPIO19_INT,
508 AU1200_GPIO20_INT,
509 AU1200_GPIO21_INT,
510 AU1200_GPIO22_INT,
511 AU1200_GPIO23_INT,
512 AU1200_GPIO24_INT,
513 AU1200_GPIO25_INT,
514 AU1200_GPIO26_INT,
515 AU1200_GPIO27_INT,
516 AU1200_GPIO28_INT,
517 AU1200_GPIO29_INT,
518 AU1200_GPIO30_INT,
519 AU1200_GPIO31_INT,
520};
160 521
161#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 522#endif /* !defined (_LANGUAGE_ASSEMBLY) */
162 523
@@ -473,6 +834,38 @@ void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
473#define MEM_STNAND_DATA 0x20 834#define MEM_STNAND_DATA 0x20
474#endif 835#endif
475 836
837
838/* Interrupt Controller register offsets */
839#define IC_CFG0RD 0x40
840#define IC_CFG0SET 0x40
841#define IC_CFG0CLR 0x44
842#define IC_CFG1RD 0x48
843#define IC_CFG1SET 0x48
844#define IC_CFG1CLR 0x4C
845#define IC_CFG2RD 0x50
846#define IC_CFG2SET 0x50
847#define IC_CFG2CLR 0x54
848#define IC_REQ0INT 0x54
849#define IC_SRCRD 0x58
850#define IC_SRCSET 0x58
851#define IC_SRCCLR 0x5C
852#define IC_REQ1INT 0x5C
853#define IC_ASSIGNRD 0x60
854#define IC_ASSIGNSET 0x60
855#define IC_ASSIGNCLR 0x64
856#define IC_WAKERD 0x68
857#define IC_WAKESET 0x68
858#define IC_WAKECLR 0x6C
859#define IC_MASKRD 0x70
860#define IC_MASKSET 0x70
861#define IC_MASKCLR 0x74
862#define IC_RISINGRD 0x78
863#define IC_RISINGCLR 0x78
864#define IC_FALLINGRD 0x7C
865#define IC_FALLINGCLR 0x7C
866#define IC_TESTBIT 0x80
867
868
476/* Interrupt Controller 0 */ 869/* Interrupt Controller 0 */
477#define IC0_CFG0RD 0xB0400040 870#define IC0_CFG0RD 0xB0400040
478#define IC0_CFG0SET 0xB0400040 871#define IC0_CFG0SET 0xB0400040
@@ -549,78 +942,16 @@ void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
549 942
550#define IC1_TESTBIT 0xB1800080 943#define IC1_TESTBIT 0xB1800080
551 944
552/* Interrupt Numbers */ 945
553/* Au1000 */ 946/* Au1000 */
554#ifdef CONFIG_SOC_AU1000 947#ifdef CONFIG_SOC_AU1000
555enum soc_au1000_ints {
556 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
557 AU1000_UART0_INT = AU1000_FIRST_INT,
558 AU1000_UART1_INT, /* au1000 */
559 AU1000_UART2_INT, /* au1000 */
560 AU1000_UART3_INT,
561 AU1000_SSI0_INT, /* au1000 */
562 AU1000_SSI1_INT, /* au1000 */
563 AU1000_DMA_INT_BASE,
564
565 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
566 AU1000_TOY_MATCH0_INT,
567 AU1000_TOY_MATCH1_INT,
568 AU1000_TOY_MATCH2_INT,
569 AU1000_RTC_INT,
570 AU1000_RTC_MATCH0_INT,
571 AU1000_RTC_MATCH1_INT,
572 AU1000_RTC_MATCH2_INT,
573 AU1000_IRDA_TX_INT, /* au1000 */
574 AU1000_IRDA_RX_INT, /* au1000 */
575 AU1000_USB_DEV_REQ_INT,
576 AU1000_USB_DEV_SUS_INT,
577 AU1000_USB_HOST_INT,
578 AU1000_ACSYNC_INT,
579 AU1000_MAC0_DMA_INT,
580 AU1000_MAC1_DMA_INT,
581 AU1000_I2S_UO_INT, /* au1000 */
582 AU1000_AC97C_INT,
583 AU1000_GPIO_0,
584 AU1000_GPIO_1,
585 AU1000_GPIO_2,
586 AU1000_GPIO_3,
587 AU1000_GPIO_4,
588 AU1000_GPIO_5,
589 AU1000_GPIO_6,
590 AU1000_GPIO_7,
591 AU1000_GPIO_8,
592 AU1000_GPIO_9,
593 AU1000_GPIO_10,
594 AU1000_GPIO_11,
595 AU1000_GPIO_12,
596 AU1000_GPIO_13,
597 AU1000_GPIO_14,
598 AU1000_GPIO_15,
599 AU1000_GPIO_16,
600 AU1000_GPIO_17,
601 AU1000_GPIO_18,
602 AU1000_GPIO_19,
603 AU1000_GPIO_20,
604 AU1000_GPIO_21,
605 AU1000_GPIO_22,
606 AU1000_GPIO_23,
607 AU1000_GPIO_24,
608 AU1000_GPIO_25,
609 AU1000_GPIO_26,
610 AU1000_GPIO_27,
611 AU1000_GPIO_28,
612 AU1000_GPIO_29,
613 AU1000_GPIO_30,
614 AU1000_GPIO_31,
615};
616 948
617#define UART0_ADDR 0xB1100000 949#define UART0_ADDR 0xB1100000
618#define UART1_ADDR 0xB1200000
619#define UART2_ADDR 0xB1300000
620#define UART3_ADDR 0xB1400000 950#define UART3_ADDR 0xB1400000
621 951
622#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 952#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
623#define USB_HOST_CONFIG 0xB017FFFC 953#define USB_HOST_CONFIG 0xB017FFFC
954#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
624 955
625#define AU1000_ETH0_BASE 0xB0500000 956#define AU1000_ETH0_BASE 0xB0500000
626#define AU1000_ETH1_BASE 0xB0510000 957#define AU1000_ETH1_BASE 0xB0510000
@@ -631,78 +962,13 @@ enum soc_au1000_ints {
631 962
632/* Au1500 */ 963/* Au1500 */
633#ifdef CONFIG_SOC_AU1500 964#ifdef CONFIG_SOC_AU1500
634enum soc_au1500_ints {
635 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
636 AU1500_UART0_INT = AU1500_FIRST_INT,
637 AU1000_PCI_INTA, /* au1500 */
638 AU1000_PCI_INTB, /* au1500 */
639 AU1500_UART3_INT,
640 AU1000_PCI_INTC, /* au1500 */
641 AU1000_PCI_INTD, /* au1500 */
642 AU1000_DMA_INT_BASE,
643
644 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
645 AU1000_TOY_MATCH0_INT,
646 AU1000_TOY_MATCH1_INT,
647 AU1000_TOY_MATCH2_INT,
648 AU1000_RTC_INT,
649 AU1000_RTC_MATCH0_INT,
650 AU1000_RTC_MATCH1_INT,
651 AU1000_RTC_MATCH2_INT,
652 AU1500_PCI_ERR_INT,
653 AU1500_RESERVED_INT,
654 AU1000_USB_DEV_REQ_INT,
655 AU1000_USB_DEV_SUS_INT,
656 AU1000_USB_HOST_INT,
657 AU1000_ACSYNC_INT,
658 AU1500_MAC0_DMA_INT,
659 AU1500_MAC1_DMA_INT,
660 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
661 AU1000_GPIO_0,
662 AU1000_GPIO_1,
663 AU1000_GPIO_2,
664 AU1000_GPIO_3,
665 AU1000_GPIO_4,
666 AU1000_GPIO_5,
667 AU1000_GPIO_6,
668 AU1000_GPIO_7,
669 AU1000_GPIO_8,
670 AU1000_GPIO_9,
671 AU1000_GPIO_10,
672 AU1000_GPIO_11,
673 AU1000_GPIO_12,
674 AU1000_GPIO_13,
675 AU1000_GPIO_14,
676 AU1000_GPIO_15,
677 AU1500_GPIO_200,
678 AU1500_GPIO_201,
679 AU1500_GPIO_202,
680 AU1500_GPIO_203,
681 AU1500_GPIO_20,
682 AU1500_GPIO_204,
683 AU1500_GPIO_205,
684 AU1500_GPIO_23,
685 AU1500_GPIO_24,
686 AU1500_GPIO_25,
687 AU1500_GPIO_26,
688 AU1500_GPIO_27,
689 AU1500_GPIO_28,
690 AU1500_GPIO_206,
691 AU1500_GPIO_207,
692 AU1500_GPIO_208_215,
693};
694
695/* shortcuts */
696#define INTA AU1000_PCI_INTA
697#define INTB AU1000_PCI_INTB
698#define INTC AU1000_PCI_INTC
699#define INTD AU1000_PCI_INTD
700 965
701#define UART0_ADDR 0xB1100000 966#define UART0_ADDR 0xB1100000
702#define UART3_ADDR 0xB1400000 967#define UART3_ADDR 0xB1400000
703 968
704#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 969#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
705#define USB_HOST_CONFIG 0xB017fffc 970#define USB_HOST_CONFIG 0xB017fffc
971#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
706 972
707#define AU1500_ETH0_BASE 0xB1500000 973#define AU1500_ETH0_BASE 0xB1500000
708#define AU1500_ETH1_BASE 0xB1510000 974#define AU1500_ETH1_BASE 0xB1510000
@@ -713,74 +979,13 @@ enum soc_au1500_ints {
713 979
714/* Au1100 */ 980/* Au1100 */
715#ifdef CONFIG_SOC_AU1100 981#ifdef CONFIG_SOC_AU1100
716enum soc_au1100_ints {
717 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
718 AU1100_UART0_INT = AU1100_FIRST_INT,
719 AU1100_UART1_INT,
720 AU1100_SD_INT,
721 AU1100_UART3_INT,
722 AU1000_SSI0_INT,
723 AU1000_SSI1_INT,
724 AU1000_DMA_INT_BASE,
725
726 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
727 AU1000_TOY_MATCH0_INT,
728 AU1000_TOY_MATCH1_INT,
729 AU1000_TOY_MATCH2_INT,
730 AU1000_RTC_INT,
731 AU1000_RTC_MATCH0_INT,
732 AU1000_RTC_MATCH1_INT,
733 AU1000_RTC_MATCH2_INT,
734 AU1000_IRDA_TX_INT,
735 AU1000_IRDA_RX_INT,
736 AU1000_USB_DEV_REQ_INT,
737 AU1000_USB_DEV_SUS_INT,
738 AU1000_USB_HOST_INT,
739 AU1000_ACSYNC_INT,
740 AU1100_MAC0_DMA_INT,
741 AU1100_GPIO_208_215,
742 AU1100_LCD_INT,
743 AU1000_AC97C_INT,
744 AU1000_GPIO_0,
745 AU1000_GPIO_1,
746 AU1000_GPIO_2,
747 AU1000_GPIO_3,
748 AU1000_GPIO_4,
749 AU1000_GPIO_5,
750 AU1000_GPIO_6,
751 AU1000_GPIO_7,
752 AU1000_GPIO_8,
753 AU1000_GPIO_9,
754 AU1000_GPIO_10,
755 AU1000_GPIO_11,
756 AU1000_GPIO_12,
757 AU1000_GPIO_13,
758 AU1000_GPIO_14,
759 AU1000_GPIO_15,
760 AU1000_GPIO_16,
761 AU1000_GPIO_17,
762 AU1000_GPIO_18,
763 AU1000_GPIO_19,
764 AU1000_GPIO_20,
765 AU1000_GPIO_21,
766 AU1000_GPIO_22,
767 AU1000_GPIO_23,
768 AU1000_GPIO_24,
769 AU1000_GPIO_25,
770 AU1000_GPIO_26,
771 AU1000_GPIO_27,
772 AU1000_GPIO_28,
773 AU1000_GPIO_29,
774 AU1000_GPIO_30,
775 AU1000_GPIO_31,
776};
777 982
778#define UART0_ADDR 0xB1100000 983#define UART0_ADDR 0xB1100000
779#define UART1_ADDR 0xB1200000
780#define UART3_ADDR 0xB1400000 984#define UART3_ADDR 0xB1400000
781 985
782#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 986#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
783#define USB_HOST_CONFIG 0xB017FFFC 987#define USB_HOST_CONFIG 0xB017FFFC
988#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
784 989
785#define AU1100_ETH0_BASE 0xB0500000 990#define AU1100_ETH0_BASE 0xB0500000
786#define AU1100_MAC0_ENABLE 0xB0520000 991#define AU1100_MAC0_ENABLE 0xB0520000
@@ -788,87 +993,12 @@ enum soc_au1100_ints {
788#endif /* CONFIG_SOC_AU1100 */ 993#endif /* CONFIG_SOC_AU1100 */
789 994
790#ifdef CONFIG_SOC_AU1550 995#ifdef CONFIG_SOC_AU1550
791enum soc_au1550_ints {
792 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
793 AU1550_UART0_INT = AU1550_FIRST_INT,
794 AU1550_PCI_INTA,
795 AU1550_PCI_INTB,
796 AU1550_DDMA_INT,
797 AU1550_CRYPTO_INT,
798 AU1550_PCI_INTC,
799 AU1550_PCI_INTD,
800 AU1550_PCI_RST_INT,
801 AU1550_UART1_INT,
802 AU1550_UART3_INT,
803 AU1550_PSC0_INT,
804 AU1550_PSC1_INT,
805 AU1550_PSC2_INT,
806 AU1550_PSC3_INT,
807 AU1000_TOY_INT,
808 AU1000_TOY_MATCH0_INT,
809 AU1000_TOY_MATCH1_INT,
810 AU1000_TOY_MATCH2_INT,
811 AU1000_RTC_INT,
812 AU1000_RTC_MATCH0_INT,
813 AU1000_RTC_MATCH1_INT,
814 AU1000_RTC_MATCH2_INT,
815
816 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
817 AU1550_USB_DEV_REQ_INT,
818 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
819 AU1550_USB_DEV_SUS_INT,
820 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
821 AU1550_USB_HOST_INT,
822 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
823 AU1550_MAC0_DMA_INT,
824 AU1550_MAC1_DMA_INT,
825 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
826 AU1000_GPIO_1,
827 AU1000_GPIO_2,
828 AU1000_GPIO_3,
829 AU1000_GPIO_4,
830 AU1000_GPIO_5,
831 AU1000_GPIO_6,
832 AU1000_GPIO_7,
833 AU1000_GPIO_8,
834 AU1000_GPIO_9,
835 AU1000_GPIO_10,
836 AU1000_GPIO_11,
837 AU1000_GPIO_12,
838 AU1000_GPIO_13,
839 AU1000_GPIO_14,
840 AU1000_GPIO_15,
841 AU1550_GPIO_200,
842 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
843 AU1500_GPIO_16,
844 AU1500_GPIO_17,
845 AU1500_GPIO_20,
846 AU1500_GPIO_21,
847 AU1500_GPIO_22,
848 AU1500_GPIO_23,
849 AU1500_GPIO_24,
850 AU1500_GPIO_25,
851 AU1500_GPIO_26,
852 AU1500_GPIO_27,
853 AU1500_GPIO_28,
854 AU1500_GPIO_206,
855 AU1500_GPIO_207,
856 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
857};
858
859/* shortcuts */
860#define INTA AU1550_PCI_INTA
861#define INTB AU1550_PCI_INTB
862#define INTC AU1550_PCI_INTC
863#define INTD AU1550_PCI_INTD
864
865#define UART0_ADDR 0xB1100000 996#define UART0_ADDR 0xB1100000
866#define UART1_ADDR 0xB1200000
867#define UART3_ADDR 0xB1400000
868 997
869#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ 998#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
870#define USB_OHCI_LEN 0x00060000 999#define USB_OHCI_LEN 0x00060000
871#define USB_HOST_CONFIG 0xB4027ffc 1000#define USB_HOST_CONFIG 0xB4027ffc
1001#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
872 1002
873#define AU1550_ETH0_BASE 0xB0500000 1003#define AU1550_ETH0_BASE 0xB0500000
874#define AU1550_ETH1_BASE 0xB0510000 1004#define AU1550_ETH1_BASE 0xB0510000
@@ -877,78 +1007,10 @@ enum soc_au1550_ints {
877#define NUM_ETH_INTERFACES 2 1007#define NUM_ETH_INTERFACES 2
878#endif /* CONFIG_SOC_AU1550 */ 1008#endif /* CONFIG_SOC_AU1550 */
879 1009
1010
880#ifdef CONFIG_SOC_AU1200 1011#ifdef CONFIG_SOC_AU1200
881enum soc_au1200_ints {
882 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
883 AU1200_UART0_INT = AU1200_FIRST_INT,
884 AU1200_SWT_INT,
885 AU1200_SD_INT,
886 AU1200_DDMA_INT,
887 AU1200_MAE_BE_INT,
888 AU1200_GPIO_200,
889 AU1200_GPIO_201,
890 AU1200_GPIO_202,
891 AU1200_UART1_INT,
892 AU1200_MAE_FE_INT,
893 AU1200_PSC0_INT,
894 AU1200_PSC1_INT,
895 AU1200_AES_INT,
896 AU1200_CAMERA_INT,
897 AU1000_TOY_INT,
898 AU1000_TOY_MATCH0_INT,
899 AU1000_TOY_MATCH1_INT,
900 AU1000_TOY_MATCH2_INT,
901 AU1000_RTC_INT,
902 AU1000_RTC_MATCH0_INT,
903 AU1000_RTC_MATCH1_INT,
904 AU1000_RTC_MATCH2_INT,
905 AU1200_GPIO_203,
906 AU1200_NAND_INT,
907 AU1200_GPIO_204,
908 AU1200_GPIO_205,
909 AU1200_GPIO_206,
910 AU1200_GPIO_207,
911 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
912 AU1200_USB_INT,
913 AU1000_USB_HOST_INT = AU1200_USB_INT,
914 AU1200_LCD_INT,
915 AU1200_MAE_BOTH_INT,
916 AU1000_GPIO_0,
917 AU1000_GPIO_1,
918 AU1000_GPIO_2,
919 AU1000_GPIO_3,
920 AU1000_GPIO_4,
921 AU1000_GPIO_5,
922 AU1000_GPIO_6,
923 AU1000_GPIO_7,
924 AU1000_GPIO_8,
925 AU1000_GPIO_9,
926 AU1000_GPIO_10,
927 AU1000_GPIO_11,
928 AU1000_GPIO_12,
929 AU1000_GPIO_13,
930 AU1000_GPIO_14,
931 AU1000_GPIO_15,
932 AU1000_GPIO_16,
933 AU1000_GPIO_17,
934 AU1000_GPIO_18,
935 AU1000_GPIO_19,
936 AU1000_GPIO_20,
937 AU1000_GPIO_21,
938 AU1000_GPIO_22,
939 AU1000_GPIO_23,
940 AU1000_GPIO_24,
941 AU1000_GPIO_25,
942 AU1000_GPIO_26,
943 AU1000_GPIO_27,
944 AU1000_GPIO_28,
945 AU1000_GPIO_29,
946 AU1000_GPIO_30,
947 AU1000_GPIO_31,
948};
949 1012
950#define UART0_ADDR 0xB1100000 1013#define UART0_ADDR 0xB1100000
951#define UART1_ADDR 0xB1200000
952 1014
953#define USB_UOC_BASE 0x14020020 1015#define USB_UOC_BASE 0x14020020
954#define USB_UOC_LEN 0x20 1016#define USB_UOC_LEN 0x20
@@ -974,15 +1036,9 @@ enum soc_au1200_ints {
974#define USBMSRMCFG_RDCOMB 30 1036#define USBMSRMCFG_RDCOMB 30
975#define USBMSRMCFG_PFEN 31 1037#define USBMSRMCFG_PFEN 31
976 1038
977#endif /* CONFIG_SOC_AU1200 */ 1039#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
978 1040
979#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 1041#endif /* CONFIG_SOC_AU1200 */
980#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
981#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
982#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
983
984#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
985#define INTX 0xFF /* not valid */
986 1042
987/* Programmable Counters 0 and 1 */ 1043/* Programmable Counters 0 and 1 */
988#define SYS_BASE 0xB1900000 1044#define SYS_BASE 0xB1900000
@@ -1231,14 +1287,6 @@ enum soc_au1200_ints {
1231#define MAC_RX_BUFF3_STATUS 0x30 1287#define MAC_RX_BUFF3_STATUS 0x30
1232#define MAC_RX_BUFF3_ADDR 0x34 1288#define MAC_RX_BUFF3_ADDR 0x34
1233 1289
1234/* UARTS 0-3 */
1235#define UART_BASE UART0_ADDR
1236#ifdef CONFIG_SOC_AU1200
1237#define UART_DEBUG_BASE UART1_ADDR
1238#else
1239#define UART_DEBUG_BASE UART3_ADDR
1240#endif
1241
1242#define UART_RX 0 /* Receive buffer */ 1290#define UART_RX 0 /* Receive buffer */
1243#define UART_TX 4 /* Transmit buffer */ 1291#define UART_TX 4 /* Transmit buffer */
1244#define UART_IER 8 /* Interrupt Enable Register */ 1292#define UART_IER 8 /* Interrupt Enable Register */
@@ -1251,84 +1299,6 @@ enum soc_au1200_ints {
1251#define UART_CLK 0x28 /* Baud Rate Clock Divider */ 1299#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1252#define UART_MOD_CNTRL 0x100 /* Module Control */ 1300#define UART_MOD_CNTRL 0x100 /* Module Control */
1253 1301
1254#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1255#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1256#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1257#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1258#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1259#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1260#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1261#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1262#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1263#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1264#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1265#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1266#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1267
1268/*
1269 * These are the definitions for the Line Control Register
1270 */
1271#define UART_LCR_SBC 0x40 /* Set break control */
1272#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1273#define UART_LCR_EPAR 0x10 /* Even parity select */
1274#define UART_LCR_PARITY 0x08 /* Parity Enable */
1275#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1276#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1277#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1278#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1279#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1280
1281/*
1282 * These are the definitions for the Line Status Register
1283 */
1284#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1285#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1286#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1287#define UART_LSR_FE 0x08 /* Frame error indicator */
1288#define UART_LSR_PE 0x04 /* Parity error indicator */
1289#define UART_LSR_OE 0x02 /* Overrun error indicator */
1290#define UART_LSR_DR 0x01 /* Receiver data ready */
1291
1292/*
1293 * These are the definitions for the Interrupt Identification Register
1294 */
1295#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1296#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1297#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1298#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1299#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1300#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1301
1302/*
1303 * These are the definitions for the Interrupt Enable Register
1304 */
1305#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1306#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1307#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1308#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1309
1310/*
1311 * These are the definitions for the Modem Control Register
1312 */
1313#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1314#define UART_MCR_OUT2 0x08 /* Out2 complement */
1315#define UART_MCR_OUT1 0x04 /* Out1 complement */
1316#define UART_MCR_RTS 0x02 /* RTS complement */
1317#define UART_MCR_DTR 0x01 /* DTR complement */
1318
1319/*
1320 * These are the definitions for the Modem Status Register
1321 */
1322#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1323#define UART_MSR_RI 0x40 /* Ring Indicator */
1324#define UART_MSR_DSR 0x20 /* Data Set Ready */
1325#define UART_MSR_CTS 0x10 /* Clear to Send */
1326#define UART_MSR_DDCD 0x08 /* Delta DCD */
1327#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1328#define UART_MSR_DDSR 0x02 /* Delta DSR */
1329#define UART_MSR_DCTS 0x01 /* Delta CTS */
1330#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1331
1332/* SSIO */ 1302/* SSIO */
1333#define SSI0_STATUS 0xB1600000 1303#define SSI0_STATUS 0xB1600000
1334# define SSI_STATUS_BF (1 << 4) 1304# define SSI_STATUS_BF (1 << 4)
@@ -1720,7 +1690,7 @@ enum soc_au1200_ints {
1720#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1690#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1721#define IOPORT_RESOURCE_END 0xffffffff 1691#define IOPORT_RESOURCE_END 0xffffffff
1722#define IOMEM_RESOURCE_START 0x10000000 1692#define IOMEM_RESOURCE_START 0x10000000
1723#define IOMEM_RESOURCE_END 0xffffffff 1693#define IOMEM_RESOURCE_END 0xfffffffffULL
1724 1694
1725#else /* Au1000 and Au1100 and Au1200 */ 1695#else /* Au1000 and Au1100 and Au1200 */
1726 1696
@@ -1728,7 +1698,7 @@ enum soc_au1200_ints {
1728#define IOPORT_RESOURCE_START 0x10000000 1698#define IOPORT_RESOURCE_START 0x10000000
1729#define IOPORT_RESOURCE_END 0xffffffff 1699#define IOPORT_RESOURCE_END 0xffffffff
1730#define IOMEM_RESOURCE_START 0x10000000 1700#define IOMEM_RESOURCE_START 0x10000000
1731#define IOMEM_RESOURCE_END 0xffffffff 1701#define IOMEM_RESOURCE_END 0xfffffffffULL
1732 1702
1733#define PCI_IO_START 0 1703#define PCI_IO_START 0
1734#define PCI_IO_END 0 1704#define PCI_IO_END 0
@@ -1739,53 +1709,4 @@ enum soc_au1200_ints {
1739 1709
1740#endif 1710#endif
1741 1711
1742#ifndef _LANGUAGE_ASSEMBLY
1743typedef volatile struct {
1744 /* 0x0000 */ u32 toytrim;
1745 /* 0x0004 */ u32 toywrite;
1746 /* 0x0008 */ u32 toymatch0;
1747 /* 0x000C */ u32 toymatch1;
1748 /* 0x0010 */ u32 toymatch2;
1749 /* 0x0014 */ u32 cntrctrl;
1750 /* 0x0018 */ u32 scratch0;
1751 /* 0x001C */ u32 scratch1;
1752 /* 0x0020 */ u32 freqctrl0;
1753 /* 0x0024 */ u32 freqctrl1;
1754 /* 0x0028 */ u32 clksrc;
1755 /* 0x002C */ u32 pinfunc;
1756 /* 0x0030 */ u32 reserved0;
1757 /* 0x0034 */ u32 wakemsk;
1758 /* 0x0038 */ u32 endian;
1759 /* 0x003C */ u32 powerctrl;
1760 /* 0x0040 */ u32 toyread;
1761 /* 0x0044 */ u32 rtctrim;
1762 /* 0x0048 */ u32 rtcwrite;
1763 /* 0x004C */ u32 rtcmatch0;
1764 /* 0x0050 */ u32 rtcmatch1;
1765 /* 0x0054 */ u32 rtcmatch2;
1766 /* 0x0058 */ u32 rtcread;
1767 /* 0x005C */ u32 wakesrc;
1768 /* 0x0060 */ u32 cpupll;
1769 /* 0x0064 */ u32 auxpll;
1770 /* 0x0068 */ u32 reserved1;
1771 /* 0x006C */ u32 reserved2;
1772 /* 0x0070 */ u32 reserved3;
1773 /* 0x0074 */ u32 reserved4;
1774 /* 0x0078 */ u32 slppwr;
1775 /* 0x007C */ u32 sleep;
1776 /* 0x0080 */ u32 reserved5[32];
1777 /* 0x0100 */ u32 trioutrd;
1778#define trioutclr trioutrd
1779 /* 0x0104 */ u32 reserved6;
1780 /* 0x0108 */ u32 outputrd;
1781#define outputset outputrd
1782 /* 0x010C */ u32 outputclr;
1783 /* 0x0110 */ u32 pinstaterd;
1784#define pininputen pinstaterd
1785} AU1X00_SYS;
1786
1787static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1788
1789#endif
1790
1791#endif 1712#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 07:25:53 -0500