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Diffstat (limited to 'arch/mips/include/asm/cpu.h')
-rw-r--r--arch/mips/include/asm/cpu.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 15687234d70a..e3adca1d0b99 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -67,7 +67,7 @@
67#define PRID_IMP_R4300 0x0b00 67#define PRID_IMP_R4300 0x0b00
68#define PRID_IMP_VR41XX 0x0c00 68#define PRID_IMP_VR41XX 0x0c00
69#define PRID_IMP_R12000 0x0e00 69#define PRID_IMP_R12000 0x0e00
70#define PRID_IMP_R14000 0x0f00 70#define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
71#define PRID_IMP_R8000 0x1000 71#define PRID_IMP_R8000 0x1000
72#define PRID_IMP_PR4450 0x1200 72#define PRID_IMP_PR4450 0x1200
73#define PRID_IMP_R4600 0x2000 73#define PRID_IMP_R4600 0x2000
@@ -284,8 +284,8 @@ enum cpu_type_enum {
284 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 284 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
285 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 285 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
286 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, 286 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
287 CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122, 287 CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
288 CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 288 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
289 CPU_SR71000, CPU_TX49XX, 289 CPU_SR71000, CPU_TX49XX,
290 290
291 /* 291 /*
@@ -377,6 +377,8 @@ enum cpu_type_enum {
377#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */ 377#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
378#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */ 378#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
379#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */ 379#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */
380#define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */
381#define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */
380 382
381/* 383/*
382 * CPU ASE encodings 384 * CPU ASE encodings