1 files changed, 9 insertions, 2 deletions

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 33866fce4d63..15687234d70a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -93,6 +93,7 @@
  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
  */
 
+#define PRID_IMP_QEMU_GENERIC   0x0000
 #define PRID_IMP_4KC            0x8000
 #define PRID_IMP_5KC            0x8100
 #define PRID_IMP_20KC           0x8200
@@ -312,6 +313,8 @@ enum cpu_type_enum {
         CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
         CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
 
+        CPU_QEMU_GENERIC,
+
         CPU_LAST
 };
 
@@ -329,11 +332,14 @@ enum cpu_type_enum {
 #define MIPS_CPU_ISA_M32R2      0x00000020
 #define MIPS_CPU_ISA_M64R1      0x00000040
 #define MIPS_CPU_ISA_M64R2      0x00000080
+#define MIPS_CPU_ISA_M32R6      0x00000100
+#define MIPS_CPU_ISA_M64R6      0x00000200
 
 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
-        MIPS_CPU_ISA_M32R2)
+        MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
-        MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
+        MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
+        MIPS_CPU_ISA_M64R6)
 
 /*
  * CPU Option encodings
@@ -370,6 +376,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_RIXIEX         0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
 #define MIPS_CPU_MAAR           0x400000000ull /* MAAR(I) registers are present */
 #define MIPS_CPU_FRE            0x800000000ull /* FRE & UFE bits implemented */
+#define MIPS_CPU_RW_LLB         0x1000000000ull /* LLADDR/LLB writes are allowed */
 
 /*
  * CPU ASE encodings