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-rw-r--r--arch/mips/include/asm/cpu.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 229a786101d9..c018727c7ddc 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -33,6 +33,7 @@
33#define PRID_COMP_TOSHIBA 0x070000 33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000 34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000 35#define PRID_COMP_LEXRA 0x0b0000
36#define PRID_COMP_CAVIUM 0x0d0000
36 37
37 38
38/* 39/*
@@ -114,6 +115,18 @@
114#define PRID_IMP_BCM3302 0x9000 115#define PRID_IMP_BCM3302 0x9000
115 116
116/* 117/*
118 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
119 */
120
121#define PRID_IMP_CAVIUM_CN38XX 0x0000
122#define PRID_IMP_CAVIUM_CN31XX 0x0100
123#define PRID_IMP_CAVIUM_CN30XX 0x0200
124#define PRID_IMP_CAVIUM_CN58XX 0x0300
125#define PRID_IMP_CAVIUM_CN56XX 0x0400
126#define PRID_IMP_CAVIUM_CN50XX 0x0600
127#define PRID_IMP_CAVIUM_CN52XX 0x0700
128
129/*
117 * Definitions for 7:0 on legacy processors 130 * Definitions for 7:0 on legacy processors
118 */ 131 */
119 132
@@ -203,6 +216,7 @@ enum cpu_type_enum {
203 * MIPS64 class processors 216 * MIPS64 class processors
204 */ 217 */
205 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 218 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
219 CPU_CAVIUM_OCTEON,
206 220
207 CPU_LAST 221 CPU_LAST
208}; 222};