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-rw-r--r--arch/mips/gt64120/ev64120/irq.c40
1 files changed, 4 insertions, 36 deletions
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index ed4d82b9a24a..b3e5796c81d7 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -66,38 +66,21 @@ asmlinkage void plat_irq_dispatch(void)
66 66
67static void disable_ev64120_irq(unsigned int irq_nr) 67static void disable_ev64120_irq(unsigned int irq_nr)
68{ 68{
69 unsigned long flags;
70
71 local_irq_save(flags);
72 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 69 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
73 clear_c0_status(9 << 10); 70 clear_c0_status(9 << 10);
74 } else { 71 } else {
75 clear_c0_status(1 << (irq_nr + 8)); 72 clear_c0_status(1 << (irq_nr + 8));
76 } 73 }
77 local_irq_restore(flags);
78} 74}
79 75
80static void enable_ev64120_irq(unsigned int irq_nr) 76static void enable_ev64120_irq(unsigned int irq_nr)
81{ 77{
82 unsigned long flags;
83
84 local_irq_save(flags);
85 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2 78 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
86 set_c0_status(9 << 10); 79 set_c0_status(9 << 10);
87 else 80 else
88 set_c0_status(1 << (irq_nr + 8)); 81 set_c0_status(1 << (irq_nr + 8));
89 local_irq_restore(flags);
90}
91
92static unsigned int startup_ev64120_irq(unsigned int irq)
93{
94 enable_ev64120_irq(irq);
95 return 0; /* Never anything pending */
96} 82}
97 83
98#define shutdown_ev64120_irq disable_ev64120_irq
99#define mask_and_ack_ev64120_irq disable_ev64120_irq
100
101static void end_ev64120_irq(unsigned int irq) 84static void end_ev64120_irq(unsigned int irq)
102{ 85{
103 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 86 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -106,13 +89,11 @@ static void end_ev64120_irq(unsigned int irq)
106 89
107static struct irq_chip ev64120_irq_type = { 90static struct irq_chip ev64120_irq_type = {
108 .typename = "EV64120", 91 .typename = "EV64120",
109 .startup = startup_ev64120_irq, 92 .ack = disable_ev64120_irq,
110 .shutdown = shutdown_ev64120_irq, 93 .mask = disable_ev64120_irq,
111 .enable = enable_ev64120_irq, 94 .mask_ack = disable_ev64120_irq,
112 .disable = disable_ev64120_irq, 95 .unmask = enable_ev64120_irq,
113 .ack = mask_and_ack_ev64120_irq,
114 .end = end_ev64120_irq, 96 .end = end_ev64120_irq,
115 .set_affinity = NULL
116}; 97};
117 98
118void gt64120_irq_setup(void) 99void gt64120_irq_setup(void)
@@ -122,8 +103,6 @@ void gt64120_irq_setup(void)
122 */ 103 */
123 clear_c0_status(ST0_IM); 104 clear_c0_status(ST0_IM);
124 105
125 local_irq_disable();
126
127 /* 106 /*
128 * Enable timer. Other interrupts will be enabled as they are 107 * Enable timer. Other interrupts will be enabled as they are
129 * registered. 108 * registered.
@@ -133,16 +112,5 @@ void gt64120_irq_setup(void)
133 112
134void __init arch_init_irq(void) 113void __init arch_init_irq(void)
135{ 114{
136 int i;
137
138 /* Let's initialize our IRQ descriptors */
139 for (i = 0; i < NR_IRQS; i++) {
140 irq_desc[i].status = 0;
141 irq_desc[i].chip = &no_irq_chip;
142 irq_desc[i].action = NULL;
143 irq_desc[i].depth = 0;
144 spin_lock_init(&irq_desc[i].lock);
145 }
146
147 gt64120_irq_setup(); 115 gt64120_irq_setup();
148} 116}