diff options
Diffstat (limited to 'arch/mips/gt64120/wrppmc/irq.c')
-rw-r--r-- | arch/mips/gt64120/wrppmc/irq.c | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c new file mode 100644 index 000000000000..8605687e24ed --- /dev/null +++ b/arch/mips/gt64120/wrppmc/irq.c | |||
@@ -0,0 +1,63 @@ | |||
1 | /* | ||
2 | * irq.c: GT64120 Interrupt Controller | ||
3 | * | ||
4 | * Copyright (C) 2006, Wind River System Inc. | ||
5 | * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the | ||
9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
10 | * option) any later version. | ||
11 | */ | ||
12 | #include <linux/errno.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/kernel_stat.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/signal.h> | ||
17 | #include <linux/sched.h> | ||
18 | #include <linux/types.h> | ||
19 | #include <linux/interrupt.h> | ||
20 | #include <linux/ioport.h> | ||
21 | #include <linux/timex.h> | ||
22 | #include <linux/slab.h> | ||
23 | #include <linux/random.h> | ||
24 | #include <linux/bitops.h> | ||
25 | #include <asm/bootinfo.h> | ||
26 | #include <asm/io.h> | ||
27 | #include <asm/bitops.h> | ||
28 | #include <asm/mipsregs.h> | ||
29 | #include <asm/system.h> | ||
30 | #include <asm/irq_cpu.h> | ||
31 | #include <asm/gt64120.h> | ||
32 | |||
33 | extern asmlinkage void handle_IRQ(void); | ||
34 | |||
35 | /** | ||
36 | * Initialize GT64120 Interrupt Controller | ||
37 | */ | ||
38 | void gt64120_init_pic(void) | ||
39 | { | ||
40 | /* clear CPU Interrupt Cause Registers */ | ||
41 | GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21)); | ||
42 | GT_WRITE(GT_HINTRCAUSE_OFS, 0x00); | ||
43 | |||
44 | /* Disable all interrupts from GT64120 bridge chip */ | ||
45 | GT_WRITE(GT_INTRMASK_OFS, 0x00); | ||
46 | GT_WRITE(GT_HINTRMASK_OFS, 0x00); | ||
47 | GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00); | ||
48 | GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00); | ||
49 | } | ||
50 | |||
51 | void __init arch_init_irq(void) | ||
52 | { | ||
53 | /* enable all CPU interrupt bits. */ | ||
54 | set_c0_status(ST0_IM); /* IE bit is still 0 */ | ||
55 | |||
56 | /* Install MIPS Interrupt Trap Vector */ | ||
57 | set_except_vector(0, handle_IRQ); | ||
58 | |||
59 | /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ | ||
60 | mips_cpu_irq_init(0); | ||
61 | |||
62 | gt64120_init_pic(); | ||
63 | } | ||