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-rw-r--r--arch/mips/cobalt/setup.c97
1 files changed, 32 insertions, 65 deletions
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index a4b69b543bd9..d0dd81790f74 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -19,12 +19,10 @@
19#include <asm/bootinfo.h> 19#include <asm/bootinfo.h>
20#include <asm/time.h> 20#include <asm/time.h>
21#include <asm/io.h> 21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/processor.h>
24#include <asm/reboot.h> 22#include <asm/reboot.h>
25#include <asm/gt64120.h> 23#include <asm/gt64120.h>
26 24
27#include <asm/mach-cobalt/cobalt.h> 25#include <cobalt.h>
28 26
29extern void cobalt_machine_restart(char *command); 27extern void cobalt_machine_restart(char *command);
30extern void cobalt_machine_halt(void); 28extern void cobalt_machine_halt(void);
@@ -63,61 +61,38 @@ void __init plat_timer_setup(struct irqaction *irq)
63 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS)); 61 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
64} 62}
65 63
66extern struct pci_ops gt64111_pci_ops; 64/*
67 65 * Cobalt doesn't have PS/2 keyboard/mouse interfaces,
68static struct resource cobalt_mem_resource = { 66 * keyboard conntroller is never used.
69 .start = GT_DEF_PCI0_MEM0_BASE, 67 * Also PCI-ISA bridge DMA contoroller is never used.
70 .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1, 68 */
71 .name = "PCI memory", 69static struct resource cobalt_reserved_resources[] = {
72 .flags = IORESOURCE_MEM 70 { /* dma1 */
73};
74
75static struct resource cobalt_io_resource = {
76 .start = 0x1000,
77 .end = 0xffff,
78 .name = "PCI I/O",
79 .flags = IORESOURCE_IO
80};
81
82static struct resource cobalt_io_resources[] = {
83 {
84 .start = 0x00, 71 .start = 0x00,
85 .end = 0x1f, 72 .end = 0x1f,
86 .name = "dma1", 73 .name = "reserved",
87 .flags = IORESOURCE_BUSY 74 .flags = IORESOURCE_BUSY | IORESOURCE_IO,
88 }, { 75 },
89 .start = 0x40, 76 { /* keyboard */
90 .end = 0x5f,
91 .name = "timer",
92 .flags = IORESOURCE_BUSY
93 }, {
94 .start = 0x60, 77 .start = 0x60,
95 .end = 0x6f, 78 .end = 0x6f,
96 .name = "keyboard", 79 .name = "reserved",
97 .flags = IORESOURCE_BUSY 80 .flags = IORESOURCE_BUSY | IORESOURCE_IO,
98 }, { 81 },
82 { /* dma page reg */
99 .start = 0x80, 83 .start = 0x80,
100 .end = 0x8f, 84 .end = 0x8f,
101 .name = "dma page reg", 85 .name = "reserved",
102 .flags = IORESOURCE_BUSY 86 .flags = IORESOURCE_BUSY | IORESOURCE_IO,
103 }, { 87 },
88 { /* dma2 */
104 .start = 0xc0, 89 .start = 0xc0,
105 .end = 0xdf, 90 .end = 0xdf,
106 .name = "dma2", 91 .name = "reserved",
107 .flags = IORESOURCE_BUSY 92 .flags = IORESOURCE_BUSY | IORESOURCE_IO,
108 }, 93 },
109}; 94};
110 95
111#define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource))
112
113static struct pci_controller cobalt_pci_controller = {
114 .pci_ops = &gt64111_pci_ops,
115 .mem_resource = &cobalt_mem_resource,
116 .mem_offset = 0,
117 .io_resource = &cobalt_io_resource,
118 .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
119};
120
121void __init plat_mem_setup(void) 96void __init plat_mem_setup(void)
122{ 97{
123 static struct uart_port uart; 98 static struct uart_port uart;
@@ -130,12 +105,12 @@ void __init plat_mem_setup(void)
130 105
131 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); 106 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
132 107
133 /* I/O port resource must include UART and LCD/buttons */ 108 /* I/O port resource must include LCD/buttons */
134 ioport_resource.end = 0x0fffffff; 109 ioport_resource.end = 0x0fffffff;
135 110
136 /* request I/O space for devices used on all i[345]86 PCs */ 111 /* These resources have been reserved by VIA SuperI/O chip. */
137 for (i = 0; i < COBALT_IO_RESOURCES; i++) 112 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
138 request_resource(&ioport_resource, cobalt_io_resources + i); 113 request_resource(&ioport_resource, cobalt_reserved_resources + i);
139 114
140 /* Read the cobalt id register out of the PCI config space */ 115 /* Read the cobalt id register out of the PCI config space */
141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 116 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
@@ -145,28 +120,20 @@ void __init plat_mem_setup(void)
145 120
146 printk("Cobalt board ID: %d\n", cobalt_board_id); 121 printk("Cobalt board ID: %d\n", cobalt_board_id);
147 122
148#ifdef CONFIG_PCI
149 register_pci_controller(&cobalt_pci_controller);
150#endif
151
152#ifdef CONFIG_SERIAL_8250
153 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { 123 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
154 124#ifdef CONFIG_SERIAL_8250
155#ifdef CONFIG_EARLY_PRINTK
156 cobalt_early_console();
157#endif
158
159 uart.line = 0; 125 uart.line = 0;
160 uart.type = PORT_UNKNOWN; 126 uart.type = PORT_UNKNOWN;
161 uart.uartclk = 18432000; 127 uart.uartclk = 18432000;
162 uart.irq = COBALT_SERIAL_IRQ; 128 uart.irq = COBALT_SERIAL_IRQ;
163 uart.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; 129 uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF |
164 uart.iobase = 0xc800000; 130 UPF_SKIP_TEST;
165 uart.iotype = UPIO_PORT; 131 uart.iotype = UPIO_MEM;
132 uart.mapbase = 0x1c800000;
166 133
167 early_serial_setup(&uart); 134 early_serial_setup(&uart);
168 }
169#endif 135#endif
136 }
170} 137}
171 138
172/* 139/*