diff options
Diffstat (limited to 'arch/mips/cobalt/irq.c')
-rw-r--r-- | arch/mips/cobalt/irq.c | 52 |
1 files changed, 19 insertions, 33 deletions
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index 0b75f4fb7195..82e569d5b02c 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c | |||
@@ -16,7 +16,6 @@ | |||
16 | #include <asm/i8259.h> | 16 | #include <asm/i8259.h> |
17 | #include <asm/irq_cpu.h> | 17 | #include <asm/irq_cpu.h> |
18 | #include <asm/gt64120.h> | 18 | #include <asm/gt64120.h> |
19 | #include <asm/ptrace.h> | ||
20 | 19 | ||
21 | #include <asm/mach-cobalt/cobalt.h> | 20 | #include <asm/mach-cobalt/cobalt.h> |
22 | 21 | ||
@@ -42,7 +41,7 @@ | |||
42 | * 15 - IDE1 | 41 | * 15 - IDE1 |
43 | */ | 42 | */ |
44 | 43 | ||
45 | static inline void galileo_irq(struct pt_regs *regs) | 44 | static inline void galileo_irq(void) |
46 | { | 45 | { |
47 | unsigned int mask, pending, devfn; | 46 | unsigned int mask, pending, devfn; |
48 | 47 | ||
@@ -52,7 +51,7 @@ static inline void galileo_irq(struct pt_regs *regs) | |||
52 | if (pending & GALILEO_INTR_T0EXP) { | 51 | if (pending & GALILEO_INTR_T0EXP) { |
53 | 52 | ||
54 | GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS); | 53 | GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS); |
55 | do_IRQ(COBALT_GALILEO_IRQ, regs); | 54 | do_IRQ(COBALT_GALILEO_IRQ); |
56 | 55 | ||
57 | } else if (pending & GALILEO_INTR_RETRY_CTR) { | 56 | } else if (pending & GALILEO_INTR_RETRY_CTR) { |
58 | 57 | ||
@@ -68,44 +67,31 @@ static inline void galileo_irq(struct pt_regs *regs) | |||
68 | } | 67 | } |
69 | } | 68 | } |
70 | 69 | ||
71 | static inline void via_pic_irq(struct pt_regs *regs) | 70 | static inline void via_pic_irq(void) |
72 | { | 71 | { |
73 | int irq; | 72 | int irq; |
74 | 73 | ||
75 | irq = i8259_irq(); | 74 | irq = i8259_irq(); |
76 | if (irq >= 0) | 75 | if (irq >= 0) |
77 | do_IRQ(irq, regs); | 76 | do_IRQ(irq); |
78 | } | 77 | } |
79 | 78 | ||
80 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) | 79 | asmlinkage void plat_irq_dispatch(void) |
81 | { | 80 | { |
82 | unsigned pending; | 81 | unsigned pending = read_c0_status() & read_c0_cause(); |
83 | 82 | ||
84 | pending = read_c0_status() & read_c0_cause(); | 83 | if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ |
85 | 84 | galileo_irq(); | |
86 | if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ | 85 | else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ |
87 | 86 | via_pic_irq(); | |
88 | galileo_irq(regs); | 87 | else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ |
89 | 88 | do_IRQ(COBALT_CPU_IRQ + 3); | |
90 | else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ | 89 | else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ |
91 | 90 | do_IRQ(COBALT_CPU_IRQ + 4); | |
92 | via_pic_irq(regs); | 91 | else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ |
93 | 92 | do_IRQ(COBALT_CPU_IRQ + 5); | |
94 | else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ | 93 | else if (pending & CAUSEF_IP7) /* IRQ 23 */ |
95 | 94 | do_IRQ(COBALT_CPU_IRQ + 7); | |
96 | do_IRQ(COBALT_CPU_IRQ + 3, regs); | ||
97 | |||
98 | else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ | ||
99 | |||
100 | do_IRQ(COBALT_CPU_IRQ + 4, regs); | ||
101 | |||
102 | else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ | ||
103 | |||
104 | do_IRQ(COBALT_CPU_IRQ + 5, regs); | ||
105 | |||
106 | else if (pending & CAUSEF_IP7) /* IRQ 23 */ | ||
107 | |||
108 | do_IRQ(COBALT_CPU_IRQ + 7, regs); | ||
109 | } | 95 | } |
110 | 96 | ||
111 | static struct irqaction irq_via = { | 97 | static struct irqaction irq_via = { |