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-rw-r--r--arch/mips/cavium-octeon/smp.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index c198efdf583e..6d99b9d8887d 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -279,14 +279,6 @@ static void octeon_cpu_die(unsigned int cpu)
279 uint32_t avail_coremask; 279 uint32_t avail_coremask;
280 struct cvmx_bootmem_named_block_desc *block_desc; 280 struct cvmx_bootmem_named_block_desc *block_desc;
281 281
282#ifdef CONFIG_CAVIUM_OCTEON_WATCHDOG
283 /* Disable the watchdog */
284 cvmx_ciu_wdogx_t ciu_wdog;
285 ciu_wdog.u64 = cvmx_read_csr(CVMX_CIU_WDOGX(cpu));
286 ciu_wdog.s.mode = 0;
287 cvmx_write_csr(CVMX_CIU_WDOGX(cpu), ciu_wdog.u64);
288#endif
289
290 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 282 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
291 cpu_relax(); 283 cpu_relax();
292 284
@@ -327,7 +319,7 @@ static void octeon_cpu_die(unsigned int cpu)
327 avail_coremask); 319 avail_coremask);
328 } 320 }
329 321
330 pr_info("Reset core %d. Available Coremask = %x \n", coreid, 322 pr_info("Reset core %d. Available Coremask = %x\n", coreid,
331 avail_coremask); 323 avail_coremask);
332 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 324 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
333 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 325 cvmx_write_csr(CVMX_CIU_PP_RST, 0);