10 files changed, 204 insertions, 80 deletions

diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index d03e8799d1cf..5639662fd503 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -25,6 +25,10 @@ config BCM63XX_CPU_6358
         bool "support 6358 CPU"
         select HW_HAS_PCI
 
+config BCM63XX_CPU_6362
+        bool "support 6362 CPU"
+        select HW_HAS_PCI
+
 config BCM63XX_CPU_6368
         bool "support 6368 CPU"
         select HW_HAS_PCI
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 9aa7d44898ed..a9505c4867e8 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -726,11 +726,11 @@ void __init board_prom_init(void)
         u32 val;
 
         /* read base address of boot chip select (0)
-         * 6328 does not have MPI but boots from a fixed address
+         * 6328/6362 do not have MPI but boot from a fixed address
          */
-        if (BCMCPU_IS_6328())
+        if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
                 val = 0x18000000;
-        else {
+        } else {
                 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
                 val &= MPI_CSBASE_BASE_MASK;
         }
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index b9e948d59430..c726a97fc798 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -15,7 +15,13 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
 #include <bcm63xx_reset.h>
-#include <bcm63xx_clk.h>
+
+struct clk {
+        void            (*set)(struct clk *, int);
+        unsigned int    rate;
+        unsigned int    usage;
+        int             id;
+};
 
 static DEFINE_MUTEX(clocks_mutex);
 
@@ -119,11 +125,18 @@ static struct clk clk_ephy = {
  */
 static void enetsw_set(struct clk *clk, int enable)
 {
-        if (!BCMCPU_IS_6368())
+        if (BCMCPU_IS_6328())
+                bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
+        else if (BCMCPU_IS_6362())
+                bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
+        else if (BCMCPU_IS_6368())
+                bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
+                                CKCTL_6368_SWPKT_USB_EN |
+                                CKCTL_6368_SWPKT_SAR_EN,
+                                enable);
+        else
                 return;
-        bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
-                        CKCTL_6368_SWPKT_USB_EN |
-                        CKCTL_6368_SWPKT_SAR_EN, enable);
+
         if (enable) {
                 /* reset switch core afer clock change */
                 bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
@@ -160,6 +173,8 @@ static void usbh_set(struct clk *clk, int enable)
                 bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
         else if (BCMCPU_IS_6348())
                 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+        else if (BCMCPU_IS_6362())
+                bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
         else if (BCMCPU_IS_6368())
                 bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
 }
@@ -175,6 +190,8 @@ static void usbd_set(struct clk *clk, int enable)
 {
         if (BCMCPU_IS_6328())
                 bcm_hwclock_set(CKCTL_6328_USBD_EN, enable);
+        else if (BCMCPU_IS_6362())
+                bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
         else if (BCMCPU_IS_6368())
                 bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
 }
@@ -196,6 +213,8 @@ static void spi_set(struct clk *clk, int enable)
                 mask = CKCTL_6348_SPI_EN;
         else if (BCMCPU_IS_6358())
                 mask = CKCTL_6358_SPI_EN;
+        else if (BCMCPU_IS_6362())
+                mask = CKCTL_6362_SPI_EN;
         else
                 /* BCMCPU_IS_6368 */
                 mask = CKCTL_6368_SPI_EN;
@@ -236,7 +255,10 @@ static struct clk clk_xtm = {
  */
 static void ipsec_set(struct clk *clk, int enable)
 {
-        bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
+        if (BCMCPU_IS_6362())
+                bcm_hwclock_set(CKCTL_6362_IPSEC_EN, enable);
+        else if (BCMCPU_IS_6368())
+                bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
 }
 
 static struct clk clk_ipsec = {
@@ -249,7 +271,10 @@ static struct clk clk_ipsec = {
 
 static void pcie_set(struct clk *clk, int enable)
 {
-        bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
+        if (BCMCPU_IS_6328())
+                bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
+        else if (BCMCPU_IS_6362())
+                bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
 }
 
 static struct clk clk_pcie = {
@@ -315,9 +340,9 @@ struct clk *clk_get(struct device *dev, const char *id)
                 return &clk_periph;
         if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
                 return &clk_pcm;
-        if (BCMCPU_IS_6368() && !strcmp(id, "ipsec"))
+        if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
                 return &clk_ipsec;
-        if (BCMCPU_IS_6328() && !strcmp(id, "pcie"))
+        if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
                 return &clk_pcie;
         return ERR_PTR(-ENOENT);
 }
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index a7afb289b15a..79fe32df5e96 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -25,7 +25,7 @@ const int *bcm63xx_irqs;
 EXPORT_SYMBOL(bcm63xx_irqs);
 
 static u16 bcm63xx_cpu_id;
-static u16 bcm63xx_cpu_rev;
+static u8 bcm63xx_cpu_rev;
 static unsigned int bcm63xx_cpu_freq;
 static unsigned int bcm63xx_memory_size;
 
@@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = {
 
 };
 
+static const unsigned long bcm6362_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6362)
+};
+
+static const int bcm6362_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6362)
+
+};
+
 static const unsigned long bcm6368_regs_base[] = {
         __GEN_CPU_REGS_TABLE(6368)
 };
@@ -87,7 +96,7 @@ u16 __bcm63xx_get_cpu_id(void)
 
 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
 
-u16 bcm63xx_get_cpu_rev(void)
+u8 bcm63xx_get_cpu_rev(void)
 {
         return bcm63xx_cpu_rev;
 }
@@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(void)
                 return (16 * 1000000 * n1 * n2) / m1;
         }
 
+        case BCM6362_CPU_ID:
+        {
+                unsigned int tmp, mips_pll_fcvo;
+
+                tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
+                mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
+                                >> STRAPBUS_6362_FCVO_SHIFT;
+                switch (mips_pll_fcvo) {
+                case 0x03:
+                case 0x0b:
+                case 0x13:
+                case 0x1b:
+                        return 240000000;
+                case 0x04:
+                case 0x0c:
+                case 0x14:
+                case 0x1c:
+                        return 160000000;
+                case 0x05:
+                case 0x0e:
+                case 0x16:
+                case 0x1e:
+                case 0x1f:
+                        return 400000000;
+                case 0x06:
+                        return 440000000;
+                case 0x07:
+                case 0x17:
+                        return 384000000;
+                case 0x15:
+                case 0x1d:
+                        return 200000000;
+                default:
+                        return 320000000;
+                }
+        }
         case BCM6368_CPU_ID:
         {
                 unsigned int tmp, p1, p2, ndiv, m1;
@@ -205,7 +250,7 @@ static unsigned int detect_memory_size(void)
         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
         u32 val;
 
-        if (BCMCPU_IS_6328())
+        if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
                 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
 
         if (BCMCPU_IS_6345()) {
@@ -240,53 +285,27 @@ static unsigned int detect_memory_size(void)
 
 void __init bcm63xx_cpu_init(void)
 {
-        unsigned int tmp, expected_cpu_id;
+        unsigned int tmp;
         struct cpuinfo_mips *c = &current_cpu_data;
         unsigned int cpu = smp_processor_id();
+        u32 chipid_reg;
 
         /* soc registers location depends on cpu type */
-        expected_cpu_id = 0;
+        chipid_reg = 0;
 
         switch (c->cputype) {
         case CPU_BMIPS3300:
-                if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
-                        expected_cpu_id = BCM6348_CPU_ID;
-                        bcm63xx_regs_base = bcm6348_regs_base;
-                        bcm63xx_irqs = bcm6348_irqs;
-                } else {
+                if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)
                         __cpu_name[cpu] = "Broadcom BCM6338";
-                        expected_cpu_id = BCM6338_CPU_ID;
-                        bcm63xx_regs_base = bcm6338_regs_base;
-                        bcm63xx_irqs = bcm6338_irqs;
-                }
-                break;
+                /* fall-through */
         case CPU_BMIPS32:
-                expected_cpu_id = BCM6345_CPU_ID;
-                bcm63xx_regs_base = bcm6345_regs_base;
-                bcm63xx_irqs = bcm6345_irqs;
+                chipid_reg = BCM_6345_PERF_BASE;
                 break;
         case CPU_BMIPS4350:
-                if ((read_c0_prid() & 0xf0) == 0x10) {
-                        expected_cpu_id = BCM6358_CPU_ID;
-                        bcm63xx_regs_base = bcm6358_regs_base;
-                        bcm63xx_irqs = bcm6358_irqs;
-                } else {
-                        /* all newer chips have the same chip id location */
-                        u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
-
-                        switch (chip_id) {
-                        case BCM6328_CPU_ID:
-                                expected_cpu_id = BCM6328_CPU_ID;
-                                bcm63xx_regs_base = bcm6328_regs_base;
-                                bcm63xx_irqs = bcm6328_irqs;
-                                break;
-                        case BCM6368_CPU_ID:
-                                expected_cpu_id = BCM6368_CPU_ID;
-                                bcm63xx_regs_base = bcm6368_regs_base;
-                                bcm63xx_irqs = bcm6368_irqs;
-                                break;
-                        }
-                }
+                if ((read_c0_prid() & 0xf0) == 0x10)
+                        chipid_reg = BCM_6345_PERF_BASE;
+                else
+                        chipid_reg = BCM_6368_PERF_BASE;
                 break;
         }
 
@@ -294,20 +313,47 @@ void __init bcm63xx_cpu_init(void)
          * really early to panic, but delaying panic would not help since we
          * will never get any working console
          */
-        if (!expected_cpu_id)
+        if (!chipid_reg)
                 panic("unsupported Broadcom CPU");
 
-        /*
-         * bcm63xx_regs_base is set, we can access soc registers
-         */
-
-        /* double check CPU type */
-        tmp = bcm_perf_readl(PERF_REV_REG);
+        /* read out CPU type */
+        tmp = bcm_readl(chipid_reg);
         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 
-        if (bcm63xx_cpu_id != expected_cpu_id)
-                panic("bcm63xx CPU id mismatch");
+        switch (bcm63xx_cpu_id) {
+        case BCM6328_CPU_ID:
+                bcm63xx_regs_base = bcm6328_regs_base;
+                bcm63xx_irqs = bcm6328_irqs;
+                break;
+        case BCM6338_CPU_ID:
+                bcm63xx_regs_base = bcm6338_regs_base;
+                bcm63xx_irqs = bcm6338_irqs;
+                break;
+        case BCM6345_CPU_ID:
+                bcm63xx_regs_base = bcm6345_regs_base;
+                bcm63xx_irqs = bcm6345_irqs;
+                break;
+        case BCM6348_CPU_ID:
+                bcm63xx_regs_base = bcm6348_regs_base;
+                bcm63xx_irqs = bcm6348_irqs;
+                break;
+        case BCM6358_CPU_ID:
+                bcm63xx_regs_base = bcm6358_regs_base;
+                bcm63xx_irqs = bcm6358_irqs;
+                break;
+        case BCM6362_CPU_ID:
+                bcm63xx_regs_base = bcm6362_regs_base;
+                bcm63xx_irqs = bcm6362_irqs;
+                break;
+        case BCM6368_CPU_ID:
+                bcm63xx_regs_base = bcm6368_regs_base;
+                bcm63xx_irqs = bcm6368_irqs;
+                break;
+        default:
+                panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
+                break;
+        }
 
         bcm63xx_cpu_freq = detect_cpu_clock();
         bcm63xx_memory_size = detect_memory_size();
diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c
index 58371c7deac2..588d1ec622e4 100644
--- a/arch/mips/bcm63xx/dev-flash.c
+++ b/arch/mips/bcm63xx/dev-flash.c
@@ -77,6 +77,12 @@ static int __init bcm63xx_detect_flash_type(void)
                         return BCM63XX_FLASH_TYPE_PARALLEL;
                 else
                         return BCM63XX_FLASH_TYPE_SERIAL;
+        case BCM6362_CPU_ID:
+                val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
+                if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
+                        return BCM63XX_FLASH_TYPE_SERIAL;
+                else
+                        return BCM63XX_FLASH_TYPE_NAND;
         case BCM6368_CPU_ID:
                 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
                 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
index e97fd60e92ef..3065bb61820d 100644
--- a/arch/mips/bcm63xx/dev-spi.c
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -22,10 +22,6 @@
 /*
  * register offsets
  */
-static const unsigned long bcm6338_regs_spi[] = {
-        __GEN_SPI_REGS_TABLE(6338)
-};
-
 static const unsigned long bcm6348_regs_spi[] = {
         __GEN_SPI_REGS_TABLE(6348)
 };
@@ -34,23 +30,15 @@ static const unsigned long bcm6358_regs_spi[] = {
         __GEN_SPI_REGS_TABLE(6358)
 };
 
-static const unsigned long bcm6368_regs_spi[] = {
-        __GEN_SPI_REGS_TABLE(6368)
-};
-
 const unsigned long *bcm63xx_regs_spi;
 EXPORT_SYMBOL(bcm63xx_regs_spi);
 
 static __init void bcm63xx_spi_regs_init(void)
 {
-        if (BCMCPU_IS_6338())
-                bcm63xx_regs_spi = bcm6338_regs_spi;
-        if (BCMCPU_IS_6348())
+        if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
                 bcm63xx_regs_spi = bcm6348_regs_spi;
-        if (BCMCPU_IS_6358())
+        if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
                 bcm63xx_regs_spi = bcm6358_regs_spi;
-        if (BCMCPU_IS_6368())
-                bcm63xx_regs_spi = bcm6368_regs_spi;
 }
 #else
 static __init void bcm63xx_spi_regs_init(void) { }
@@ -93,13 +81,13 @@ int __init bcm63xx_spi_register(void)
         spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
 
         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
-                spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
-                spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
-                spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT;
-                spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
+                spi_resources[0].end += BCM_6348_RSET_SPI_SIZE - 1;
+                spi_pdata.fifo_size = SPI_6348_MSG_DATA_SIZE;
+                spi_pdata.msg_type_shift = SPI_6348_MSG_TYPE_SHIFT;
+                spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
         }
 
-        if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+        if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
                 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
                 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
                 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index da24c2bd9b7c..c0ab3887f42e 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -82,6 +82,17 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
 #define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6358
 #define ext_irq_cfg_reg2        0
 #endif
+#ifdef CONFIG_BCM63XX_CPU_6362
+#define irq_stat_reg            PERF_IRQSTAT_6362_REG
+#define irq_mask_reg            PERF_IRQMASK_6362_REG
+#define irq_bits                64
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6362
+#define ext_irq_cfg_reg2        0
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6368
 #define irq_stat_reg            PERF_IRQSTAT_6368_REG
 #define irq_mask_reg            PERF_IRQMASK_6368_REG
@@ -170,6 +181,16 @@ static void bcm63xx_init_irq(void)
                 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
                 break;
+        case BCM6362_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6362_REG;
+                irq_mask_addr += PERF_IRQMASK_6362_REG;
+                irq_bits = 64;
+                ext_irq_count = 4;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
+                break;
         case BCM6368_CPU_ID:
                 irq_stat_addr += PERF_IRQSTAT_6368_REG;
                 irq_mask_addr += PERF_IRQMASK_6368_REG;
@@ -458,6 +479,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
         case BCM6338_CPU_ID:
         case BCM6345_CPU_ID:
         case BCM6358_CPU_ID:
+        case BCM6362_CPU_ID:
         case BCM6368_CPU_ID:
                 if (levelsense)
                         reg |= EXTIRQ_CFG_LEVELSENSE(irq);
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 10eaff458071..fd698087fbfd 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -36,6 +36,8 @@ void __init prom_init(void)
                 mask = CKCTL_6348_ALL_SAFE_EN;
         else if (BCMCPU_IS_6358())
                 mask = CKCTL_6358_ALL_SAFE_EN;
+        else if (BCMCPU_IS_6362())
+                mask = CKCTL_6362_ALL_SAFE_EN;
         else if (BCMCPU_IS_6368())
                 mask = CKCTL_6368_ALL_SAFE_EN;
         else
diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c
index 68a31bb90cbf..317931c6cf58 100644
--- a/arch/mips/bcm63xx/reset.c
+++ b/arch/mips/bcm63xx/reset.c
@@ -85,6 +85,20 @@
 #define BCM6358_RESET_PCIE      0
 #define BCM6358_RESET_PCIE_EXT  0
 
+#define BCM6362_RESET_SPI       SOFTRESET_6362_SPI_MASK
+#define BCM6362_RESET_ENET      0
+#define BCM6362_RESET_USBH      SOFTRESET_6362_USBH_MASK
+#define BCM6362_RESET_USBD      SOFTRESET_6362_USBS_MASK
+#define BCM6362_RESET_DSL       0
+#define BCM6362_RESET_SAR       SOFTRESET_6362_SAR_MASK
+#define BCM6362_RESET_EPHY      SOFTRESET_6362_EPHY_MASK
+#define BCM6362_RESET_ENETSW    SOFTRESET_6362_ENETSW_MASK
+#define BCM6362_RESET_PCM       SOFTRESET_6362_PCM_MASK
+#define BCM6362_RESET_MPI       0
+#define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \
+                                 SOFTRESET_6362_PCIE_CORE_MASK)
+#define BCM6362_RESET_PCIE_EXT  SOFTRESET_6362_PCIE_EXT_MASK
+
 #define BCM6368_RESET_SPI       SOFTRESET_6368_SPI_MASK
 #define BCM6368_RESET_ENET      0
 #define BCM6368_RESET_USBH      SOFTRESET_6368_USBH_MASK
@@ -119,6 +133,10 @@ static const u32 bcm6358_reset_bits[] = {
         __GEN_RESET_BITS_TABLE(6358)
 };
 
+static const u32 bcm6362_reset_bits[] = {
+        __GEN_RESET_BITS_TABLE(6362)
+};
+
 static const u32 bcm6368_reset_bits[] = {
         __GEN_RESET_BITS_TABLE(6368)
 };
@@ -140,6 +158,9 @@ static int __init bcm63xx_reset_bits_init(void)
         } else if (BCMCPU_IS_6358()) {
                 reset_reg = PERF_SOFTRESET_6358_REG;
                 bcm63xx_reset_bits = bcm6358_reset_bits;
+        } else if (BCMCPU_IS_6362()) {
+                reset_reg = PERF_SOFTRESET_6362_REG;
+                bcm63xx_reset_bits = bcm6362_reset_bits;
         } else if (BCMCPU_IS_6368()) {
                 reset_reg = PERF_SOFTRESET_6368_REG;
                 bcm63xx_reset_bits = bcm6368_reset_bits;
@@ -182,6 +203,13 @@ static const u32 bcm63xx_reset_bits[] = {
 #define reset_reg PERF_SOFTRESET_6358_REG
 #endif
 
+#ifdef CONFIG_BCM63XX_CPU_6362
+static const u32 bcm63xx_reset_bits[] = {
+        __GEN_RESET_BITS_TABLE(6362)
+};
+#define reset_reg PERF_SOFTRESET_6362_REG
+#endif
+
 #ifdef CONFIG_BCM63XX_CPU_6368
 static const u32 bcm63xx_reset_bits[] = {
         __GEN_RESET_BITS_TABLE(6368)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 35e18e98beb9..24a24445db64 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void)
         case BCM6358_CPU_ID:
                 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
                 break;
+        case BCM6362_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
+                break;
         }
 
         for (i = 0; i < 2; i++) {
@@ -126,7 +129,7 @@ static void __bcm63xx_machine_reboot(char *p)
 const char *get_system_type(void)
 {
         static char buf[128];
-        snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)",
+        snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%02X)",
                  board_get_name(),
                  bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
         return buf;