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-rw-r--r--arch/mips/basler/excite/excite_device.c16
-rw-r--r--arch/mips/basler/excite/excite_fpga.h80
2 files changed, 8 insertions, 88 deletions
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
index bbb4ea43da88..cc1ce77eab4a 100644
--- a/arch/mips/basler/excite/excite_device.c
+++ b/arch/mips/basler/excite/excite_device.c
@@ -68,7 +68,7 @@ enum {
68 68
69 69
70static struct resource 70static struct resource
71 excite_ctr_resource = { 71 excite_ctr_resource __attribute__((unused)) = {
72 .name = "GPI counters", 72 .name = "GPI counters",
73 .start = 0, 73 .start = 0,
74 .end = 5, 74 .end = 5,
@@ -77,7 +77,7 @@ static struct resource
77 .sibling = NULL, 77 .sibling = NULL,
78 .child = NULL 78 .child = NULL
79 }, 79 },
80 excite_gpislice_resource = { 80 excite_gpislice_resource __attribute__((unused)) = {
81 .name = "GPI slices", 81 .name = "GPI slices",
82 .start = 0, 82 .start = 0,
83 .end = 1, 83 .end = 1,
@@ -86,7 +86,7 @@ static struct resource
86 .sibling = NULL, 86 .sibling = NULL,
87 .child = NULL 87 .child = NULL
88 }, 88 },
89 excite_mdio_channel_resource = { 89 excite_mdio_channel_resource __attribute__((unused)) = {
90 .name = "MDIO channels", 90 .name = "MDIO channels",
91 .start = 0, 91 .start = 0,
92 .end = 1, 92 .end = 1,
@@ -95,7 +95,7 @@ static struct resource
95 .sibling = NULL, 95 .sibling = NULL,
96 .child = NULL 96 .child = NULL
97 }, 97 },
98 excite_fifomem_resource = { 98 excite_fifomem_resource __attribute__((unused)) = {
99 .name = "FIFO memory", 99 .name = "FIFO memory",
100 .start = 0, 100 .start = 0,
101 .end = 767, 101 .end = 767,
@@ -104,7 +104,7 @@ static struct resource
104 .sibling = NULL, 104 .sibling = NULL,
105 .child = NULL 105 .child = NULL
106 }, 106 },
107 excite_scram_resource = { 107 excite_scram_resource __attribute__((unused)) = {
108 .name = "Scratch RAM", 108 .name = "Scratch RAM",
109 .start = EXCITE_PHYS_SCRAM, 109 .start = EXCITE_PHYS_SCRAM,
110 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1, 110 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
@@ -113,7 +113,7 @@ static struct resource
113 .sibling = NULL, 113 .sibling = NULL,
114 .child = NULL 114 .child = NULL
115 }, 115 },
116 excite_fpga_resource = { 116 excite_fpga_resource __attribute__((unused)) = {
117 .name = "System FPGA", 117 .name = "System FPGA",
118 .start = EXCITE_PHYS_FPGA, 118 .start = EXCITE_PHYS_FPGA,
119 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1, 119 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
@@ -122,7 +122,7 @@ static struct resource
122 .sibling = NULL, 122 .sibling = NULL,
123 .child = NULL 123 .child = NULL
124 }, 124 },
125 excite_nand_resource = { 125 excite_nand_resource __attribute__((unused)) = {
126 .name = "NAND flash control", 126 .name = "NAND flash control",
127 .start = EXCITE_PHYS_NAND, 127 .start = EXCITE_PHYS_NAND,
128 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1, 128 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
@@ -131,7 +131,7 @@ static struct resource
131 .sibling = NULL, 131 .sibling = NULL,
132 .child = NULL 132 .child = NULL
133 }, 133 },
134 excite_titan_resource = { 134 excite_titan_resource __attribute__((unused)) = {
135 .name = "TITAN registers", 135 .name = "TITAN registers",
136 .start = EXCITE_PHYS_TITAN, 136 .start = EXCITE_PHYS_TITAN,
137 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1, 137 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
diff --git a/arch/mips/basler/excite/excite_fpga.h b/arch/mips/basler/excite/excite_fpga.h
deleted file mode 100644
index 38fcda703a0b..000000000000
--- a/arch/mips/basler/excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
1#ifndef EXCITE_FPGA_H_INCLUDED
2#define EXCITE_FPGA_H_INCLUDED
3
4
5/**
6 * Adress alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform.
9 */
10#ifdef EXCITE_CCI_FPGA_MK2
11typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12#else
13typedef unsigned char excite_cci_fpga_align_t;
14#endif
15
16
17/**
18 * Size of Dual Ported RAM.
19 */
20#define EXCITE_DPR_SIZE 263
21
22
23/**
24 * Size of Reserved Status Fields in Dual Ported RAM.
25 */
26#define EXCITE_DPR_STATUS_SIZE 7
27
28
29
30/**
31 * FPGA.
32 * Hardware register layout of the FPGA interface. The FPGA must accessed
33 * byte wise solely.
34 * @see EXCITE_CCI_DPR_MK2
35 */
36typedef struct excite_fpga {
37
38 /**
39 * Dual Ported RAM.
40 */
41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42
43 /**
44 * Status.
45 */
46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47
48#ifdef EXCITE_CCI_FPGA_MK2
49 /**
50 * RM9000 Interrupt.
51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52 */
53 excite_cci_fpga_align_t rm9k_int;
54#else
55 /**
56 * MK2 Interrupt.
57 * Write access initiates interrupt at the ARM processor of the MK2.
58 */
59 excite_cci_fpga_align_t mk2_int;
60
61 excite_cci_fpga_align_t gap[0x1000-0x10f];
62
63 /**
64 * IRQ Source/Acknowledge.
65 */
66 excite_cci_fpga_align_t rm9k_irq_src;
67
68 /**
69 * IRQ Mask.
70 * Set bits enable the related interrupt.
71 */
72 excite_cci_fpga_align_t rm9k_irq_mask;
73#endif
74
75
76} excite_fpga;
77
78
79
80#endif /* ndef EXCITE_FPGA_H_INCLUDED */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 17:27:07 -0500