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Diffstat (limited to 'arch/mips/basler/excite/excite_irq.c')
-rw-r--r--arch/mips/basler/excite/excite_irq.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
index 511ad8730f54..2e2061a286c5 100644
--- a/arch/mips/basler/excite/excite_irq.c
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -56,7 +56,7 @@ void __init arch_init_irq(void)
56#endif 56#endif
57} 57}
58 58
59asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 59asmlinkage void plat_irq_dispatch(void)
60{ 60{
61 const u32 61 const u32
62 interrupts = read_c0_cause() >> 8, 62 interrupts = read_c0_cause() >> 8,
@@ -67,7 +67,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
67 67
68 /* process timer interrupt */ 68 /* process timer interrupt */
69 if (pending & (1 << TIMER_IRQ)) { 69 if (pending & (1 << TIMER_IRQ)) {
70 do_IRQ(TIMER_IRQ, regs); 70 do_IRQ(TIMER_IRQ);
71 return; 71 return;
72 } 72 }
73 73
@@ -80,7 +80,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
80#else 80#else
81 if (pending & (1 << USB_IRQ)) { 81 if (pending & (1 << USB_IRQ)) {
82#endif 82#endif
83 do_IRQ(USB_IRQ, regs); 83 do_IRQ(USB_IRQ);
84 return; 84 return;
85 } 85 }
86 86
@@ -91,9 +91,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
91 if ((pending & (1 << TITAN_IRQ)) && msgint) { 91 if ((pending & (1 << TITAN_IRQ)) && msgint) {
92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10)); 92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
93#if defined(CONFIG_KGDB) 93#if defined(CONFIG_KGDB)
94 excite_kgdb_inthdl(regs); 94 excite_kgdb_inthdl();
95#endif 95#endif
96 do_IRQ(TITAN_IRQ, regs); 96 do_IRQ(TITAN_IRQ);
97 return; 97 return;
98 } 98 }
99 99
@@ -102,7 +102,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
102 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10)); 102 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
103 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20)); 103 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
104 if ((pending & (1 << FPGA0_IRQ)) && msgint) { 104 if ((pending & (1 << FPGA0_IRQ)) && msgint) {
105 do_IRQ(FPGA0_IRQ, regs); 105 do_IRQ(FPGA0_IRQ);
106 return; 106 return;
107 } 107 }
108 108
@@ -111,7 +111,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
111 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10)); 111 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
112 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20)); 112 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
113 if ((pending & (1 << FPGA1_IRQ)) && msgint) { 113 if ((pending & (1 << FPGA1_IRQ)) && msgint) {
114 do_IRQ(FPGA1_IRQ, regs); 114 do_IRQ(FPGA1_IRQ);
115 return; 115 return;
116 } 116 }
117 117
@@ -120,10 +120,10 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
120 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10)); 120 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
121 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20)); 121 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
122 if ((pending & (1 << PHY_IRQ)) && msgint) { 122 if ((pending & (1 << PHY_IRQ)) && msgint) {
123 do_IRQ(PHY_IRQ, regs); 123 do_IRQ(PHY_IRQ);
124 return; 124 return;
125 } 125 }
126 126
127 /* Process spurious interrupts */ 127 /* Process spurious interrupts */
128 spurious_interrupt(regs); 128 spurious_interrupt();
129} 129}