diff options
Diffstat (limited to 'arch/mips/au1000/pb1100/board_setup.c')
-rw-r--r-- | arch/mips/au1000/pb1100/board_setup.c | 50 |
1 files changed, 26 insertions, 24 deletions
diff --git a/arch/mips/au1000/pb1100/board_setup.c b/arch/mips/au1000/pb1100/board_setup.c index 656164c8e9ca..c0bfd59a7a36 100644 --- a/arch/mips/au1000/pb1100/board_setup.c +++ b/arch/mips/au1000/pb1100/board_setup.c | |||
@@ -1,7 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2002 MontaVista Software Inc. | 2 | * Copyright 2002, 2008 MontaVista Software Inc. |
3 | * Author: MontaVista Software, Inc. | 3 | * Author: MontaVista Software, Inc. <source@mvista.com> |
4 | * ppopov@mvista.com or source@mvista.com | ||
5 | * | 4 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 5 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms of the GNU General Public License as published by the | 6 | * under the terms of the GNU General Public License as published by the |
@@ -32,15 +31,15 @@ | |||
32 | 31 | ||
33 | void board_reset(void) | 32 | void board_reset(void) |
34 | { | 33 | { |
35 | /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ | 34 | /* Hit BCSR.RST_VDDI[SOFT_RESET] */ |
36 | au_writel(0x00000000, 0xAE00001C); | 35 | au_writel(0x00000000, PB1100_RST_VDDI); |
37 | } | 36 | } |
38 | 37 | ||
39 | void __init board_setup(void) | 38 | void __init board_setup(void) |
40 | { | 39 | { |
41 | volatile void __iomem * base = (volatile void __iomem *) 0xac000000UL; | 40 | volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; |
42 | 41 | ||
43 | // set AUX clock to 12MHz * 8 = 96 MHz | 42 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ |
44 | au_writel(8, SYS_AUXPLL); | 43 | au_writel(8, SYS_AUXPLL); |
45 | au_writel(0, SYS_PININPUTEN); | 44 | au_writel(0, SYS_PININPUTEN); |
46 | udelay(100); | 45 | udelay(100); |
@@ -49,44 +48,47 @@ void __init board_setup(void) | |||
49 | { | 48 | { |
50 | u32 pin_func, sys_freqctrl, sys_clksrc; | 49 | u32 pin_func, sys_freqctrl, sys_clksrc; |
51 | 50 | ||
52 | // configure pins GPIO[14:9] as GPIO | 51 | /* Configure pins GPIO[14:9] as GPIO */ |
53 | pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x80); | 52 | pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; |
54 | 53 | ||
55 | /* zero and disable FREQ2 */ | 54 | /* Zero and disable FREQ2 */ |
56 | sys_freqctrl = au_readl(SYS_FREQCTRL0); | 55 | sys_freqctrl = au_readl(SYS_FREQCTRL0); |
57 | sys_freqctrl &= ~0xFFF00000; | 56 | sys_freqctrl &= ~0xFFF00000; |
58 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | 57 | au_writel(sys_freqctrl, SYS_FREQCTRL0); |
59 | 58 | ||
60 | /* zero and disable USBH/USBD/IrDA clock */ | 59 | /* Zero and disable USBH/USBD/IrDA clock */ |
61 | sys_clksrc = au_readl(SYS_CLKSRC); | 60 | sys_clksrc = au_readl(SYS_CLKSRC); |
62 | sys_clksrc &= ~0x0000001F; | 61 | sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK); |
63 | au_writel(sys_clksrc, SYS_CLKSRC); | 62 | au_writel(sys_clksrc, SYS_CLKSRC); |
64 | 63 | ||
65 | sys_freqctrl = au_readl(SYS_FREQCTRL0); | 64 | sys_freqctrl = au_readl(SYS_FREQCTRL0); |
66 | sys_freqctrl &= ~0xFFF00000; | 65 | sys_freqctrl &= ~0xFFF00000; |
67 | 66 | ||
68 | sys_clksrc = au_readl(SYS_CLKSRC); | 67 | sys_clksrc = au_readl(SYS_CLKSRC); |
69 | sys_clksrc &= ~0x0000001F; | 68 | sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK); |
70 | 69 | ||
71 | // FREQ2 = aux/2 = 48 MHz | 70 | /* FREQ2 = aux / 2 = 48 MHz */ |
72 | sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); | 71 | sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | |
72 | SYS_FC_FE2 | SYS_FC_FS2; | ||
73 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | 73 | au_writel(sys_freqctrl, SYS_FREQCTRL0); |
74 | 74 | ||
75 | /* | 75 | /* |
76 | * Route 48MHz FREQ2 into USBH/USBD/IrDA | 76 | * Route 48 MHz FREQ2 into USBH/USBD/IrDA |
77 | */ | 77 | */ |
78 | sys_clksrc |= ((4<<2) | (0<<1) | 0 ); | 78 | sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT; |
79 | au_writel(sys_clksrc, SYS_CLKSRC); | 79 | au_writel(sys_clksrc, SYS_CLKSRC); |
80 | 80 | ||
81 | /* setup the static bus controller */ | 81 | /* Setup the static bus controller */ |
82 | au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ | 82 | au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ |
83 | au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ | 83 | au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ |
84 | au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ | 84 | au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ |
85 | 85 | ||
86 | // get USB Functionality pin state (device vs host drive pins) | 86 | /* |
87 | pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000); | 87 | * Get USB Functionality pin state (device vs host drive pins). |
88 | // 2nd USB port is USB host | 88 | */ |
89 | pin_func |= 0x8000; | 89 | pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB; |
90 | /* 2nd USB port is USB host. */ | ||
91 | pin_func |= SYS_PF_USB; | ||
90 | au_writel(pin_func, SYS_PINFUNC); | 92 | au_writel(pin_func, SYS_PINFUNC); |
91 | } | 93 | } |
92 | #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ | 94 | #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ |
@@ -94,12 +96,12 @@ void __init board_setup(void) | |||
94 | /* Enable sys bus clock divider when IDLE state or no bus activity. */ | 96 | /* Enable sys bus clock divider when IDLE state or no bus activity. */ |
95 | au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); | 97 | au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); |
96 | 98 | ||
97 | // Enable the RTC if not already enabled | 99 | /* Enable the RTC if not already enabled. */ |
98 | if (!(readb(base + 0x28) & 0x20)) { | 100 | if (!(readb(base + 0x28) & 0x20)) { |
99 | writeb(readb(base + 0x28) | 0x20, base + 0x28); | 101 | writeb(readb(base + 0x28) | 0x20, base + 0x28); |
100 | au_sync(); | 102 | au_sync(); |
101 | } | 103 | } |
102 | // Put the clock in BCD mode | 104 | /* Put the clock in BCD mode. */ |
103 | if (readb(base + 0x2C) & 0x4) { /* reg B */ | 105 | if (readb(base + 0x2C) & 0x4) { /* reg B */ |
104 | writeb(readb(base + 0x2c) & ~0x4, base + 0x2c); | 106 | writeb(readb(base + 0x2c) & ~0x4, base + 0x2c); |
105 | au_sync(); | 107 | au_sync(); |