diff options
Diffstat (limited to 'arch/mips/alchemy/common/power.c')
-rw-r--r-- | arch/mips/alchemy/common/power.c | 74 |
1 files changed, 36 insertions, 38 deletions
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index bdb28dee8fdd..921ed30b440c 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c | |||
@@ -54,28 +54,28 @@ static unsigned int sleep_static_memctlr[4][3]; | |||
54 | static void save_core_regs(void) | 54 | static void save_core_regs(void) |
55 | { | 55 | { |
56 | /* Clocks and PLLs. */ | 56 | /* Clocks and PLLs. */ |
57 | sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); | 57 | sleep_sys_clocks[0] = alchemy_rdsys(AU1000_SYS_FREQCTRL0); |
58 | sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); | 58 | sleep_sys_clocks[1] = alchemy_rdsys(AU1000_SYS_FREQCTRL1); |
59 | sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); | 59 | sleep_sys_clocks[2] = alchemy_rdsys(AU1000_SYS_CLKSRC); |
60 | sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); | 60 | sleep_sys_clocks[3] = alchemy_rdsys(AU1000_SYS_CPUPLL); |
61 | sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); | 61 | sleep_sys_clocks[4] = alchemy_rdsys(AU1000_SYS_AUXPLL); |
62 | 62 | ||
63 | /* pin mux config */ | 63 | /* pin mux config */ |
64 | sleep_sys_pinfunc = au_readl(SYS_PINFUNC); | 64 | sleep_sys_pinfunc = alchemy_rdsys(AU1000_SYS_PINFUNC); |
65 | 65 | ||
66 | /* Save the static memory controller configuration. */ | 66 | /* Save the static memory controller configuration. */ |
67 | sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); | 67 | sleep_static_memctlr[0][0] = alchemy_rdsmem(AU1000_MEM_STCFG0); |
68 | sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); | 68 | sleep_static_memctlr[0][1] = alchemy_rdsmem(AU1000_MEM_STTIME0); |
69 | sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); | 69 | sleep_static_memctlr[0][2] = alchemy_rdsmem(AU1000_MEM_STADDR0); |
70 | sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1); | 70 | sleep_static_memctlr[1][0] = alchemy_rdsmem(AU1000_MEM_STCFG1); |
71 | sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1); | 71 | sleep_static_memctlr[1][1] = alchemy_rdsmem(AU1000_MEM_STTIME1); |
72 | sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1); | 72 | sleep_static_memctlr[1][2] = alchemy_rdsmem(AU1000_MEM_STADDR1); |
73 | sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2); | 73 | sleep_static_memctlr[2][0] = alchemy_rdsmem(AU1000_MEM_STCFG2); |
74 | sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2); | 74 | sleep_static_memctlr[2][1] = alchemy_rdsmem(AU1000_MEM_STTIME2); |
75 | sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2); | 75 | sleep_static_memctlr[2][2] = alchemy_rdsmem(AU1000_MEM_STADDR2); |
76 | sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); | 76 | sleep_static_memctlr[3][0] = alchemy_rdsmem(AU1000_MEM_STCFG3); |
77 | sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); | 77 | sleep_static_memctlr[3][1] = alchemy_rdsmem(AU1000_MEM_STTIME3); |
78 | sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); | 78 | sleep_static_memctlr[3][2] = alchemy_rdsmem(AU1000_MEM_STADDR3); |
79 | } | 79 | } |
80 | 80 | ||
81 | static void restore_core_regs(void) | 81 | static void restore_core_regs(void) |
@@ -85,30 +85,28 @@ static void restore_core_regs(void) | |||
85 | * one of those Au1000 with a write-only PLL, where we dont | 85 | * one of those Au1000 with a write-only PLL, where we dont |
86 | * have a valid value) | 86 | * have a valid value) |
87 | */ | 87 | */ |
88 | au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); | 88 | alchemy_wrsys(sleep_sys_clocks[0], AU1000_SYS_FREQCTRL0); |
89 | au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); | 89 | alchemy_wrsys(sleep_sys_clocks[1], AU1000_SYS_FREQCTRL1); |
90 | au_writel(sleep_sys_clocks[2], SYS_CLKSRC); | 90 | alchemy_wrsys(sleep_sys_clocks[2], AU1000_SYS_CLKSRC); |
91 | au_writel(sleep_sys_clocks[4], SYS_AUXPLL); | 91 | alchemy_wrsys(sleep_sys_clocks[4], AU1000_SYS_AUXPLL); |
92 | if (!au1xxx_cpu_has_pll_wo()) | 92 | if (!au1xxx_cpu_has_pll_wo()) |
93 | au_writel(sleep_sys_clocks[3], SYS_CPUPLL); | 93 | alchemy_wrsys(sleep_sys_clocks[3], AU1000_SYS_CPUPLL); |
94 | au_sync(); | ||
95 | 94 | ||
96 | au_writel(sleep_sys_pinfunc, SYS_PINFUNC); | 95 | alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC); |
97 | au_sync(); | ||
98 | 96 | ||
99 | /* Restore the static memory controller configuration. */ | 97 | /* Restore the static memory controller configuration. */ |
100 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); | 98 | alchemy_wrsmem(sleep_static_memctlr[0][0], AU1000_MEM_STCFG0); |
101 | au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); | 99 | alchemy_wrsmem(sleep_static_memctlr[0][1], AU1000_MEM_STTIME0); |
102 | au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); | 100 | alchemy_wrsmem(sleep_static_memctlr[0][2], AU1000_MEM_STADDR0); |
103 | au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); | 101 | alchemy_wrsmem(sleep_static_memctlr[1][0], AU1000_MEM_STCFG1); |
104 | au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); | 102 | alchemy_wrsmem(sleep_static_memctlr[1][1], AU1000_MEM_STTIME1); |
105 | au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); | 103 | alchemy_wrsmem(sleep_static_memctlr[1][2], AU1000_MEM_STADDR1); |
106 | au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); | 104 | alchemy_wrsmem(sleep_static_memctlr[2][0], AU1000_MEM_STCFG2); |
107 | au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); | 105 | alchemy_wrsmem(sleep_static_memctlr[2][1], AU1000_MEM_STTIME2); |
108 | au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); | 106 | alchemy_wrsmem(sleep_static_memctlr[2][2], AU1000_MEM_STADDR2); |
109 | au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); | 107 | alchemy_wrsmem(sleep_static_memctlr[3][0], AU1000_MEM_STCFG3); |
110 | au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); | 108 | alchemy_wrsmem(sleep_static_memctlr[3][1], AU1000_MEM_STTIME3); |
111 | au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); | 109 | alchemy_wrsmem(sleep_static_memctlr[3][2], AU1000_MEM_STADDR3); |
112 | } | 110 | } |
113 | 111 | ||
114 | void au_sleep(void) | 112 | void au_sleep(void) |