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-rw-r--r--arch/mips/alchemy/common/platform.c370
1 files changed, 89 insertions, 281 deletions
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index f72c48d4804c..c8e5d72a5826 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -18,7 +18,7 @@
18#include <linux/serial_8250.h> 18#include <linux/serial_8250.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20 20
21#include <asm/mach-au1x00/au1xxx.h> 21#include <asm/mach-au1x00/au1000.h>
22#include <asm/mach-au1x00/au1xxx_dbdma.h> 22#include <asm/mach-au1x00/au1xxx_dbdma.h>
23#include <asm/mach-au1x00/au1100_mmc.h> 23#include <asm/mach-au1x00/au1100_mmc.h>
24#include <asm/mach-au1x00/au1xxx_eth.h> 24#include <asm/mach-au1x00/au1xxx_eth.h>
@@ -111,270 +111,87 @@ static void __init alchemy_setup_uarts(int ctype)
111 printk(KERN_INFO "Alchemy: failed to register UARTs\n"); 111 printk(KERN_INFO "Alchemy: failed to register UARTs\n");
112} 112}
113 113
114/* OHCI (USB full speed host controller) */
115static struct resource au1xxx_usb_ohci_resources[] = {
116 [0] = {
117 .start = USB_OHCI_BASE,
118 .end = USB_OHCI_BASE + USB_OHCI_LEN - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 [1] = {
122 .start = FOR_PLATFORM_C_USB_HOST_INT,
123 .end = FOR_PLATFORM_C_USB_HOST_INT,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128/* The dmamask must be set for OHCI to work */
129static u64 ohci_dmamask = DMA_BIT_MASK(32);
130
131static struct platform_device au1xxx_usb_ohci_device = {
132 .name = "au1xxx-ohci",
133 .id = 0,
134 .dev = {
135 .dma_mask = &ohci_dmamask,
136 .coherent_dma_mask = DMA_BIT_MASK(32),
137 },
138 .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources),
139 .resource = au1xxx_usb_ohci_resources,
140};
141
142/*** AU1100 LCD controller ***/
143
144#ifdef CONFIG_FB_AU1100
145static struct resource au1100_lcd_resources[] = {
146 [0] = {
147 .start = LCD_PHYS_ADDR,
148 .end = LCD_PHYS_ADDR + 0x800 - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = AU1100_LCD_INT,
153 .end = AU1100_LCD_INT,
154 .flags = IORESOURCE_IRQ,
155 }
156};
157
158static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
159
160static struct platform_device au1100_lcd_device = {
161 .name = "au1100-lcd",
162 .id = 0,
163 .dev = {
164 .dma_mask = &au1100_lcd_dmamask,
165 .coherent_dma_mask = DMA_BIT_MASK(32),
166 },
167 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
168 .resource = au1100_lcd_resources,
169};
170#endif
171
172#ifdef CONFIG_SOC_AU1200
173/* EHCI (USB high speed host controller) */
174static struct resource au1xxx_usb_ehci_resources[] = {
175 [0] = {
176 .start = USB_EHCI_BASE,
177 .end = USB_EHCI_BASE + USB_EHCI_LEN - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = AU1200_USB_INT,
182 .end = AU1200_USB_INT,
183 .flags = IORESOURCE_IRQ,
184 },
185};
186
187static u64 ehci_dmamask = DMA_BIT_MASK(32);
188
189static struct platform_device au1xxx_usb_ehci_device = {
190 .name = "au1xxx-ehci",
191 .id = 0,
192 .dev = {
193 .dma_mask = &ehci_dmamask,
194 .coherent_dma_mask = DMA_BIT_MASK(32),
195 },
196 .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
197 .resource = au1xxx_usb_ehci_resources,
198};
199
200/* Au1200 UDC (USB gadget controller) */
201static struct resource au1xxx_usb_gdt_resources[] = {
202 [0] = {
203 .start = USB_UDC_BASE,
204 .end = USB_UDC_BASE + USB_UDC_LEN - 1,
205 .flags = IORESOURCE_MEM,
206 },
207 [1] = {
208 .start = AU1200_USB_INT,
209 .end = AU1200_USB_INT,
210 .flags = IORESOURCE_IRQ,
211 },
212};
213
214static u64 udc_dmamask = DMA_BIT_MASK(32);
215 114
216static struct platform_device au1xxx_usb_gdt_device = { 115/* The dmamask must be set for OHCI/EHCI to work */
217 .name = "au1xxx-udc", 116static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);
218 .id = 0, 117static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);
219 .dev = {
220 .dma_mask = &udc_dmamask,
221 .coherent_dma_mask = DMA_BIT_MASK(32),
222 },
223 .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
224 .resource = au1xxx_usb_gdt_resources,
225};
226 118
227/* Au1200 UOC (USB OTG controller) */ 119static unsigned long alchemy_ohci_data[][2] __initdata = {
228static struct resource au1xxx_usb_otg_resources[] = { 120 [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT },
229 [0] = { 121 [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT },
230 .start = USB_UOC_BASE, 122 [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
231 .end = USB_UOC_BASE + USB_UOC_LEN - 1, 123 [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
232 .flags = IORESOURCE_MEM, 124 [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
233 },
234 [1] = {
235 .start = AU1200_USB_INT,
236 .end = AU1200_USB_INT,
237 .flags = IORESOURCE_IRQ,
238 },
239}; 125};
240 126
241static u64 uoc_dmamask = DMA_BIT_MASK(32); 127static unsigned long alchemy_ehci_data[][2] __initdata = {
242 128 [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
243static struct platform_device au1xxx_usb_otg_device = {
244 .name = "au1xxx-uoc",
245 .id = 0,
246 .dev = {
247 .dma_mask = &uoc_dmamask,
248 .coherent_dma_mask = DMA_BIT_MASK(32),
249 },
250 .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
251 .resource = au1xxx_usb_otg_resources,
252}; 129};
253 130
254static struct resource au1200_lcd_resources[] = { 131static int __init _new_usbres(struct resource **r, struct platform_device **d)
255 [0] = { 132{
256 .start = LCD_PHYS_ADDR, 133 *r = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
257 .end = LCD_PHYS_ADDR + 0x800 - 1, 134 if (!*r)
258 .flags = IORESOURCE_MEM, 135 return -ENOMEM;
259 }, 136 *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
260 [1] = { 137 if (!*d) {
261 .start = AU1200_LCD_INT, 138 kfree(*r);
262 .end = AU1200_LCD_INT, 139 return -ENOMEM;
263 .flags = IORESOURCE_IRQ,
264 } 140 }
265};
266
267static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
268
269static struct platform_device au1200_lcd_device = {
270 .name = "au1200-lcd",
271 .id = 0,
272 .dev = {
273 .dma_mask = &au1200_lcd_dmamask,
274 .coherent_dma_mask = DMA_BIT_MASK(32),
275 },
276 .num_resources = ARRAY_SIZE(au1200_lcd_resources),
277 .resource = au1200_lcd_resources,
278};
279 141
280static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 142 (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32);
143 (*d)->num_resources = 2;
144 (*d)->resource = *r;
281 145
282extern struct au1xmmc_platform_data au1xmmc_platdata[2]; 146 return 0;
147}
283 148
284static struct resource au1200_mmc0_resources[] = { 149static void __init alchemy_setup_usb(int ctype)
285 [0] = { 150{
286 .start = AU1100_SD0_PHYS_ADDR, 151 struct resource *res;
287 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 152 struct platform_device *pdev;
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = AU1200_SD_INT,
292 .end = AU1200_SD_INT,
293 .flags = IORESOURCE_IRQ,
294 },
295 [2] = {
296 .start = DSCR_CMD0_SDMS_TX0,
297 .end = DSCR_CMD0_SDMS_TX0,
298 .flags = IORESOURCE_DMA,
299 },
300 [3] = {
301 .start = DSCR_CMD0_SDMS_RX0,
302 .end = DSCR_CMD0_SDMS_RX0,
303 .flags = IORESOURCE_DMA,
304 }
305};
306 153
307static struct platform_device au1200_mmc0_device = { 154 /* setup OHCI0. Every variant has one */
308 .name = "au1xxx-mmc", 155 if (_new_usbres(&res, &pdev))
309 .id = 0, 156 return;
310 .dev = {
311 .dma_mask = &au1xxx_mmc_dmamask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
313 .platform_data = &au1xmmc_platdata[0],
314 },
315 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
316 .resource = au1200_mmc0_resources,
317};
318 157
319#ifndef CONFIG_MIPS_DB1200 158 res[0].start = alchemy_ohci_data[ctype][0];
320static struct resource au1200_mmc1_resources[] = { 159 res[0].end = res[0].start + 0x100 - 1;
321 [0] = { 160 res[0].flags = IORESOURCE_MEM;
322 .start = AU1100_SD1_PHYS_ADDR, 161 res[1].start = alchemy_ohci_data[ctype][1];
323 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 162 res[1].end = res[1].start;
324 .flags = IORESOURCE_MEM, 163 res[1].flags = IORESOURCE_IRQ;
325 }, 164 pdev->name = "au1xxx-ohci";
326 [1] = { 165 pdev->id = 0;
327 .start = AU1200_SD_INT, 166 pdev->dev.dma_mask = &alchemy_ohci_dmamask;
328 .end = AU1200_SD_INT, 167
329 .flags = IORESOURCE_IRQ, 168 if (platform_device_register(pdev))
330 }, 169 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
331 [2] = { 170
332 .start = DSCR_CMD0_SDMS_TX1, 171
333 .end = DSCR_CMD0_SDMS_TX1, 172 /* setup EHCI0: Au1200 */
334 .flags = IORESOURCE_DMA, 173 if (ctype == ALCHEMY_CPU_AU1200) {
335 }, 174 if (_new_usbres(&res, &pdev))
336 [3] = { 175 return;
337 .start = DSCR_CMD0_SDMS_RX1, 176
338 .end = DSCR_CMD0_SDMS_RX1, 177 res[0].start = alchemy_ehci_data[ctype][0];
339 .flags = IORESOURCE_DMA, 178 res[0].end = res[0].start + 0x100 - 1;
179 res[0].flags = IORESOURCE_MEM;
180 res[1].start = alchemy_ehci_data[ctype][1];
181 res[1].end = res[1].start;
182 res[1].flags = IORESOURCE_IRQ;
183 pdev->name = "au1xxx-ehci";
184 pdev->id = 0;
185 pdev->dev.dma_mask = &alchemy_ehci_dmamask;
186
187 if (platform_device_register(pdev))
188 printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
340 } 189 }
341}; 190}
342
343static struct platform_device au1200_mmc1_device = {
344 .name = "au1xxx-mmc",
345 .id = 1,
346 .dev = {
347 .dma_mask = &au1xxx_mmc_dmamask,
348 .coherent_dma_mask = DMA_BIT_MASK(32),
349 .platform_data = &au1xmmc_platdata[1],
350 },
351 .num_resources = ARRAY_SIZE(au1200_mmc1_resources),
352 .resource = au1200_mmc1_resources,
353};
354#endif /* #ifndef CONFIG_MIPS_DB1200 */
355#endif /* #ifdef CONFIG_SOC_AU1200 */
356
357/* All Alchemy demoboards with I2C have this #define in their headers */
358#ifdef SMBUS_PSC_BASE
359static struct resource pbdb_smbus_resources[] = {
360 {
361 .start = CPHYSADDR(SMBUS_PSC_BASE),
362 .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
363 .flags = IORESOURCE_MEM,
364 },
365};
366
367static struct platform_device pbdb_smbus_device = {
368 .name = "au1xpsc_smbus",
369 .id = 0, /* bus number */
370 .num_resources = ARRAY_SIZE(pbdb_smbus_resources),
371 .resource = pbdb_smbus_resources,
372};
373#endif
374 191
375/* Macro to help defining the Ethernet MAC resources */ 192/* Macro to help defining the Ethernet MAC resources */
376#define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */ 193#define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
377#define MAC_RES(_base, _enable, _irq) \ 194#define MAC_RES(_base, _enable, _irq, _macdma) \
378 { \ 195 { \
379 .start = _base, \ 196 .start = _base, \
380 .end = _base + 0xffff, \ 197 .end = _base + 0xffff, \
@@ -389,28 +206,37 @@ static struct platform_device pbdb_smbus_device = {
389 .start = _irq, \ 206 .start = _irq, \
390 .end = _irq, \ 207 .end = _irq, \
391 .flags = IORESOURCE_IRQ \ 208 .flags = IORESOURCE_IRQ \
209 }, \
210 { \
211 .start = _macdma, \
212 .end = _macdma + 0x1ff, \
213 .flags = IORESOURCE_MEM, \
392 } 214 }
393 215
394static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = { 216static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
395 [ALCHEMY_CPU_AU1000] = { 217 [ALCHEMY_CPU_AU1000] = {
396 MAC_RES(AU1000_MAC0_PHYS_ADDR, 218 MAC_RES(AU1000_MAC0_PHYS_ADDR,
397 AU1000_MACEN_PHYS_ADDR, 219 AU1000_MACEN_PHYS_ADDR,
398 AU1000_MAC0_DMA_INT) 220 AU1000_MAC0_DMA_INT,
221 AU1000_MACDMA0_PHYS_ADDR)
399 }, 222 },
400 [ALCHEMY_CPU_AU1500] = { 223 [ALCHEMY_CPU_AU1500] = {
401 MAC_RES(AU1500_MAC0_PHYS_ADDR, 224 MAC_RES(AU1500_MAC0_PHYS_ADDR,
402 AU1500_MACEN_PHYS_ADDR, 225 AU1500_MACEN_PHYS_ADDR,
403 AU1500_MAC0_DMA_INT) 226 AU1500_MAC0_DMA_INT,
227 AU1000_MACDMA0_PHYS_ADDR)
404 }, 228 },
405 [ALCHEMY_CPU_AU1100] = { 229 [ALCHEMY_CPU_AU1100] = {
406 MAC_RES(AU1000_MAC0_PHYS_ADDR, 230 MAC_RES(AU1000_MAC0_PHYS_ADDR,
407 AU1000_MACEN_PHYS_ADDR, 231 AU1000_MACEN_PHYS_ADDR,
408 AU1100_MAC0_DMA_INT) 232 AU1100_MAC0_DMA_INT,
233 AU1000_MACDMA0_PHYS_ADDR)
409 }, 234 },
410 [ALCHEMY_CPU_AU1550] = { 235 [ALCHEMY_CPU_AU1550] = {
411 MAC_RES(AU1000_MAC0_PHYS_ADDR, 236 MAC_RES(AU1000_MAC0_PHYS_ADDR,
412 AU1000_MACEN_PHYS_ADDR, 237 AU1000_MACEN_PHYS_ADDR,
413 AU1550_MAC0_DMA_INT) 238 AU1550_MAC0_DMA_INT,
239 AU1000_MACDMA0_PHYS_ADDR)
414 }, 240 },
415}; 241};
416 242
@@ -429,17 +255,20 @@ static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
429 [ALCHEMY_CPU_AU1000] = { 255 [ALCHEMY_CPU_AU1000] = {
430 MAC_RES(AU1000_MAC1_PHYS_ADDR, 256 MAC_RES(AU1000_MAC1_PHYS_ADDR,
431 AU1000_MACEN_PHYS_ADDR + 4, 257 AU1000_MACEN_PHYS_ADDR + 4,
432 AU1000_MAC1_DMA_INT) 258 AU1000_MAC1_DMA_INT,
259 AU1000_MACDMA1_PHYS_ADDR)
433 }, 260 },
434 [ALCHEMY_CPU_AU1500] = { 261 [ALCHEMY_CPU_AU1500] = {
435 MAC_RES(AU1500_MAC1_PHYS_ADDR, 262 MAC_RES(AU1500_MAC1_PHYS_ADDR,
436 AU1500_MACEN_PHYS_ADDR + 4, 263 AU1500_MACEN_PHYS_ADDR + 4,
437 AU1500_MAC1_DMA_INT) 264 AU1500_MAC1_DMA_INT,
265 AU1000_MACDMA1_PHYS_ADDR)
438 }, 266 },
439 [ALCHEMY_CPU_AU1550] = { 267 [ALCHEMY_CPU_AU1550] = {
440 MAC_RES(AU1000_MAC1_PHYS_ADDR, 268 MAC_RES(AU1000_MAC1_PHYS_ADDR,
441 AU1000_MACEN_PHYS_ADDR + 4, 269 AU1000_MACEN_PHYS_ADDR + 4,
442 AU1550_MAC1_DMA_INT) 270 AU1550_MAC1_DMA_INT,
271 AU1000_MACDMA1_PHYS_ADDR)
443 }, 272 },
444}; 273};
445 274
@@ -521,36 +350,15 @@ static void __init alchemy_setup_macs(int ctype)
521 } 350 }
522} 351}
523 352
524static struct platform_device *au1xxx_platform_devices[] __initdata = {
525 &au1xxx_usb_ohci_device,
526#ifdef CONFIG_FB_AU1100
527 &au1100_lcd_device,
528#endif
529#ifdef CONFIG_SOC_AU1200
530 &au1xxx_usb_ehci_device,
531 &au1xxx_usb_gdt_device,
532 &au1xxx_usb_otg_device,
533 &au1200_lcd_device,
534 &au1200_mmc0_device,
535#ifndef CONFIG_MIPS_DB1200
536 &au1200_mmc1_device,
537#endif
538#endif
539#ifdef SMBUS_PSC_BASE
540 &pbdb_smbus_device,
541#endif
542};
543
544static int __init au1xxx_platform_init(void) 353static int __init au1xxx_platform_init(void)
545{ 354{
546 int err, ctype = alchemy_get_cputype(); 355 int ctype = alchemy_get_cputype();
547 356
548 alchemy_setup_uarts(ctype); 357 alchemy_setup_uarts(ctype);
549 alchemy_setup_macs(ctype); 358 alchemy_setup_macs(ctype);
359 alchemy_setup_usb(ctype);
550 360
551 err = platform_add_devices(au1xxx_platform_devices, 361 return 0;
552 ARRAY_SIZE(au1xxx_platform_devices));
553 return err;
554} 362}
555 363
556arch_initcall(au1xxx_platform_init); 364arch_initcall(au1xxx_platform_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 07:02:47 -0400