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-rw-r--r--arch/mips/alchemy/common/irq.c745
1 files changed, 380 insertions, 365 deletions
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 40c6ceceb5f9..c88c821b4c36 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -24,6 +24,7 @@
24 * with this program; if not, write to the Free Software Foundation, Inc., 24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */ 26 */
27
27#include <linux/bitops.h> 28#include <linux/bitops.h>
28#include <linux/init.h> 29#include <linux/init.h>
29#include <linux/interrupt.h> 30#include <linux/interrupt.h>
@@ -36,15 +37,172 @@
36#include <asm/mach-pb1x00/pb1000.h> 37#include <asm/mach-pb1x00/pb1000.h>
37#endif 38#endif
38 39
39#define EXT_INTC0_REQ0 2 /* IP 2 */ 40static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
40#define EXT_INTC0_REQ1 3 /* IP 3 */ 41
41#define EXT_INTC1_REQ0 4 /* IP 4 */ 42/* per-processor fixed function irqs */
42#define EXT_INTC1_REQ1 5 /* IP 5 */ 43struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = {
43#define MIPS_TIMER_IP 7 /* IP 7 */ 44
44 45#if defined(CONFIG_SOC_AU1000)
45void (*board_init_irq)(void) __initdata = NULL; 46 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
47 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
48 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
49 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
50 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
51 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
52 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
53 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
54 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
55 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
56 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
57 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
58 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
59 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
60 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
61 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
62 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
63 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
64 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
65 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
66 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
67 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
68 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
69 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
70 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
71 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
72 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
73 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
74 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
75 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
76 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
77
78#elif defined(CONFIG_SOC_AU1500)
79
80 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
81 { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
82 { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
83 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
84 { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
85 { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
86 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
87 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
88 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
89 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
90 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
91 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
92 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
93 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
94 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
95 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
96 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
97 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
98 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
99 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
100 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
101 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
102 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
103 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
104 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
105 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
106 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
107 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
108 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
109
110#elif defined(CONFIG_SOC_AU1100)
111
112 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
113 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
114 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
115 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
116 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
120 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
121 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
122 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
123 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
124 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
125 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
127 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
128 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
129 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
130 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
131 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
132 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
133 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
134 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
137 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
138 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
139 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
141 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
142 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
143
144#elif defined(CONFIG_SOC_AU1550)
145
146 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
147 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
148 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
149 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
150 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
152 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
153 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
154 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
155 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
156 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
157 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
158 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
159 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
160 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
161 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
162 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
163 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
164 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
165 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
166 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
167 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
168 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
169 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
170 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
171 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
172 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
173 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
174
175#elif defined(CONFIG_SOC_AU1200)
176
177 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
178 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
179 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
180 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
181 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
182 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
185 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
186 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
187 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
189 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
190 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
191 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
192 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
193 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
194 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
195 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
196 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
197 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
198 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
199 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
200
201#else
202#error "Error: Unknown Alchemy SOC"
203#endif
204};
46 205
47static DEFINE_SPINLOCK(irq_lock);
48 206
49#ifdef CONFIG_PM 207#ifdef CONFIG_PM
50 208
@@ -130,67 +288,47 @@ void restore_au1xxx_intctl(void)
130#endif /* CONFIG_PM */ 288#endif /* CONFIG_PM */
131 289
132 290
133inline void local_enable_irq(unsigned int irq_nr) 291static void au1x_ic0_unmask(unsigned int irq_nr)
134{ 292{
135 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 293 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
136 294 au_writel(1 << bit, IC0_MASKSET);
137 if (bit >= 32) { 295 au_writel(1 << bit, IC0_WAKESET);
138 au_writel(1 << (bit - 32), IC1_MASKSET);
139 au_writel(1 << (bit - 32), IC1_WAKESET);
140 } else {
141 au_writel(1 << bit, IC0_MASKSET);
142 au_writel(1 << bit, IC0_WAKESET);
143 }
144 au_sync(); 296 au_sync();
145} 297}
146 298
147 299static void au1x_ic1_unmask(unsigned int irq_nr)
148inline void local_disable_irq(unsigned int irq_nr)
149{ 300{
150 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 301 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
302 au_writel(1 << bit, IC1_MASKSET);
303 au_writel(1 << bit, IC1_WAKESET);
151 304
152 if (bit >= 32) { 305/* very hacky. does the pb1000 cpld auto-disable this int?
153 au_writel(1 << (bit - 32), IC1_MASKCLR); 306 * nowhere in the current kernel sources is it disabled. --mlau
154 au_writel(1 << (bit - 32), IC1_WAKECLR); 307 */
155 } else { 308#if defined(CONFIG_MIPS_PB1000)
156 au_writel(1 << bit, IC0_MASKCLR); 309 if (irq_nr == AU1000_GPIO_15)
157 au_writel(1 << bit, IC0_WAKECLR); 310 au_writel(0x4000, PB1000_MDR); /* enable int */
158 } 311#endif
159 au_sync(); 312 au_sync();
160} 313}
161 314
162 315static void au1x_ic0_mask(unsigned int irq_nr)
163static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
164{ 316{
165 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 317 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
166 318 au_writel(1 << bit, IC0_MASKCLR);
167 if (bit >= 32) { 319 au_writel(1 << bit, IC0_WAKECLR);
168 au_writel(1 << (bit - 32), IC1_RISINGCLR);
169 au_writel(1 << (bit - 32), IC1_MASKCLR);
170 } else {
171 au_writel(1 << bit, IC0_RISINGCLR);
172 au_writel(1 << bit, IC0_MASKCLR);
173 }
174 au_sync(); 320 au_sync();
175} 321}
176 322
177 323static void au1x_ic1_mask(unsigned int irq_nr)
178static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
179{ 324{
180 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 325 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
181 326 au_writel(1 << bit, IC1_MASKCLR);
182 if (bit >= 32) { 327 au_writel(1 << bit, IC1_WAKECLR);
183 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
184 au_writel(1 << (bit - 32), IC1_MASKCLR);
185 } else {
186 au_writel(1 << bit, IC0_FALLINGCLR);
187 au_writel(1 << bit, IC0_MASKCLR);
188 }
189 au_sync(); 328 au_sync();
190} 329}
191 330
192 331static void au1x_ic0_ack(unsigned int irq_nr)
193static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
194{ 332{
195 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 333 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
196 334
@@ -198,349 +336,229 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
198 * This may assume that we don't get interrupts from 336 * This may assume that we don't get interrupts from
199 * both edges at once, or if we do, that we don't care. 337 * both edges at once, or if we do, that we don't care.
200 */ 338 */
201 if (bit >= 32) { 339 au_writel(1 << bit, IC0_FALLINGCLR);
202 au_writel(1 << (bit - 32), IC1_FALLINGCLR); 340 au_writel(1 << bit, IC0_RISINGCLR);
203 au_writel(1 << (bit - 32), IC1_RISINGCLR);
204 au_writel(1 << (bit - 32), IC1_MASKCLR);
205 } else {
206 au_writel(1 << bit, IC0_FALLINGCLR);
207 au_writel(1 << bit, IC0_RISINGCLR);
208 au_writel(1 << bit, IC0_MASKCLR);
209 }
210 au_sync(); 341 au_sync();
211} 342}
212 343
213static inline void mask_and_ack_level_irq(unsigned int irq_nr) 344static void au1x_ic1_ack(unsigned int irq_nr)
214{ 345{
215 local_disable_irq(irq_nr); 346 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
216 au_sync();
217#if defined(CONFIG_MIPS_PB1000)
218 if (irq_nr == AU1000_GPIO_15) {
219 au_writel(0x8000, PB1000_MDR); /* ack int */
220 au_sync();
221 }
222#endif
223}
224
225static void end_irq(unsigned int irq_nr)
226{
227 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
228 local_enable_irq(irq_nr);
229 347
230#if defined(CONFIG_MIPS_PB1000) 348 /*
231 if (irq_nr == AU1000_GPIO_15) { 349 * This may assume that we don't get interrupts from
232 au_writel(0x4000, PB1000_MDR); /* enable int */ 350 * both edges at once, or if we do, that we don't care.
233 au_sync(); 351 */
234 } 352 au_writel(1 << bit, IC1_FALLINGCLR);
235#endif 353 au_writel(1 << bit, IC1_RISINGCLR);
354 au_sync();
236} 355}
237 356
238unsigned long save_local_and_disable(int controller) 357static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
239{ 358{
240 int i; 359 unsigned int bit = irq - AU1000_INTC1_INT_BASE;
241 unsigned long flags, mask; 360 unsigned long wakemsk, flags;
242
243 spin_lock_irqsave(&irq_lock, flags);
244 if (controller) {
245 mask = au_readl(IC1_MASKSET);
246 for (i = 32; i < 64; i++)
247 local_disable_irq(i);
248 } else {
249 mask = au_readl(IC0_MASKSET);
250 for (i = 0; i < 32; i++)
251 local_disable_irq(i);
252 }
253 spin_unlock_irqrestore(&irq_lock, flags);
254
255 return mask;
256}
257 361
258void restore_local_and_enable(int controller, unsigned long mask) 362 /* only GPIO 0-7 can act as wakeup source: */
259{ 363 if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7))
260 int i; 364 return -EINVAL;
261 unsigned long flags, new_mask;
262
263 spin_lock_irqsave(&irq_lock, flags);
264 for (i = 0; i < 32; i++)
265 if (mask & (1 << i)) {
266 if (controller)
267 local_enable_irq(i + 32);
268 else
269 local_enable_irq(i);
270 }
271 365
272 if (controller) 366 local_irq_save(flags);
273 new_mask = au_readl(IC1_MASKSET); 367 wakemsk = au_readl(SYS_WAKEMSK);
368 if (on)
369 wakemsk |= 1 << bit;
274 else 370 else
275 new_mask = au_readl(IC0_MASKSET); 371 wakemsk &= ~(1 << bit);
372 au_writel(wakemsk, SYS_WAKEMSK);
373 au_sync();
374 local_irq_restore(flags);
276 375
277 spin_unlock_irqrestore(&irq_lock, flags); 376 return 0;
278} 377}
279 378
280 379/*
281static struct irq_chip rise_edge_irq_type = { 380 * irq_chips for both ICs; this way the mask handlers can be
282 .name = "Au1000 Rise Edge", 381 * as short as possible.
283 .ack = mask_and_ack_rise_edge_irq, 382 *
284 .mask = local_disable_irq, 383 * NOTE: the ->ack() callback is used by the handle_edge_irq
285 .mask_ack = mask_and_ack_rise_edge_irq, 384 * flowhandler only, the ->mask_ack() one by handle_level_irq,
286 .unmask = local_enable_irq, 385 * so no need for an irq_chip for each type of irq (level/edge).
287 .end = end_irq, 386 */
288}; 387static struct irq_chip au1x_ic0_chip = {
289 388 .name = "Alchemy-IC0",
290static struct irq_chip fall_edge_irq_type = { 389 .ack = au1x_ic0_ack, /* edge */
291 .name = "Au1000 Fall Edge", 390 .mask = au1x_ic0_mask,
292 .ack = mask_and_ack_fall_edge_irq, 391 .mask_ack = au1x_ic0_mask, /* level */
293 .mask = local_disable_irq, 392 .unmask = au1x_ic0_unmask,
294 .mask_ack = mask_and_ack_fall_edge_irq, 393 .set_type = au1x_ic_settype,
295 .unmask = local_enable_irq,
296 .end = end_irq,
297};
298
299static struct irq_chip either_edge_irq_type = {
300 .name = "Au1000 Rise or Fall Edge",
301 .ack = mask_and_ack_either_edge_irq,
302 .mask = local_disable_irq,
303 .mask_ack = mask_and_ack_either_edge_irq,
304 .unmask = local_enable_irq,
305 .end = end_irq,
306}; 394};
307 395
308static struct irq_chip level_irq_type = { 396static struct irq_chip au1x_ic1_chip = {
309 .name = "Au1000 Level", 397 .name = "Alchemy-IC1",
310 .ack = mask_and_ack_level_irq, 398 .ack = au1x_ic1_ack, /* edge */
311 .mask = local_disable_irq, 399 .mask = au1x_ic1_mask,
312 .mask_ack = mask_and_ack_level_irq, 400 .mask_ack = au1x_ic1_mask, /* level */
313 .unmask = local_enable_irq, 401 .unmask = au1x_ic1_unmask,
314 .end = end_irq, 402 .set_type = au1x_ic_settype,
403 .set_wake = au1x_ic1_setwake,
315}; 404};
316 405
317static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req) 406static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
318{ 407{
319 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 408 struct irq_chip *chip;
320 409 unsigned long icr[6];
321 if (irq_nr > AU1000_MAX_INTR) 410 unsigned int bit, ic;
322 return; 411 int ret;
323 412
324 /* Config2[n], Config1[n], Config0[n] */ 413 if (irq >= AU1000_INTC1_INT_BASE) {
325 if (bit >= 32) { 414 bit = irq - AU1000_INTC1_INT_BASE;
326 switch (type) { 415 chip = &au1x_ic1_chip;
327 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 416 ic = 1;
328 au_writel(1 << (bit - 32), IC1_CFG2CLR);
329 au_writel(1 << (bit - 32), IC1_CFG1CLR);
330 au_writel(1 << (bit - 32), IC1_CFG0SET);
331 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1 << (bit - 32), IC1_CFG2CLR);
335 au_writel(1 << (bit - 32), IC1_CFG1SET);
336 au_writel(1 << (bit - 32), IC1_CFG0CLR);
337 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1 << (bit - 32), IC1_CFG2CLR);
341 au_writel(1 << (bit - 32), IC1_CFG1SET);
342 au_writel(1 << (bit - 32), IC1_CFG0SET);
343 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1 << (bit - 32), IC1_CFG2SET);
347 au_writel(1 << (bit - 32), IC1_CFG1CLR);
348 au_writel(1 << (bit - 32), IC1_CFG0SET);
349 set_irq_chip(irq_nr, &level_irq_type);
350 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1 << (bit - 32), IC1_CFG2SET);
353 au_writel(1 << (bit - 32), IC1_CFG1SET);
354 au_writel(1 << (bit - 32), IC1_CFG0CLR);
355 set_irq_chip(irq_nr, &level_irq_type);
356 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1 << (bit - 32), IC1_CFG0CLR);
359 au_writel(1 << (bit - 32), IC1_CFG1CLR);
360 au_writel(1 << (bit - 32), IC1_CFG2CLR);
361 break;
362 default: /* disable the interrupt */
363 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
364 type, irq_nr);
365 au_writel(1 << (bit - 32), IC1_CFG0CLR);
366 au_writel(1 << (bit - 32), IC1_CFG1CLR);
367 au_writel(1 << (bit - 32), IC1_CFG2CLR);
368 return;
369 }
370 if (int_req) /* assign to interrupt request 1 */
371 au_writel(1 << (bit - 32), IC1_ASSIGNCLR);
372 else /* assign to interrupt request 0 */
373 au_writel(1 << (bit - 32), IC1_ASSIGNSET);
374 au_writel(1 << (bit - 32), IC1_SRCSET);
375 au_writel(1 << (bit - 32), IC1_MASKCLR);
376 au_writel(1 << (bit - 32), IC1_WAKECLR);
377 } else { 417 } else {
378 switch (type) { 418 bit = irq - AU1000_INTC0_INT_BASE;
379 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 419 chip = &au1x_ic0_chip;
380 au_writel(1 << bit, IC0_CFG2CLR); 420 ic = 0;
381 au_writel(1 << bit, IC0_CFG1CLR); 421 }
382 au_writel(1 << bit, IC0_CFG0SET); 422
383 set_irq_chip(irq_nr, &rise_edge_irq_type); 423 if (bit > 31)
384 break; 424 return -EINVAL;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 425
386 au_writel(1 << bit, IC0_CFG2CLR); 426 icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
387 au_writel(1 << bit, IC0_CFG1SET); 427 icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
388 au_writel(1 << bit, IC0_CFG0CLR); 428 icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
389 set_irq_chip(irq_nr, &fall_edge_irq_type); 429 icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
390 break; 430 icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 431 icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
392 au_writel(1 << bit, IC0_CFG2CLR); 432
393 au_writel(1 << bit, IC0_CFG1SET); 433 ret = 0;
394 au_writel(1 << bit, IC0_CFG0SET); 434
395 set_irq_chip(irq_nr, &either_edge_irq_type); 435 switch (flow_type) { /* cfgregs 2:1:0 */
396 break; 436 case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 437 au_writel(1 << bit, icr[5]);
398 au_writel(1 << bit, IC0_CFG2SET); 438 au_writel(1 << bit, icr[4]);
399 au_writel(1 << bit, IC0_CFG1CLR); 439 au_writel(1 << bit, icr[0]);
400 au_writel(1 << bit, IC0_CFG0SET); 440 set_irq_chip_and_handler_name(irq, chip,
401 set_irq_chip(irq_nr, &level_irq_type); 441 handle_edge_irq, "riseedge");
402 break; 442 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 443 case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */
404 au_writel(1 << bit, IC0_CFG2SET); 444 au_writel(1 << bit, icr[5]);
405 au_writel(1 << bit, IC0_CFG1SET); 445 au_writel(1 << bit, icr[1]);
406 au_writel(1 << bit, IC0_CFG0CLR); 446 au_writel(1 << bit, icr[3]);
407 set_irq_chip(irq_nr, &level_irq_type); 447 set_irq_chip_and_handler_name(irq, chip,
408 break; 448 handle_edge_irq, "falledge");
409 case INTC_INT_DISABLED: /* 0:0:0 */ 449 break;
410 au_writel(1 << bit, IC0_CFG0CLR); 450 case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */
411 au_writel(1 << bit, IC0_CFG1CLR); 451 au_writel(1 << bit, icr[5]);
412 au_writel(1 << bit, IC0_CFG2CLR); 452 au_writel(1 << bit, icr[1]);
413 break; 453 au_writel(1 << bit, icr[0]);
414 default: /* disable the interrupt */ 454 set_irq_chip_and_handler_name(irq, chip,
415 printk(KERN_WARNING "unexpected int type %d (irq %d)\n", 455 handle_edge_irq, "bothedge");
416 type, irq_nr); 456 break;
417 au_writel(1 << bit, IC0_CFG0CLR); 457 case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */
418 au_writel(1 << bit, IC0_CFG1CLR); 458 au_writel(1 << bit, icr[2]);
419 au_writel(1 << bit, IC0_CFG2CLR); 459 au_writel(1 << bit, icr[4]);
420 return; 460 au_writel(1 << bit, icr[0]);
421 } 461 set_irq_chip_and_handler_name(irq, chip,
422 if (int_req) /* assign to interrupt request 1 */ 462 handle_level_irq, "hilevel");
423 au_writel(1 << bit, IC0_ASSIGNCLR); 463 break;
424 else /* assign to interrupt request 0 */ 464 case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */
425 au_writel(1 << bit, IC0_ASSIGNSET); 465 au_writel(1 << bit, icr[2]);
426 au_writel(1 << bit, IC0_SRCSET); 466 au_writel(1 << bit, icr[1]);
427 au_writel(1 << bit, IC0_MASKCLR); 467 au_writel(1 << bit, icr[3]);
428 au_writel(1 << bit, IC0_WAKECLR); 468 set_irq_chip_and_handler_name(irq, chip,
469 handle_level_irq, "lowlevel");
470 break;
471 case IRQ_TYPE_NONE: /* 0:0:0 */
472 au_writel(1 << bit, icr[5]);
473 au_writel(1 << bit, icr[4]);
474 au_writel(1 << bit, icr[3]);
475 /* set at least chip so we can call set_irq_type() on it */
476 set_irq_chip(irq, chip);
477 break;
478 default:
479 ret = -EINVAL;
429 } 480 }
430 au_sync(); 481 au_sync();
431}
432 482
433/* 483 return ret;
434 * Interrupts are nested. Even if an interrupt handler is registered 484}
435 * as "fast", we might get another interrupt before we return from
436 * intcX_reqX_irqdispatch().
437 */
438 485
439static void intc0_req0_irqdispatch(void) 486asmlinkage void plat_irq_dispatch(void)
440{ 487{
441 static unsigned long intc0_req0; 488 unsigned int pending = read_c0_status() & read_c0_cause();
442 unsigned int bit; 489 unsigned long s, off, bit;
443
444 intc0_req0 |= au_readl(IC0_REQ0INT);
445 490
446 if (!intc0_req0) 491 if (pending & CAUSEF_IP7) {
492 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
447 return; 493 return;
448 494 } else if (pending & CAUSEF_IP2) {
495 s = IC0_REQ0INT;
496 off = AU1000_INTC0_INT_BASE;
497 } else if (pending & CAUSEF_IP3) {
498 s = IC0_REQ1INT;
499 off = AU1000_INTC0_INT_BASE;
500 } else if (pending & CAUSEF_IP4) {
501 s = IC1_REQ0INT;
502 off = AU1000_INTC1_INT_BASE;
503 } else if (pending & CAUSEF_IP5) {
504 s = IC1_REQ1INT;
505 off = AU1000_INTC1_INT_BASE;
506 } else
507 goto spurious;
508
509 bit = 0;
510 s = au_readl(s);
511 if (unlikely(!s)) {
512spurious:
513 spurious_interrupt();
514 return;
515 }
449#ifdef AU1000_USB_DEV_REQ_INT 516#ifdef AU1000_USB_DEV_REQ_INT
450 /* 517 /*
451 * Because of the tight timing of SETUP token to reply 518 * Because of the tight timing of SETUP token to reply
452 * transactions, the USB devices-side packet complete 519 * transactions, the USB devices-side packet complete
453 * interrupt needs the highest priority. 520 * interrupt needs the highest priority.
454 */ 521 */
455 if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) { 522 bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE);
456 intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT); 523 if ((pending & CAUSEF_IP2) && (s & bit)) {
457 do_IRQ(AU1000_USB_DEV_REQ_INT); 524 do_IRQ(AU1000_USB_DEV_REQ_INT);
458 return; 525 return;
459 } 526 }
460#endif 527#endif
461 bit = __ffs(intc0_req0); 528 do_IRQ(__ffs(s) + off);
462 intc0_req0 &= ~(1 << bit);
463 do_IRQ(AU1000_INTC0_INT_BASE + bit);
464} 529}
465 530
466 531/* setup edge/level and assign request 0/1 */
467static void intc0_req1_irqdispatch(void) 532void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count)
468{
469 static unsigned long intc0_req1;
470 unsigned int bit;
471
472 intc0_req1 |= au_readl(IC0_REQ1INT);
473
474 if (!intc0_req1)
475 return;
476
477 bit = __ffs(intc0_req1);
478 intc0_req1 &= ~(1 << bit);
479 do_IRQ(AU1000_INTC0_INT_BASE + bit);
480}
481
482
483/*
484 * Interrupt Controller 1:
485 * interrupts 32 - 63
486 */
487static void intc1_req0_irqdispatch(void)
488{ 533{
489 static unsigned long intc1_req0; 534 unsigned int bit, irq_nr;
490 unsigned int bit; 535
491 536 while (count--) {
492 intc1_req0 |= au_readl(IC1_REQ0INT); 537 irq_nr = map[count].im_irq;
493 538
494 if (!intc1_req0) 539 if (((irq_nr < AU1000_INTC0_INT_BASE) ||
495 return; 540 (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
496 541 ((irq_nr < AU1000_INTC1_INT_BASE) ||
497 bit = __ffs(intc1_req0); 542 (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
498 intc1_req0 &= ~(1 << bit); 543 continue;
499 do_IRQ(AU1000_INTC1_INT_BASE + bit); 544
500} 545 if (irq_nr >= AU1000_INTC1_INT_BASE) {
501 546 bit = irq_nr - AU1000_INTC1_INT_BASE;
502 547 if (map[count].im_request)
503static void intc1_req1_irqdispatch(void) 548 au_writel(1 << bit, IC1_ASSIGNCLR);
504{ 549 } else {
505 static unsigned long intc1_req1; 550 bit = irq_nr - AU1000_INTC0_INT_BASE;
506 unsigned int bit; 551 if (map[count].im_request)
507 552 au_writel(1 << bit, IC0_ASSIGNCLR);
508 intc1_req1 |= au_readl(IC1_REQ1INT); 553 }
509
510 if (!intc1_req1)
511 return;
512
513 bit = __ffs(intc1_req1);
514 intc1_req1 &= ~(1 << bit);
515 do_IRQ(AU1000_INTC1_INT_BASE + bit);
516}
517
518asmlinkage void plat_irq_dispatch(void)
519{
520 unsigned int pending = read_c0_status() & read_c0_cause();
521 554
522 if (pending & CAUSEF_IP7) 555 au1x_ic_settype(irq_nr, map[count].im_type);
523 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 556 }
524 else if (pending & CAUSEF_IP2)
525 intc0_req0_irqdispatch();
526 else if (pending & CAUSEF_IP3)
527 intc0_req1_irqdispatch();
528 else if (pending & CAUSEF_IP4)
529 intc1_req0_irqdispatch();
530 else if (pending & CAUSEF_IP5)
531 intc1_req1_irqdispatch();
532 else
533 spurious_interrupt();
534} 557}
535 558
536void __init arch_init_irq(void) 559void __init arch_init_irq(void)
537{ 560{
538 int i; 561 int i;
539 struct au1xxx_irqmap *imp;
540 extern struct au1xxx_irqmap au1xxx_irq_map[];
541 extern struct au1xxx_irqmap au1xxx_ic0_map[];
542 extern int au1xxx_nr_irqs;
543 extern int au1xxx_ic0_nr_irqs;
544 562
545 /* 563 /*
546 * Initialize interrupt controllers to a safe state. 564 * Initialize interrupt controllers to a safe state.
@@ -569,28 +587,25 @@ void __init arch_init_irq(void)
569 587
570 mips_cpu_irq_init(); 588 mips_cpu_irq_init();
571 589
572 /* 590 /* register all 64 possible IC0+IC1 irq sources as type "none".
573 * Initialize IC0, which is fixed per processor. 591 * Use set_irq_type() to set edge/level behaviour at runtime.
574 */ 592 */
575 imp = au1xxx_ic0_map; 593 for (i = AU1000_INTC0_INT_BASE;
576 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) { 594 (i < AU1000_INTC0_INT_BASE + 32); i++)
577 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); 595 au1x_ic_settype(i, IRQ_TYPE_NONE);
578 imp++; 596
579 } 597 for (i = AU1000_INTC1_INT_BASE;
598 (i < AU1000_INTC1_INT_BASE + 32); i++)
599 au1x_ic_settype(i, IRQ_TYPE_NONE);
580 600
581 /* 601 /*
582 * Now set up the irq mapping for the board. 602 * Initialize IC0, which is fixed per processor.
583 */ 603 */
584 imp = au1xxx_irq_map; 604 au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));
585 for (i = 0; i < au1xxx_nr_irqs; i++) {
586 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
587 imp++;
588 }
589
590 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
591 605
592 /* Board specific IRQ initialization. 606 /* Boards can register additional (GPIO-based) IRQs.
593 */ 607 */
594 if (board_init_irq) 608 board_init_irq();
595 board_init_irq(); 609
610 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
596} 611}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 18:20:17 -0500