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-rw-r--r--arch/mips/alchemy/common/dma.c72
1 files changed, 34 insertions, 38 deletions
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 347980e79a89..9b624e2c0fcf 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -40,8 +40,6 @@
40#include <asm/mach-au1x00/au1000.h> 40#include <asm/mach-au1x00/au1000.h>
41#include <asm/mach-au1x00/au1000_dma.h> 41#include <asm/mach-au1x00/au1000_dma.h>
42 42
43#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
44 defined(CONFIG_SOC_AU1100)
45/* 43/*
46 * A note on resource allocation: 44 * A note on resource allocation:
47 * 45 *
@@ -88,12 +86,12 @@ static const struct dma_dev {
88 { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */ 86 { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
89 { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */ 87 { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
90 { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */ 88 { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
91 { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */ 89 { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
92 { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */ 90 { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
93 { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */ 91 { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
94 { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */ 92 { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
95 { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */ 93 { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
96 { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */ 94 { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
97 /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */ 95 /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
98 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */ 96 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
99 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */ 97 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
@@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str,
170 const struct dma_dev *dev; 168 const struct dma_dev *dev;
171 int i, ret; 169 int i, ret;
172 170
173#if defined(CONFIG_SOC_AU1100) 171 if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
174 if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2)) 172 if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
175 return -EINVAL; 173 return -EINVAL;
176#else 174 } else {
177 if (dev_id < 0 || dev_id >= DMA_NUM_DEV) 175 if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
178 return -EINVAL; 176 return -EINVAL;
179#endif 177 }
180 178
181 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) 179 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
182 if (au1000_dma_table[i].dev_id < 0) 180 if (au1000_dma_table[i].dev_id < 0)
@@ -239,30 +237,28 @@ EXPORT_SYMBOL(free_au1000_dma);
239 237
240static int __init au1000_dma_init(void) 238static int __init au1000_dma_init(void)
241{ 239{
242 int base, i; 240 int base, i;
243 241
244 switch (alchemy_get_cputype()) { 242 switch (alchemy_get_cputype()) {
245 case ALCHEMY_CPU_AU1000: 243 case ALCHEMY_CPU_AU1000:
246 base = AU1000_DMA_INT_BASE; 244 base = AU1000_DMA_INT_BASE;
247 break; 245 break;
248 case ALCHEMY_CPU_AU1500: 246 case ALCHEMY_CPU_AU1500:
249 base = AU1500_DMA_INT_BASE; 247 base = AU1500_DMA_INT_BASE;
250 break; 248 break;
251 case ALCHEMY_CPU_AU1100: 249 case ALCHEMY_CPU_AU1100:
252 base = AU1100_DMA_INT_BASE; 250 base = AU1100_DMA_INT_BASE;
253 break; 251 break;
254 default: 252 default:
255 goto out; 253 goto out;
256 } 254 }
257 255
258 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) 256 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
259 au1000_dma_table[i].irq = base + i; 257 au1000_dma_table[i].irq = base + i;
260 258
261 printk(KERN_INFO "Alchemy DMA initialized\n"); 259 printk(KERN_INFO "Alchemy DMA initialized\n");
262 260
263out: 261out:
264 return 0; 262 return 0;
265} 263}
266arch_initcall(au1000_dma_init); 264arch_initcall(au1000_dma_init);
267
268#endif /* AU1000 AU1500 AU1100 */