1 files changed, 22 insertions, 5 deletions

diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 604b7d009d8d..6a98d2cb402c 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -127,12 +127,20 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
                 t = 396000000;
         else {
                 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
+                if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
+                        t &= 0x3f;
                 t *= parent_rate;
         }
 
         return t;
 }
 
+void __init alchemy_set_lpj(void)
+{
+        preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE);
+        preset_lpj /= 2 * HZ;
+}
+
 static struct clk_ops alchemy_clkops_cpu = {
         .recalc_rate    = alchemy_clk_cpu_recalc,
 };
@@ -315,17 +323,26 @@ static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
 
 /* lrclk: external synchronous static bus clock ***********************/
 
-static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
+static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
 {
-        /* MEM_STCFG0[15:13] = divisor.
+        /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
+         * otherwise lrclk=pclk/4.
+         * All other variants: MEM_STCFG0[15:13] = divisor.
          * L/RCLK = periph_clk / (divisor + 1)
          * On Au1000, Au1500, Au1100 it's called LCLK,
          * on later models it's called RCLK, but it's the same thing.
          */
         struct clk *c;
-        unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
+        unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
 
-        v = (v & 7) + 1;
+        switch (t) {
+        case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1500:
+                v = 4 + ((v >> 11) & 1);
+                break;
+        default:        /* all other models */
+                v = ((v >> 13) & 7) + 1;
+        }
         c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
                                       pn, 0, 1, v);
         if (!IS_ERR(c))
@@ -1066,7 +1083,7 @@ static int __init alchemy_clk_init(void)
         ERRCK(c)
 
         /* L/RCLK: external static bus clock for synchronous mode */
-        c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
+        c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
         ERRCK(c)
 
         /* Frequency dividers 0-5 */