7 files changed, 94 insertions, 87 deletions

diff --git a/arch/microblaze/kernel/dma.c b/arch/microblaze/kernel/dma.c
index 9d69ca4b9635..ce72dd4967cf 100644
--- a/arch/microblaze/kernel/dma.c
+++ b/arch/microblaze/kernel/dma.c
@@ -38,7 +38,7 @@ static inline void __dma_sync_page(unsigned long paddr, unsigned long offset,
 
 static unsigned long get_dma_direct_offset(struct device *dev)
 {
-        if (dev)
+        if (likely(dev))
                 return (unsigned long)dev->archdata.dma_data;
 
         return PCI_DRAM_OFFSET; /* FIXME Not sure if is correct */
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index cb7815cfe5ab..da6a5f5dc766 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -51,6 +51,12 @@ swapper_pg_dir:
 
         .text
 ENTRY(_start)
+#if CONFIG_KERNEL_BASE_ADDR == 0
+        brai    TOPHYS(real_start)
+        .org    0x100
+real_start:
+#endif
+
         mfs     r1, rmsr
         andi    r1, r1, ~2
         mts     rmsr, r1
@@ -99,8 +105,8 @@ no_fdt_arg:
         tophys(r4,r4)                   /* convert to phys address */
         ori     r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
 _copy_command_line:
-        lbu     r2, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */
-        sb      r2, r4, r6              /* addr[r4+r6]= r7*/
+        lbu     r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
+        sb      r2, r4, r6              /* addr[r4+r6]= r2*/
         addik   r6, r6, 1               /* increment counting */
         bgtid   r3, _copy_command_line  /* loop for all entries       */
         addik   r3, r3, -1              /* descrement loop */
@@ -128,7 +134,7 @@ _copy_bram:
          * virtual to physical.
          */
         nop
-        addik   r3, r0, 63              /* Invalidate all TLB entries */
+        addik   r3, r0, MICROBLAZE_TLB_SIZE -1  /* Invalidate all TLB entries */
 _invalidate:
         mts     rtlbx, r3
         mts     rtlbhi, r0                      /* flush: ensure V is clear   */
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 2b86c03aa841..995a2123635b 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -313,13 +313,13 @@ _hw_exception_handler:
         mfs     r5, rmsr;
         nop
         swi     r5, r1, 0;
-        mfs     r3, resr
+        mfs     r4, resr
         nop
-        mfs     r4, rear;
+        mfs     r3, rear;
         nop
 
 #ifndef CONFIG_MMU
-        andi    r5, r3, 0x1000;         /* Check ESR[DS] */
+        andi    r5, r4, 0x1000;         /* Check ESR[DS] */
         beqi    r5, not_in_delay_slot;  /* Branch if ESR[DS] not set */
         mfs     r17, rbtr;      /* ESR[DS] set - return address in BTR */
         nop
@@ -327,13 +327,14 @@ not_in_delay_slot:
         swi     r17, r1, PT_R17
 #endif
 
-        andi    r5, r3, 0x1F;           /* Extract ESR[EXC] */
+        andi    r5, r4, 0x1F;           /* Extract ESR[EXC] */
 
 #ifdef CONFIG_MMU
         /* Calculate exception vector offset = r5 << 2 */
         addk    r6, r5, r5; /* << 1 */
         addk    r6, r6, r6; /* << 2 */
 
+#ifdef DEBUG
 /* counting which exception happen */
         lwi     r5, r0, 0x200 + TOPHYS(r0_ram)
         addi    r5, r5, 1
@@ -341,6 +342,7 @@ not_in_delay_slot:
         lwi     r5, r6, 0x200 + TOPHYS(r0_ram)
         addi    r5, r5, 1
         swi     r5, r6, 0x200 + TOPHYS(r0_ram)
+#endif
 /* end */
         /* Load the HW Exception vector */
         lwi     r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
@@ -376,7 +378,7 @@ handle_other_ex: /* Handle Other exceptions here */
         swi     r18, r1, PT_R18
 
         or      r5, r1, r0
-        andi    r6, r3, 0x1F; /* Load ESR[EC] */
+        andi    r6, r4, 0x1F; /* Load ESR[EC] */
         lwi     r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
         swi     r7, r1, PT_MODE
         mfs     r7, rfsr
@@ -426,11 +428,11 @@ handle_other_ex: /* Handle Other exceptions here */
  */
 handle_unaligned_ex:
         /* Working registers already saved: R3, R4, R5, R6
-         *  R3 = ESR
-         *  R4 = EAR
+         *  R4 = ESR
+         *  R3 = EAR
          */
 #ifdef CONFIG_MMU
-        andi    r6, r3, 0x1000                  /* Check ESR[DS] */
+        andi    r6, r4, 0x1000                  /* Check ESR[DS] */
         beqi    r6, _no_delayslot               /* Branch if ESR[DS] not set */
         mfs     r17, rbtr;      /* ESR[DS] set - return address in BTR */
         nop
@@ -439,7 +441,7 @@ _no_delayslot:
         RESTORE_STATE;
         bri     unaligned_data_trap
 #endif
-        andi    r6, r3, 0x3E0; /* Mask and extract the register operand */
+        andi    r6, r4, 0x3E0; /* Mask and extract the register operand */
         srl     r6, r6; /* r6 >> 5 */
         srl     r6, r6;
         srl     r6, r6;
@@ -448,33 +450,33 @@ _no_delayslot:
         /* Store the register operand in a temporary location */
         sbi     r6, r0, TOPHYS(ex_reg_op);
 
-        andi    r6, r3, 0x400; /* Extract ESR[S] */
+        andi    r6, r4, 0x400; /* Extract ESR[S] */
         bnei    r6, ex_sw;
 ex_lw:
-        andi    r6, r3, 0x800; /* Extract ESR[W] */
+        andi    r6, r4, 0x800; /* Extract ESR[W] */
         beqi    r6, ex_lhw;
-        lbui    r5, r4, 0; /* Exception address in r4 */
+        lbui    r5, r3, 0; /* Exception address in r3 */
         /* Load a word, byte-by-byte from destination address
                 and save it in tmp space */
         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_0);
-        lbui    r5, r4, 1;
+        lbui    r5, r3, 1;
         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_1);
-        lbui    r5, r4, 2;
+        lbui    r5, r3, 2;
         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_2);
-        lbui    r5, r4, 3;
+        lbui    r5, r3, 3;
         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_3);
-        /* Get the destination register value into r3 */
-        lwi     r3, r0, TOPHYS(ex_tmp_data_loc_0);
+        /* Get the destination register value into r4 */
+        lwi     r4, r0, TOPHYS(ex_tmp_data_loc_0);
         bri     ex_lw_tail;
 ex_lhw:
-        lbui    r5, r4, 0; /* Exception address in r4 */
+        lbui    r5, r3, 0; /* Exception address in r3 */
         /* Load a half-word, byte-by-byte from destination
                 address and save it in tmp space */
         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_0);
-        lbui    r5, r4, 1;
+        lbui    r5, r3, 1;
         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_1);
-        /* Get the destination register value into r3 */
-        lhui    r3, r0, TOPHYS(ex_tmp_data_loc_0);
+        /* Get the destination register value into r4 */
+        lhui    r4, r0, TOPHYS(ex_tmp_data_loc_0);
 ex_lw_tail:
         /* Get the destination register number into r5 */
         lbui    r5, r0, TOPHYS(ex_reg_op);
@@ -502,25 +504,25 @@ ex_sw_tail:
         andi    r6, r6, 0x800; /* Extract ESR[W] */
         beqi    r6, ex_shw;
         /* Get the word - delay slot */
-        swi     r3, r0, TOPHYS(ex_tmp_data_loc_0);
+        swi     r4, r0, TOPHYS(ex_tmp_data_loc_0);
         /* Store the word, byte-by-byte into destination address */
-        lbui    r3, r0, TOPHYS(ex_tmp_data_loc_0);
-        sbi     r3, r4, 0;
-        lbui    r3, r0, TOPHYS(ex_tmp_data_loc_1);
-        sbi     r3, r4, 1;
-        lbui    r3, r0, TOPHYS(ex_tmp_data_loc_2);
-        sbi     r3, r4, 2;
-        lbui    r3, r0, TOPHYS(ex_tmp_data_loc_3);
-        sbi     r3, r4, 3;
+        lbui    r4, r0, TOPHYS(ex_tmp_data_loc_0);
+        sbi     r4, r3, 0;
+        lbui    r4, r0, TOPHYS(ex_tmp_data_loc_1);
+        sbi     r4, r3, 1;
+        lbui    r4, r0, TOPHYS(ex_tmp_data_loc_2);
+        sbi     r4, r3, 2;
+        lbui    r4, r0, TOPHYS(ex_tmp_data_loc_3);
+        sbi     r4, r3, 3;
         bri     ex_handler_done;
 
 ex_shw:
         /* Store the lower half-word, byte-by-byte into destination address */
-        swi     r3, r0, TOPHYS(ex_tmp_data_loc_0);
-        lbui    r3, r0, TOPHYS(ex_tmp_data_loc_2);
-        sbi     r3, r4, 0;
-        lbui    r3, r0, TOPHYS(ex_tmp_data_loc_3);
-        sbi     r3, r4, 1;
+        swi     r4, r0, TOPHYS(ex_tmp_data_loc_0);
+        lbui    r4, r0, TOPHYS(ex_tmp_data_loc_2);
+        sbi     r4, r3, 0;
+        lbui    r4, r0, TOPHYS(ex_tmp_data_loc_3);
+        sbi     r4, r3, 1;
 ex_sw_end: /* Exception handling of store word, ends. */
 
 ex_handler_done:
@@ -560,21 +562,16 @@ ex_handler_done:
                  */
                 mfs     r11, rpid
                 nop
-                bri     4
-                mfs     r3, rear                /* Get faulting address */
-                nop
                 /* If we are faulting a kernel address, we have to use the
                  * kernel page tables.
                  */
-                ori     r4, r0, CONFIG_KERNEL_START
-                cmpu    r4, r3, r4
-                bgti    r4, ex3
+                ori     r5, r0, CONFIG_KERNEL_START
+                cmpu    r5, r3, r5
+                bgti    r5, ex3
                 /* First, check if it was a zone fault (which means a user
                  * tried to access a kernel or read-protected page - always
                  * a SEGV). All other faults here must be stores, so no
                  * need to check ESR_S as well. */
-                mfs     r4, resr
-                nop
                 andi    r4, r4, 0x800           /* ESR_Z - zone protection */
                 bnei    r4, ex2
 
@@ -589,8 +586,6 @@ ex_handler_done:
                  * tried to access a kernel or read-protected page - always
                  * a SEGV). All other faults here must be stores, so no
                  * need to check ESR_S as well. */
-                mfs     r4, resr
-                nop
                 andi    r4, r4, 0x800           /* ESR_Z */
                 bnei    r4, ex2
                 /* get current task address */
@@ -665,8 +660,6 @@ ex_handler_done:
                  * R3 = ESR
                  */
 
-                mfs     r3, rear                /* Get faulting address */
-                nop
                 RESTORE_STATE;
                 bri     page_fault_instr_trap
 
@@ -677,18 +670,15 @@ ex_handler_done:
          */
         handle_data_tlb_miss_exception:
                 /* Working registers already saved: R3, R4, R5, R6
-                 * R3 = ESR
+                 * R3 = EAR, R4 = ESR
                  */
                 mfs     r11, rpid
                 nop
-                bri     4
-                mfs     r3, rear                /* Get faulting address */
-                nop
 
                 /* If we are faulting a kernel address, we have to use the
                  * kernel page tables. */
-                ori     r4, r0, CONFIG_KERNEL_START
-                cmpu    r4, r3, r4
+                ori     r6, r0, CONFIG_KERNEL_START
+                cmpu    r4, r3, r6
                 bgti    r4, ex5
                 ori     r4, r0, swapper_pg_dir
                 mts     rpid, r0                /* TLB will have 0 TID */
@@ -731,9 +721,8 @@ ex_handler_done:
                  * Many of these bits are software only. Bits we don't set
                  * here we (properly should) assume have the appropriate value.
                  */
+                brid    finish_tlb_load
                 andni   r4, r4, 0x0ce2          /* Make sure 20, 21 are zero */
-
-                bri     finish_tlb_load
         ex7:
                 /* The bailout. Restore registers to pre-exception conditions
                  * and call the heavyweights to help us out.
@@ -754,9 +743,6 @@ ex_handler_done:
                  */
                 mfs     r11, rpid
                 nop
-                bri     4
-                mfs     r3, rear                /* Get faulting address */
-                nop
 
                 /* If we are faulting a kernel address, we have to use the
                  * kernel page tables.
@@ -792,7 +778,7 @@ ex_handler_done:
                 lwi     r4, r5, 0               /* Get Linux PTE */
 
                 andi    r6, r4, _PAGE_PRESENT
-                beqi    r6, ex7
+                beqi    r6, ex10
 
                 ori     r4, r4, _PAGE_ACCESSED
                 swi     r4, r5, 0
@@ -805,9 +791,8 @@ ex_handler_done:
                  * Many of these bits are software only. Bits we don't set
                  * here we (properly should) assume have the appropriate value.
                  */
+                brid    finish_tlb_load
                 andni   r4, r4, 0x0ce2          /* Make sure 20, 21 are zero */
-
-                bri     finish_tlb_load
         ex10:
                 /* The bailout. Restore registers to pre-exception conditions
                  * and call the heavyweights to help us out.
@@ -837,9 +822,9 @@ ex_handler_done:
                 andi    r5, r5, (MICROBLAZE_TLB_SIZE-1)
                 ori     r6, r0, 1
                 cmp     r31, r5, r6
-                blti    r31, sem
+                blti    r31, ex12
                 addik   r5, r6, 1
-        sem:
+        ex12:
                 /* MS: save back current TLB index */
                 swi     r5, r0, TOPHYS(tlb_index)
 
@@ -859,7 +844,6 @@ ex_handler_done:
                 nop
 
                 /* Done...restore registers and get out of here. */
-        ex12:
                 mts     rpid, r11
                 nop
                 bri 4
diff --git a/arch/microblaze/kernel/misc.S b/arch/microblaze/kernel/misc.S
index df16c6287a8e..7cf86498326c 100644
--- a/arch/microblaze/kernel/misc.S
+++ b/arch/microblaze/kernel/misc.S
@@ -26,9 +26,10 @@
  * We avoid flushing the pinned 0, 1 and possibly 2 entries.
  */
 .globl _tlbia;
+.type  _tlbia, @function
 .align 4;
 _tlbia:
-        addik   r12, r0, 63 /* flush all entries (63 - 3) */
+        addik   r12, r0, MICROBLAZE_TLB_SIZE - 1 /* flush all entries (63 - 3) */
         /* isync */
 _tlbia_1:
         mts     rtlbx, r12
@@ -41,11 +42,13 @@ _tlbia_1:
         /* sync */
         rtsd    r15, 8
         nop
+        .size  _tlbia, . - _tlbia
 
 /*
  * Flush MMU TLB for a particular address (in r5)
  */
 .globl _tlbie;
+.type  _tlbie, @function
 .align 4;
 _tlbie:
         mts     rtlbsx, r5 /* look up the address in TLB */
@@ -59,17 +62,20 @@ _tlbie_1:
         rtsd    r15, 8
         nop
 
+        .size  _tlbie, . - _tlbie
+
 /*
  * Allocate TLB entry for early console
  */
 .globl early_console_reg_tlb_alloc;
+.type  early_console_reg_tlb_alloc, @function
 .align 4;
 early_console_reg_tlb_alloc:
         /*
          * Load a TLB entry for the UART, so that microblaze_progress() can use
          * the UARTs nice and early.  We use a 4k real==virtual mapping.
          */
-        ori     r4, r0, 63
+        ori     r4, r0, MICROBLAZE_TLB_SIZE - 1
         mts     rtlbx, r4 /* TLB slot 2 */
 
         or      r4,r5,r0
@@ -86,6 +92,8 @@ early_console_reg_tlb_alloc:
         rtsd    r15, 8
         nop
 
+        .size  early_console_reg_tlb_alloc, . - early_console_reg_tlb_alloc
+
 /*
  * Copy a whole page (4096 bytes).
  */
@@ -104,6 +112,7 @@ early_console_reg_tlb_alloc:
 #define DCACHE_LINE_BYTES (4 * 4)
 
 .globl copy_page;
+.type  copy_page, @function
 .align 4;
 copy_page:
         ori     r11, r0, (PAGE_SIZE/DCACHE_LINE_BYTES) - 1
@@ -118,3 +127,5 @@ _copy_page_loop:
         addik   r11, r11, -1
         rtsd    r15, 8
         nop
+
+        .size  copy_page, . - copy_page
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index 812f1bf06c9e..09bed44dfcd3 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -15,6 +15,7 @@
 #include <linux/bitops.h>
 #include <asm/system.h>
 #include <asm/pgalloc.h>
+#include <asm/uaccess.h> /* for USER_DS macros */
 #include <asm/cacheflush.h>
 
 void show_regs(struct pt_regs *regs)
@@ -74,7 +75,10 @@ __setup("hlt", hlt_setup);
 
 void default_idle(void)
 {
-        if (!hlt_counter) {
+        if (likely(hlt_counter)) {
+                while (!need_resched())
+                        cpu_relax();
+        } else {
                 clear_thread_flag(TIF_POLLING_NRFLAG);
                 smp_mb__after_clear_bit();
                 local_irq_disable();
@@ -82,9 +86,7 @@ void default_idle(void)
                         cpu_sleep();
                 local_irq_enable();
                 set_thread_flag(TIF_POLLING_NRFLAG);
-        } else
-                while (!need_resched())
-                        cpu_relax();
+        }
 }
 
 void cpu_idle(void)
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index f974ec7aa357..17c98dbcec88 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -92,6 +92,12 @@ inline unsigned get_romfs_len(unsigned *addr)
 }
 #endif  /* CONFIG_MTD_UCLINUX_EBSS */
 
+#if defined(CONFIG_EARLY_PRINTK) && defined(CONFIG_SERIAL_UARTLITE_CONSOLE)
+#define eprintk early_printk
+#else
+#define eprintk printk
+#endif
+
 void __init machine_early_init(const char *cmdline, unsigned int ram,
                 unsigned int fdt, unsigned int msr)
 {
@@ -139,32 +145,32 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
         setup_early_printk(NULL);
 #endif
 
-        early_printk("Ramdisk addr 0x%08x, ", ram);
+        eprintk("Ramdisk addr 0x%08x, ", ram);
         if (fdt)
-                early_printk("FDT at 0x%08x\n", fdt);
+                eprintk("FDT at 0x%08x\n", fdt);
         else
-                early_printk("Compiled-in FDT at 0x%08x\n",
+                eprintk("Compiled-in FDT at 0x%08x\n",
                                         (unsigned int)_fdt_start);
 
 #ifdef CONFIG_MTD_UCLINUX
-        early_printk("Found romfs @ 0x%08x (0x%08x)\n",
+        eprintk("Found romfs @ 0x%08x (0x%08x)\n",
                         romfs_base, romfs_size);
-        early_printk("#### klimit %p ####\n", old_klimit);
+        eprintk("#### klimit %p ####\n", old_klimit);
         BUG_ON(romfs_size < 0); /* What else can we do? */
 
-        early_printk("Moved 0x%08x bytes from 0x%08x to 0x%08x\n",
+        eprintk("Moved 0x%08x bytes from 0x%08x to 0x%08x\n",
                         romfs_size, romfs_base, (unsigned)&_ebss);
 
-        early_printk("New klimit: 0x%08x\n", (unsigned)klimit);
+        eprintk("New klimit: 0x%08x\n", (unsigned)klimit);
 #endif
 
 #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
         if (msr)
-                early_printk("!!!Your kernel has setup MSR instruction but "
+                eprintk("!!!Your kernel has setup MSR instruction but "
                                 "CPU don't have it %d\n", msr);
 #else
         if (!msr)
-                early_printk("!!!Your kernel not setup MSR instruction but "
+                eprintk("!!!Your kernel not setup MSR instruction but "
                                 "CPU have it %d\n", msr);
 #endif
 
diff --git a/arch/microblaze/kernel/traps.c b/arch/microblaze/kernel/traps.c
index eaaaf805f31b..5e4570ef515c 100644
--- a/arch/microblaze/kernel/traps.c
+++ b/arch/microblaze/kernel/traps.c
@@ -22,13 +22,11 @@ void trap_init(void)
         __enable_hw_exceptions();
 }
 
-static int kstack_depth_to_print = 24;
+static unsigned long kstack_depth_to_print = 24;
 
 static int __init kstack_setup(char *s)
 {
-        kstack_depth_to_print = strict_strtoul(s, 0, NULL);
-
-        return 1;
+        return !strict_strtoul(s, 0, &kstack_depth_to_print);
 }
 __setup("kstack=", kstack_setup);