diff options
Diffstat (limited to 'arch/microblaze/include')
31 files changed, 377 insertions, 331 deletions
diff --git a/arch/microblaze/include/asm/byteorder.h b/arch/microblaze/include/asm/byteorder.h index ce9c58732ffc..31902762a426 100644 --- a/arch/microblaze/include/asm/byteorder.h +++ b/arch/microblaze/include/asm/byteorder.h | |||
@@ -1,6 +1,10 @@ | |||
1 | #ifndef _ASM_MICROBLAZE_BYTEORDER_H | 1 | #ifndef _ASM_MICROBLAZE_BYTEORDER_H |
2 | #define _ASM_MICROBLAZE_BYTEORDER_H | 2 | #define _ASM_MICROBLAZE_BYTEORDER_H |
3 | 3 | ||
4 | #ifdef __MICROBLAZEEL__ | ||
5 | #include <linux/byteorder/little_endian.h> | ||
6 | #else | ||
4 | #include <linux/byteorder/big_endian.h> | 7 | #include <linux/byteorder/big_endian.h> |
8 | #endif | ||
5 | 9 | ||
6 | #endif /* _ASM_MICROBLAZE_BYTEORDER_H */ | 10 | #endif /* _ASM_MICROBLAZE_BYTEORDER_H */ |
diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h index 7ebd955460d9..0f553bc009a0 100644 --- a/arch/microblaze/include/asm/cacheflush.h +++ b/arch/microblaze/include/asm/cacheflush.h | |||
@@ -84,12 +84,13 @@ do { \ | |||
84 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | 84 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
85 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | 85 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
86 | 86 | ||
87 | |||
88 | #define flush_cache_dup_mm(mm) do { } while (0) | 87 | #define flush_cache_dup_mm(mm) do { } while (0) |
89 | #define flush_cache_vmap(start, end) do { } while (0) | 88 | #define flush_cache_vmap(start, end) do { } while (0) |
90 | #define flush_cache_vunmap(start, end) do { } while (0) | 89 | #define flush_cache_vunmap(start, end) do { } while (0) |
91 | #define flush_cache_mm(mm) do { } while (0) | 90 | #define flush_cache_mm(mm) do { } while (0) |
92 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) | 91 | |
92 | #define flush_cache_page(vma, vmaddr, pfn) \ | ||
93 | flush_dcache_range(pfn << PAGE_SHIFT, (pfn << PAGE_SHIFT) + PAGE_SIZE); | ||
93 | 94 | ||
94 | /* MS: kgdb code use this macro, wrong len with FLASH */ | 95 | /* MS: kgdb code use this macro, wrong len with FLASH */ |
95 | #if 0 | 96 | #if 0 |
@@ -104,9 +105,13 @@ do { \ | |||
104 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | 105 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
105 | do { \ | 106 | do { \ |
106 | u32 addr = virt_to_phys(dst); \ | 107 | u32 addr = virt_to_phys(dst); \ |
107 | invalidate_icache_range((unsigned) (addr), (unsigned) (addr) + (len));\ | ||
108 | memcpy((dst), (src), (len)); \ | 108 | memcpy((dst), (src), (len)); \ |
109 | flush_dcache_range((unsigned) (addr), (unsigned) (addr) + (len));\ | 109 | if (vma->vm_flags & VM_EXEC) { \ |
110 | invalidate_icache_range((unsigned) (addr), \ | ||
111 | (unsigned) (addr) + PAGE_SIZE); \ | ||
112 | flush_dcache_range((unsigned) (addr), \ | ||
113 | (unsigned) (addr) + PAGE_SIZE); \ | ||
114 | } \ | ||
110 | } while (0) | 115 | } while (0) |
111 | 116 | ||
112 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | 117 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
diff --git a/arch/microblaze/include/asm/checksum.h b/arch/microblaze/include/asm/checksum.h index 128bf03b54b7..0185cbefdda4 100644 --- a/arch/microblaze/include/asm/checksum.h +++ b/arch/microblaze/include/asm/checksum.h | |||
@@ -24,8 +24,13 @@ csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, | |||
24 | "addc %0, %0, %3\n\t" | 24 | "addc %0, %0, %3\n\t" |
25 | "addc %0, %0, r0\n\t" | 25 | "addc %0, %0, r0\n\t" |
26 | : "+&d" (sum) | 26 | : "+&d" (sum) |
27 | : "d" (saddr), "d" (daddr), "d" (len + proto)); | 27 | : "d" (saddr), "d" (daddr), |
28 | 28 | #ifdef __MICROBLAZEEL__ | |
29 | "d" ((len + proto) << 8) | ||
30 | #else | ||
31 | "d" (len + proto) | ||
32 | #endif | ||
33 | ); | ||
29 | return sum; | 34 | return sum; |
30 | } | 35 | } |
31 | 36 | ||
diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h index b4f5ca33aebf..d8f013347a9e 100644 --- a/arch/microblaze/include/asm/cpuinfo.h +++ b/arch/microblaze/include/asm/cpuinfo.h | |||
@@ -38,6 +38,7 @@ struct cpuinfo { | |||
38 | u32 use_exc; | 38 | u32 use_exc; |
39 | u32 ver_code; | 39 | u32 ver_code; |
40 | u32 mmu; | 40 | u32 mmu; |
41 | u32 endian; | ||
41 | 42 | ||
42 | /* CPU caches */ | 43 | /* CPU caches */ |
43 | u32 use_icache; | 44 | u32 use_icache; |
@@ -76,7 +77,6 @@ struct cpuinfo { | |||
76 | u32 num_rd_brk; | 77 | u32 num_rd_brk; |
77 | u32 num_wr_brk; | 78 | u32 num_wr_brk; |
78 | u32 cpu_clock_freq; /* store real freq of cpu */ | 79 | u32 cpu_clock_freq; /* store real freq of cpu */ |
79 | u32 freq_div_hz; /* store freq/HZ */ | ||
80 | 80 | ||
81 | /* FPGA family */ | 81 | /* FPGA family */ |
82 | u32 fpga_family_code; | 82 | u32 fpga_family_code; |
@@ -96,8 +96,9 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu); | |||
96 | 96 | ||
97 | static inline unsigned int fcpu(struct device_node *cpu, char *n) | 97 | static inline unsigned int fcpu(struct device_node *cpu, char *n) |
98 | { | 98 | { |
99 | int *val; | 99 | const __be32 *val; |
100 | return (val = (int *) of_get_property(cpu, n, NULL)) ? *val : 0; | 100 | return (val = of_get_property(cpu, n, NULL)) ? |
101 | be32_to_cpup(val) : 0; | ||
101 | } | 102 | } |
102 | 103 | ||
103 | #endif /* _ASM_MICROBLAZE_CPUINFO_H */ | 104 | #endif /* _ASM_MICROBLAZE_CPUINFO_H */ |
diff --git a/arch/microblaze/include/asm/elf.h b/arch/microblaze/include/asm/elf.h index 732caf1be741..098dfdde4b06 100644 --- a/arch/microblaze/include/asm/elf.h +++ b/arch/microblaze/include/asm/elf.h | |||
@@ -71,7 +71,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; | |||
71 | 71 | ||
72 | #define ELF_ET_DYN_BASE (0x08000000) | 72 | #define ELF_ET_DYN_BASE (0x08000000) |
73 | 73 | ||
74 | #ifdef __LITTLE_ENDIAN__ | 74 | #ifdef __MICROBLAZEEL__ |
75 | #define ELF_DATA ELFDATA2LSB | 75 | #define ELF_DATA ELFDATA2LSB |
76 | #else | 76 | #else |
77 | #define ELF_DATA ELFDATA2MSB | 77 | #define ELF_DATA ELFDATA2MSB |
diff --git a/arch/microblaze/include/asm/entry.h b/arch/microblaze/include/asm/entry.h index ec89f2ad0fe1..af0144b91b79 100644 --- a/arch/microblaze/include/asm/entry.h +++ b/arch/microblaze/include/asm/entry.h | |||
@@ -31,40 +31,4 @@ DECLARE_PER_CPU(unsigned int, R11_SAVE); /* Temp variable for entry */ | |||
31 | DECLARE_PER_CPU(unsigned int, CURRENT_SAVE); /* Saved current pointer */ | 31 | DECLARE_PER_CPU(unsigned int, CURRENT_SAVE); /* Saved current pointer */ |
32 | # endif /* __ASSEMBLY__ */ | 32 | # endif /* __ASSEMBLY__ */ |
33 | 33 | ||
34 | #ifndef CONFIG_MMU | ||
35 | |||
36 | /* noMMU hasn't any space for args */ | ||
37 | # define STATE_SAVE_ARG_SPACE (0) | ||
38 | |||
39 | #else /* CONFIG_MMU */ | ||
40 | |||
41 | /* If true, system calls save and restore all registers (except result | ||
42 | * registers, of course). If false, then `call clobbered' registers | ||
43 | * will not be preserved, on the theory that system calls are basically | ||
44 | * function calls anyway, and the caller should be able to deal with it. | ||
45 | * This is a security risk, of course, as `internal' values may leak out | ||
46 | * after a system call, but that certainly doesn't matter very much for | ||
47 | * a processor with no MMU protection! For a protected-mode kernel, it | ||
48 | * would be faster to just zero those registers before returning. | ||
49 | * | ||
50 | * I can not rely on the glibc implementation. If you turn it off make | ||
51 | * sure that r11/r12 is saved in user-space. --KAA | ||
52 | * | ||
53 | * These are special variables using by the kernel trap/interrupt code | ||
54 | * to save registers in, at a time when there are no spare registers we | ||
55 | * can use to do so, and we can't depend on the value of the stack | ||
56 | * pointer. This means that they must be within a signed 16-bit | ||
57 | * displacement of 0x00000000. | ||
58 | */ | ||
59 | |||
60 | /* A `state save frame' is a struct pt_regs preceded by some extra space | ||
61 | * suitable for a function call stack frame. */ | ||
62 | |||
63 | /* Amount of room on the stack reserved for arguments and to satisfy the | ||
64 | * C calling conventions, in addition to the space used by the struct | ||
65 | * pt_regs that actually holds saved values. */ | ||
66 | #define STATE_SAVE_ARG_SPACE (6*4) /* Up to six arguments */ | ||
67 | |||
68 | #endif /* CONFIG_MMU */ | ||
69 | |||
70 | #endif /* _ASM_MICROBLAZE_ENTRY_H */ | 34 | #endif /* _ASM_MICROBLAZE_ENTRY_H */ |
diff --git a/arch/microblaze/include/asm/exceptions.h b/arch/microblaze/include/asm/exceptions.h index 6479097b802b..e6a8ddea1dca 100644 --- a/arch/microblaze/include/asm/exceptions.h +++ b/arch/microblaze/include/asm/exceptions.h | |||
@@ -66,6 +66,9 @@ | |||
66 | asmlinkage void full_exception(struct pt_regs *regs, unsigned int type, | 66 | asmlinkage void full_exception(struct pt_regs *regs, unsigned int type, |
67 | int fsr, int addr); | 67 | int fsr, int addr); |
68 | 68 | ||
69 | asmlinkage void sw_exception(struct pt_regs *regs); | ||
70 | void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig); | ||
71 | |||
69 | void die(const char *str, struct pt_regs *fp, long err); | 72 | void die(const char *str, struct pt_regs *fp, long err); |
70 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr); | 73 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr); |
71 | 74 | ||
diff --git a/arch/microblaze/include/asm/futex.h b/arch/microblaze/include/asm/futex.h index ad3fd61b2fe7..b0526d2716fa 100644 --- a/arch/microblaze/include/asm/futex.h +++ b/arch/microblaze/include/asm/futex.h | |||
@@ -29,7 +29,7 @@ | |||
29 | }) | 29 | }) |
30 | 30 | ||
31 | static inline int | 31 | static inline int |
32 | futex_atomic_op_inuser(int encoded_op, int __user *uaddr) | 32 | futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) |
33 | { | 33 | { |
34 | int op = (encoded_op >> 28) & 7; | 34 | int op = (encoded_op >> 28) & 7; |
35 | int cmp = (encoded_op >> 24) & 15; | 35 | int cmp = (encoded_op >> 24) & 15; |
@@ -39,7 +39,7 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr) | |||
39 | if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) | 39 | if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) |
40 | oparg = 1 << oparg; | 40 | oparg = 1 << oparg; |
41 | 41 | ||
42 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) | 42 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
43 | return -EFAULT; | 43 | return -EFAULT; |
44 | 44 | ||
45 | pagefault_disable(); | 45 | pagefault_disable(); |
@@ -94,31 +94,34 @@ futex_atomic_op_inuser(int encoded_op, int __user *uaddr) | |||
94 | } | 94 | } |
95 | 95 | ||
96 | static inline int | 96 | static inline int |
97 | futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) | 97 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, |
98 | u32 oldval, u32 newval) | ||
98 | { | 99 | { |
99 | int prev, cmp; | 100 | int ret = 0, cmp; |
101 | u32 prev; | ||
100 | 102 | ||
101 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) | 103 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
102 | return -EFAULT; | 104 | return -EFAULT; |
103 | 105 | ||
104 | __asm__ __volatile__ ("1: lwx %0, %2, r0; \ | 106 | __asm__ __volatile__ ("1: lwx %1, %3, r0; \ |
105 | cmp %1, %0, %3; \ | 107 | cmp %2, %1, %4; \ |
106 | beqi %1, 3f; \ | 108 | beqi %2, 3f; \ |
107 | 2: swx %4, %2, r0; \ | 109 | 2: swx %5, %3, r0; \ |
108 | addic %1, r0, 0; \ | 110 | addic %2, r0, 0; \ |
109 | bnei %1, 1b; \ | 111 | bnei %2, 1b; \ |
110 | 3: \ | 112 | 3: \ |
111 | .section .fixup,\"ax\"; \ | 113 | .section .fixup,\"ax\"; \ |
112 | 4: brid 3b; \ | 114 | 4: brid 3b; \ |
113 | addik %0, r0, %5; \ | 115 | addik %0, r0, %6; \ |
114 | .previous; \ | 116 | .previous; \ |
115 | .section __ex_table,\"a\"; \ | 117 | .section __ex_table,\"a\"; \ |
116 | .word 1b,4b,2b,4b; \ | 118 | .word 1b,4b,2b,4b; \ |
117 | .previous;" \ | 119 | .previous;" \ |
118 | : "=&r" (prev), "=&r"(cmp) \ | 120 | : "+r" (ret), "=&r" (prev), "=&r"(cmp) \ |
119 | : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)); | 121 | : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)); |
120 | 122 | ||
121 | return prev; | 123 | *uval = prev; |
124 | return ret; | ||
122 | } | 125 | } |
123 | 126 | ||
124 | #endif /* __KERNEL__ */ | 127 | #endif /* __KERNEL__ */ |
diff --git a/arch/microblaze/include/asm/gpio.h b/arch/microblaze/include/asm/gpio.h index 2345ac354d9b..2b2c18be71c6 100644 --- a/arch/microblaze/include/asm/gpio.h +++ b/arch/microblaze/include/asm/gpio.h | |||
@@ -38,12 +38,9 @@ static inline int gpio_cansleep(unsigned int gpio) | |||
38 | return __gpio_cansleep(gpio); | 38 | return __gpio_cansleep(gpio); |
39 | } | 39 | } |
40 | 40 | ||
41 | /* | ||
42 | * Not implemented, yet. | ||
43 | */ | ||
44 | static inline int gpio_to_irq(unsigned int gpio) | 41 | static inline int gpio_to_irq(unsigned int gpio) |
45 | { | 42 | { |
46 | return -ENOSYS; | 43 | return __gpio_to_irq(gpio); |
47 | } | 44 | } |
48 | 45 | ||
49 | static inline int irq_to_gpio(unsigned int irq) | 46 | static inline int irq_to_gpio(unsigned int irq) |
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h index 00b5398d08c7..8cdac14b55b0 100644 --- a/arch/microblaze/include/asm/io.h +++ b/arch/microblaze/include/asm/io.h | |||
@@ -70,7 +70,7 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) | |||
70 | 70 | ||
71 | /* | 71 | /* |
72 | * read (readb, readw, readl, readq) and write (writeb, writew, | 72 | * read (readb, readw, readl, readq) and write (writeb, writew, |
73 | * writel, writeq) accessors are for PCI and thus littel endian. | 73 | * writel, writeq) accessors are for PCI and thus little endian. |
74 | * Linux 2.4 for Microblaze had this wrong. | 74 | * Linux 2.4 for Microblaze had this wrong. |
75 | */ | 75 | */ |
76 | static inline unsigned char readb(const volatile void __iomem *addr) | 76 | static inline unsigned char readb(const volatile void __iomem *addr) |
@@ -243,6 +243,8 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size, | |||
243 | #define out_8(a, v) __raw_writeb((v), (a)) | 243 | #define out_8(a, v) __raw_writeb((v), (a)) |
244 | #define in_8(a) __raw_readb(a) | 244 | #define in_8(a) __raw_readb(a) |
245 | 245 | ||
246 | #define mmiowb() | ||
247 | |||
246 | #define ioport_map(port, nr) ((void __iomem *)(port)) | 248 | #define ioport_map(port, nr) ((void __iomem *)(port)) |
247 | #define ioport_unmap(addr) | 249 | #define ioport_unmap(addr) |
248 | 250 | ||
diff --git a/arch/microblaze/include/asm/irq.h b/arch/microblaze/include/asm/irq.h index ec5583d6111c..cc54187f3d38 100644 --- a/arch/microblaze/include/asm/irq.h +++ b/arch/microblaze/include/asm/irq.h | |||
@@ -12,8 +12,6 @@ | |||
12 | #define NR_IRQS 32 | 12 | #define NR_IRQS 32 |
13 | #include <asm-generic/irq.h> | 13 | #include <asm-generic/irq.h> |
14 | 14 | ||
15 | #include <linux/interrupt.h> | ||
16 | |||
17 | /* This type is the placeholder for a hardware interrupt number. It has to | 15 | /* This type is the placeholder for a hardware interrupt number. It has to |
18 | * be big enough to enclose whatever representation is used by a given | 16 | * be big enough to enclose whatever representation is used by a given |
19 | * platform. | 17 | * platform. |
diff --git a/arch/microblaze/include/asm/irqflags.h b/arch/microblaze/include/asm/irqflags.h index 2c38c6d80176..c4532f032b3b 100644 --- a/arch/microblaze/include/asm/irqflags.h +++ b/arch/microblaze/include/asm/irqflags.h | |||
@@ -9,103 +9,114 @@ | |||
9 | #ifndef _ASM_MICROBLAZE_IRQFLAGS_H | 9 | #ifndef _ASM_MICROBLAZE_IRQFLAGS_H |
10 | #define _ASM_MICROBLAZE_IRQFLAGS_H | 10 | #define _ASM_MICROBLAZE_IRQFLAGS_H |
11 | 11 | ||
12 | #include <linux/irqflags.h> | 12 | #include <linux/types.h> |
13 | #include <asm/registers.h> | 13 | #include <asm/registers.h> |
14 | 14 | ||
15 | # if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR | 15 | #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR |
16 | 16 | ||
17 | # define raw_local_irq_save(flags) \ | 17 | static inline unsigned long arch_local_irq_save(void) |
18 | do { \ | 18 | { |
19 | asm volatile (" msrclr %0, %1; \ | 19 | unsigned long flags; |
20 | nop;" \ | 20 | asm volatile(" msrclr %0, %1 \n" |
21 | : "=r"(flags) \ | 21 | " nop \n" |
22 | : "i"(MSR_IE) \ | 22 | : "=r"(flags) |
23 | : "memory"); \ | 23 | : "i"(MSR_IE) |
24 | } while (0) | 24 | : "memory"); |
25 | 25 | return flags; | |
26 | # define raw_local_irq_disable() \ | 26 | } |
27 | do { \ | 27 | |
28 | asm volatile (" msrclr r0, %0; \ | 28 | static inline void arch_local_irq_disable(void) |
29 | nop;" \ | 29 | { |
30 | : \ | 30 | /* this uses r0 without declaring it - is that correct? */ |
31 | : "i"(MSR_IE) \ | 31 | asm volatile(" msrclr r0, %0 \n" |
32 | : "memory"); \ | 32 | " nop \n" |
33 | } while (0) | 33 | : |
34 | 34 | : "i"(MSR_IE) | |
35 | # define raw_local_irq_enable() \ | 35 | : "memory"); |
36 | do { \ | 36 | } |
37 | asm volatile (" msrset r0, %0; \ | 37 | |
38 | nop;" \ | 38 | static inline void arch_local_irq_enable(void) |
39 | : \ | 39 | { |
40 | : "i"(MSR_IE) \ | 40 | /* this uses r0 without declaring it - is that correct? */ |
41 | : "memory"); \ | 41 | asm volatile(" msrset r0, %0 \n" |
42 | } while (0) | 42 | " nop \n" |
43 | 43 | : | |
44 | # else /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 0 */ | 44 | : "i"(MSR_IE) |
45 | 45 | : "memory"); | |
46 | # define raw_local_irq_save(flags) \ | 46 | } |
47 | do { \ | 47 | |
48 | register unsigned tmp; \ | 48 | #else /* !CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */ |
49 | asm volatile (" mfs %0, rmsr; \ | 49 | |
50 | nop; \ | 50 | static inline unsigned long arch_local_irq_save(void) |
51 | andi %1, %0, %2; \ | 51 | { |
52 | mts rmsr, %1; \ | 52 | unsigned long flags, tmp; |
53 | nop;" \ | 53 | asm volatile (" mfs %0, rmsr \n" |
54 | : "=r"(flags), "=r" (tmp) \ | 54 | " nop \n" |
55 | : "i"(~MSR_IE) \ | 55 | " andi %1, %0, %2 \n" |
56 | : "memory"); \ | 56 | " mts rmsr, %1 \n" |
57 | } while (0) | 57 | " nop \n" |
58 | 58 | : "=r"(flags), "=r"(tmp) | |
59 | # define raw_local_irq_disable() \ | 59 | : "i"(~MSR_IE) |
60 | do { \ | 60 | : "memory"); |
61 | register unsigned tmp; \ | 61 | return flags; |
62 | asm volatile (" mfs %0, rmsr; \ | 62 | } |
63 | nop; \ | 63 | |
64 | andi %0, %0, %1; \ | 64 | static inline void arch_local_irq_disable(void) |
65 | mts rmsr, %0; \ | 65 | { |
66 | nop;" \ | 66 | unsigned long tmp; |
67 | : "=r"(tmp) \ | 67 | asm volatile(" mfs %0, rmsr \n" |
68 | : "i"(~MSR_IE) \ | 68 | " nop \n" |
69 | : "memory"); \ | 69 | " andi %0, %0, %1 \n" |
70 | } while (0) | 70 | " mts rmsr, %0 \n" |
71 | 71 | " nop \n" | |
72 | # define raw_local_irq_enable() \ | 72 | : "=r"(tmp) |
73 | do { \ | 73 | : "i"(~MSR_IE) |
74 | register unsigned tmp; \ | 74 | : "memory"); |
75 | asm volatile (" mfs %0, rmsr; \ | 75 | } |
76 | nop; \ | 76 | |
77 | ori %0, %0, %1; \ | 77 | static inline void arch_local_irq_enable(void) |
78 | mts rmsr, %0; \ | 78 | { |
79 | nop;" \ | 79 | unsigned long tmp; |
80 | : "=r"(tmp) \ | 80 | asm volatile(" mfs %0, rmsr \n" |
81 | : "i"(MSR_IE) \ | 81 | " nop \n" |
82 | : "memory"); \ | 82 | " ori %0, %0, %1 \n" |
83 | } while (0) | 83 | " mts rmsr, %0 \n" |
84 | 84 | " nop \n" | |
85 | # endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */ | 85 | : "=r"(tmp) |
86 | 86 | : "i"(MSR_IE) | |
87 | #define raw_local_irq_restore(flags) \ | 87 | : "memory"); |
88 | do { \ | 88 | } |
89 | asm volatile (" mts rmsr, %0; \ | 89 | |
90 | nop;" \ | 90 | #endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */ |
91 | : \ | 91 | |
92 | : "r"(flags) \ | 92 | static inline unsigned long arch_local_save_flags(void) |
93 | : "memory"); \ | ||
94 | } while (0) | ||
95 | |||
96 | static inline unsigned long get_msr(void) | ||
97 | { | 93 | { |
98 | unsigned long flags; | 94 | unsigned long flags; |
99 | asm volatile (" mfs %0, rmsr; \ | 95 | asm volatile(" mfs %0, rmsr \n" |
100 | nop;" \ | 96 | " nop \n" |
101 | : "=r"(flags) \ | 97 | : "=r"(flags) |
102 | : \ | 98 | : |
103 | : "memory"); \ | 99 | : "memory"); |
104 | return flags; | 100 | return flags; |
105 | } | 101 | } |
106 | 102 | ||
107 | #define raw_local_save_flags(flags) ((flags) = get_msr()) | 103 | static inline void arch_local_irq_restore(unsigned long flags) |
108 | #define raw_irqs_disabled() ((get_msr() & MSR_IE) == 0) | 104 | { |
109 | #define raw_irqs_disabled_flags(flags) ((flags & MSR_IE) == 0) | 105 | asm volatile(" mts rmsr, %0 \n" |
106 | " nop \n" | ||
107 | : | ||
108 | : "r"(flags) | ||
109 | : "memory"); | ||
110 | } | ||
111 | |||
112 | static inline bool arch_irqs_disabled_flags(unsigned long flags) | ||
113 | { | ||
114 | return (flags & MSR_IE) == 0; | ||
115 | } | ||
116 | |||
117 | static inline bool arch_irqs_disabled(void) | ||
118 | { | ||
119 | return arch_irqs_disabled_flags(arch_local_save_flags()); | ||
120 | } | ||
110 | 121 | ||
111 | #endif /* _ASM_MICROBLAZE_IRQFLAGS_H */ | 122 | #endif /* _ASM_MICROBLAZE_IRQFLAGS_H */ |
diff --git a/arch/microblaze/include/asm/memblock.h b/arch/microblaze/include/asm/memblock.h index f9c2fa331d2a..20a8e257c77f 100644 --- a/arch/microblaze/include/asm/memblock.h +++ b/arch/microblaze/include/asm/memblock.h | |||
@@ -9,9 +9,6 @@ | |||
9 | #ifndef _ASM_MICROBLAZE_MEMBLOCK_H | 9 | #ifndef _ASM_MICROBLAZE_MEMBLOCK_H |
10 | #define _ASM_MICROBLAZE_MEMBLOCK_H | 10 | #define _ASM_MICROBLAZE_MEMBLOCK_H |
11 | 11 | ||
12 | /* MEMBLOCK limit is OFF */ | ||
13 | #define MEMBLOCK_REAL_LIMIT 0xFFFFFFFF | ||
14 | |||
15 | #endif /* _ASM_MICROBLAZE_MEMBLOCK_H */ | 12 | #endif /* _ASM_MICROBLAZE_MEMBLOCK_H */ |
16 | 13 | ||
17 | 14 | ||
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h index cf377d91da71..ed9d0f6e2cdb 100644 --- a/arch/microblaze/include/asm/page.h +++ b/arch/microblaze/include/asm/page.h | |||
@@ -205,9 +205,6 @@ extern int page_is_ram(unsigned long pfn); | |||
205 | #define TOPHYS(addr) __virt_to_phys(addr) | 205 | #define TOPHYS(addr) __virt_to_phys(addr) |
206 | 206 | ||
207 | #ifdef CONFIG_MMU | 207 | #ifdef CONFIG_MMU |
208 | #ifdef CONFIG_CONTIGUOUS_PAGE_ALLOC | ||
209 | #define WANT_PAGE_VIRTUAL 1 /* page alloc 2 relies on this */ | ||
210 | #endif | ||
211 | 208 | ||
212 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ | 209 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ |
213 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | 210 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) |
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 0c68764ab547..746df91e5796 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h | |||
@@ -76,7 +76,7 @@ struct pci_controller { | |||
76 | * Used for variants of PCI indirect handling and possible quirks: | 76 | * Used for variants of PCI indirect handling and possible quirks: |
77 | * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 | 77 | * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 |
78 | * EXT_REG - provides access to PCI-e extended registers | 78 | * EXT_REG - provides access to PCI-e extended registers |
79 | * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS | 79 | * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS |
80 | * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS | 80 | * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS |
81 | * to determine which bus number to match on when generating type0 | 81 | * to determine which bus number to match on when generating type0 |
82 | * config cycles | 82 | * config cycles |
@@ -104,11 +104,22 @@ struct pci_controller { | |||
104 | int global_number; /* PCI domain number */ | 104 | int global_number; /* PCI domain number */ |
105 | }; | 105 | }; |
106 | 106 | ||
107 | #ifdef CONFIG_PCI | ||
107 | static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) | 108 | static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) |
108 | { | 109 | { |
109 | return bus->sysdata; | 110 | return bus->sysdata; |
110 | } | 111 | } |
111 | 112 | ||
113 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) | ||
114 | { | ||
115 | struct pci_controller *host; | ||
116 | |||
117 | if (bus->self) | ||
118 | return pci_device_to_OF_node(bus->self); | ||
119 | host = pci_bus_to_host(bus); | ||
120 | return host ? host->dn : NULL; | ||
121 | } | ||
122 | |||
112 | static inline int isa_vaddr_is_ioport(void __iomem *address) | 123 | static inline int isa_vaddr_is_ioport(void __iomem *address) |
113 | { | 124 | { |
114 | /* No specific ISA handling on ppc32 at this stage, it | 125 | /* No specific ISA handling on ppc32 at this stage, it |
@@ -116,6 +127,7 @@ static inline int isa_vaddr_is_ioport(void __iomem *address) | |||
116 | */ | 127 | */ |
117 | return 0; | 128 | return 0; |
118 | } | 129 | } |
130 | #endif /* CONFIG_PCI */ | ||
119 | 131 | ||
120 | /* These are used for config access before all the PCI probing | 132 | /* These are used for config access before all the PCI probing |
121 | has been done. */ | 133 | has been done. */ |
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h index 5a388eeeb28f..ba65cf472544 100644 --- a/arch/microblaze/include/asm/pci.h +++ b/arch/microblaze/include/asm/pci.h | |||
@@ -158,12 +158,14 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar, | |||
158 | extern void pcibios_setup_bus_devices(struct pci_bus *bus); | 158 | extern void pcibios_setup_bus_devices(struct pci_bus *bus); |
159 | extern void pcibios_setup_bus_self(struct pci_bus *bus); | 159 | extern void pcibios_setup_bus_self(struct pci_bus *bus); |
160 | 160 | ||
161 | /* This part of code was originaly in xilinx-pci.h */ | 161 | /* This part of code was originally in xilinx-pci.h */ |
162 | #ifdef CONFIG_PCI_XILINX | 162 | #ifdef CONFIG_PCI_XILINX |
163 | extern void __init xilinx_pci_init(void); | 163 | extern void __init xilinx_pci_init(void); |
164 | #else | 164 | #else |
165 | static inline void __init xilinx_pci_init(void) { return; } | 165 | static inline void __init xilinx_pci_init(void) { return; } |
166 | #endif | 166 | #endif |
167 | 167 | ||
168 | #include <asm-generic/pci-dma-compat.h> | ||
169 | |||
168 | #endif /* __KERNEL__ */ | 170 | #endif /* __KERNEL__ */ |
169 | #endif /* __ASM_MICROBLAZE_PCI_H */ | 171 | #endif /* __ASM_MICROBLAZE_PCI_H */ |
diff --git a/arch/microblaze/include/asm/pgalloc.h b/arch/microblaze/include/asm/pgalloc.h index c614a893f8a3..ebd35792482c 100644 --- a/arch/microblaze/include/asm/pgalloc.h +++ b/arch/microblaze/include/asm/pgalloc.h | |||
@@ -165,7 +165,8 @@ extern inline void pte_free(struct mm_struct *mm, struct page *ptepage) | |||
165 | 165 | ||
166 | #define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, (pte)) | 166 | #define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, (pte)) |
167 | 167 | ||
168 | #define pmd_populate(mm, pmd, pte) (pmd_val(*(pmd)) = page_address(pte)) | 168 | #define pmd_populate(mm, pmd, pte) \ |
169 | (pmd_val(*(pmd)) = (unsigned long)page_address(pte)) | ||
169 | 170 | ||
170 | #define pmd_populate_kernel(mm, pmd, pte) \ | 171 | #define pmd_populate_kernel(mm, pmd, pte) \ |
171 | (pmd_val(*(pmd)) = (unsigned long) (pte)) | 172 | (pmd_val(*(pmd)) = (unsigned long) (pte)) |
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index ca2d92871545..b2af42311a12 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h | |||
@@ -57,6 +57,13 @@ static inline int pte_file(pte_t pte) { return 0; } | |||
57 | 57 | ||
58 | #define pgprot_noncached_wc(prot) prot | 58 | #define pgprot_noncached_wc(prot) prot |
59 | 59 | ||
60 | /* | ||
61 | * All 32bit addresses are effectively valid for vmalloc... | ||
62 | * Sort of meaningless for non-VM targets. | ||
63 | */ | ||
64 | #define VMALLOC_START 0 | ||
65 | #define VMALLOC_END 0xffffffff | ||
66 | |||
60 | #else /* CONFIG_MMU */ | 67 | #else /* CONFIG_MMU */ |
61 | 68 | ||
62 | #include <asm-generic/4level-fixup.h> | 69 | #include <asm-generic/4level-fixup.h> |
@@ -404,20 +411,19 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | |||
404 | static inline unsigned long pte_update(pte_t *p, unsigned long clr, | 411 | static inline unsigned long pte_update(pte_t *p, unsigned long clr, |
405 | unsigned long set) | 412 | unsigned long set) |
406 | { | 413 | { |
407 | unsigned long old, tmp, msr; | 414 | unsigned long flags, old, tmp; |
408 | 415 | ||
409 | __asm__ __volatile__("\ | 416 | raw_local_irq_save(flags); |
410 | msrclr %2, 0x2\n\ | 417 | |
411 | nop\n\ | 418 | __asm__ __volatile__( "lw %0, %2, r0 \n" |
412 | lw %0, %4, r0\n\ | 419 | "andn %1, %0, %3 \n" |
413 | andn %1, %0, %5\n\ | 420 | "or %1, %1, %4 \n" |
414 | or %1, %1, %6\n\ | 421 | "sw %1, %2, r0 \n" |
415 | sw %1, %4, r0\n\ | 422 | : "=&r" (old), "=&r" (tmp) |
416 | mts rmsr, %2\n\ | 423 | : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set) |
417 | nop" | 424 | : "cc"); |
418 | : "=&r" (old), "=&r" (tmp), "=&r" (msr), "=m" (*p) | 425 | |
419 | : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set), "m" (*p) | 426 | raw_local_irq_restore(flags); |
420 | : "cc"); | ||
421 | 427 | ||
422 | return old; | 428 | return old; |
423 | } | 429 | } |
@@ -437,8 +443,9 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |||
437 | *ptep = pte; | 443 | *ptep = pte; |
438 | } | 444 | } |
439 | 445 | ||
440 | static inline int ptep_test_and_clear_young(struct mm_struct *mm, | 446 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
441 | unsigned long addr, pte_t *ptep) | 447 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, |
448 | unsigned long address, pte_t *ptep) | ||
442 | { | 449 | { |
443 | return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; | 450 | return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; |
444 | } | 451 | } |
@@ -450,6 +457,7 @@ static inline int ptep_test_and_clear_dirty(struct mm_struct *mm, | |||
450 | (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; | 457 | (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; |
451 | } | 458 | } |
452 | 459 | ||
460 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | ||
453 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | 461 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
454 | unsigned long addr, pte_t *ptep) | 462 | unsigned long addr, pte_t *ptep) |
455 | { | 463 | { |
@@ -497,12 +505,9 @@ static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) | |||
497 | #define pte_offset_kernel(dir, addr) \ | 505 | #define pte_offset_kernel(dir, addr) \ |
498 | ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr)) | 506 | ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr)) |
499 | #define pte_offset_map(dir, addr) \ | 507 | #define pte_offset_map(dir, addr) \ |
500 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr)) | 508 | ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr)) |
501 | #define pte_offset_map_nested(dir, addr) \ | ||
502 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr)) | ||
503 | 509 | ||
504 | #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) | 510 | #define pte_unmap(pte) kunmap_atomic(pte) |
505 | #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) | ||
506 | 511 | ||
507 | /* Encode and decode a nonlinear file mapping entry */ | 512 | /* Encode and decode a nonlinear file mapping entry */ |
508 | #define PTE_FILE_MAX_BITS 29 | 513 | #define PTE_FILE_MAX_BITS 29 |
@@ -567,7 +572,7 @@ void __init *early_get_page(void); | |||
567 | 572 | ||
568 | extern unsigned long ioremap_bot, ioremap_base; | 573 | extern unsigned long ioremap_bot, ioremap_base; |
569 | 574 | ||
570 | void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle); | 575 | void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle); |
571 | void consistent_free(size_t size, void *vaddr); | 576 | void consistent_free(size_t size, void *vaddr); |
572 | void consistent_sync(void *vaddr, size_t size, int direction); | 577 | void consistent_sync(void *vaddr, size_t size, int direction); |
573 | void consistent_sync_page(struct page *page, unsigned long offset, | 578 | void consistent_sync_page(struct page *page, unsigned long offset, |
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h index 8eeb09211ece..aed2a6be8e27 100644 --- a/arch/microblaze/include/asm/processor.h +++ b/arch/microblaze/include/asm/processor.h | |||
@@ -155,7 +155,7 @@ unsigned long get_wchan(struct task_struct *p); | |||
155 | # define task_regs(task) ((struct pt_regs *)task_tos(task) - 1) | 155 | # define task_regs(task) ((struct pt_regs *)task_tos(task) - 1) |
156 | 156 | ||
157 | # define task_pt_regs_plus_args(tsk) \ | 157 | # define task_pt_regs_plus_args(tsk) \ |
158 | (((void *)task_pt_regs(tsk)) - STATE_SAVE_ARG_SPACE) | 158 | ((void *)task_pt_regs(tsk)) |
159 | 159 | ||
160 | # define task_sp(task) (task_regs(task)->r1) | 160 | # define task_sp(task) (task_regs(task)->r1) |
161 | # define task_pc(task) (task_regs(task)->pc) | 161 | # define task_pc(task) (task_regs(task)->pc) |
diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h index 101fa098f62a..d0890d36ef61 100644 --- a/arch/microblaze/include/asm/prom.h +++ b/arch/microblaze/include/asm/prom.h | |||
@@ -27,6 +27,7 @@ | |||
27 | 27 | ||
28 | /* Other Prototypes */ | 28 | /* Other Prototypes */ |
29 | extern int early_uartlite_console(void); | 29 | extern int early_uartlite_console(void); |
30 | extern int early_uart16550_console(void); | ||
30 | 31 | ||
31 | #ifdef CONFIG_PCI | 32 | #ifdef CONFIG_PCI |
32 | /* | 33 | /* |
@@ -63,24 +64,6 @@ extern void kdump_move_device_tree(void); | |||
63 | /* CPU OF node matching */ | 64 | /* CPU OF node matching */ |
64 | struct device_node *of_get_cpu_node(int cpu, unsigned int *thread); | 65 | struct device_node *of_get_cpu_node(int cpu, unsigned int *thread); |
65 | 66 | ||
66 | /* Get the MAC address */ | ||
67 | extern const void *of_get_mac_address(struct device_node *np); | ||
68 | |||
69 | /** | ||
70 | * of_irq_map_pci - Resolve the interrupt for a PCI device | ||
71 | * @pdev: the device whose interrupt is to be resolved | ||
72 | * @out_irq: structure of_irq filled by this function | ||
73 | * | ||
74 | * This function resolves the PCI interrupt for a given PCI device. If a | ||
75 | * device-node exists for a given pci_dev, it will use normal OF tree | ||
76 | * walking. If not, it will implement standard swizzling and walk up the | ||
77 | * PCI tree until an device-node is found, at which point it will finish | ||
78 | * resolving using the OF tree walking. | ||
79 | */ | ||
80 | struct pci_dev; | ||
81 | struct of_irq; | ||
82 | extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq); | ||
83 | |||
84 | #endif /* __ASSEMBLY__ */ | 67 | #endif /* __ASSEMBLY__ */ |
85 | #endif /* __KERNEL__ */ | 68 | #endif /* __KERNEL__ */ |
86 | 69 | ||
diff --git a/arch/microblaze/include/asm/ptrace.h b/arch/microblaze/include/asm/ptrace.h index d74dbfb92c04..d9b66304d5dd 100644 --- a/arch/microblaze/include/asm/ptrace.h +++ b/arch/microblaze/include/asm/ptrace.h | |||
@@ -66,13 +66,13 @@ void show_regs(struct pt_regs *); | |||
66 | #else /* __KERNEL__ */ | 66 | #else /* __KERNEL__ */ |
67 | 67 | ||
68 | /* pt_regs offsets used by gdbserver etc in ptrace syscalls */ | 68 | /* pt_regs offsets used by gdbserver etc in ptrace syscalls */ |
69 | #define PT_GPR(n) ((n) * sizeof(microblaze_reg_t)) | 69 | #define PT_GPR(n) ((n) * sizeof(microblaze_reg_t)) |
70 | #define PT_PC (32 * sizeof(microblaze_reg_t)) | 70 | #define PT_PC (32 * sizeof(microblaze_reg_t)) |
71 | #define PT_MSR (33 * sizeof(microblaze_reg_t)) | 71 | #define PT_MSR (33 * sizeof(microblaze_reg_t)) |
72 | #define PT_EAR (34 * sizeof(microblaze_reg_t)) | 72 | #define PT_EAR (34 * sizeof(microblaze_reg_t)) |
73 | #define PT_ESR (35 * sizeof(microblaze_reg_t)) | 73 | #define PT_ESR (35 * sizeof(microblaze_reg_t)) |
74 | #define PT_FSR (36 * sizeof(microblaze_reg_t)) | 74 | #define PT_FSR (36 * sizeof(microblaze_reg_t)) |
75 | #define PT_KERNEL_MODE (37 * sizeof(microblaze_reg_t)) | 75 | #define PT_KERNEL_MODE (37 * sizeof(microblaze_reg_t)) |
76 | 76 | ||
77 | #endif /* __KERNEL */ | 77 | #endif /* __KERNEL */ |
78 | 78 | ||
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h index 9578666e98ba..a10bec62e857 100644 --- a/arch/microblaze/include/asm/pvr.h +++ b/arch/microblaze/include/asm/pvr.h | |||
@@ -1,9 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * Support for the MicroBlaze PVR (Processor Version Register) | 2 | * Support for the MicroBlaze PVR (Processor Version Register) |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Michal Simek <monstr@monstr.eu> | 4 | * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu> |
5 | * Copyright (C) 2007 John Williams <john.williams@petalogix.com> | 5 | * Copyright (C) 2007 John Williams <john.williams@petalogix.com> |
6 | * Copyright (C) 2007 - 2009 PetaLogix | 6 | * Copyright (C) 2007 - 2011 PetaLogix |
7 | * | 7 | * |
8 | * This file is subject to the terms and conditions of the GNU General | 8 | * This file is subject to the terms and conditions of the GNU General |
9 | * Public License. See the file COPYING in the main directory of this | 9 | * Public License. See the file COPYING in the main directory of this |
@@ -30,7 +30,9 @@ struct pvr_s { | |||
30 | #define PVR0_USE_EXC_MASK 0x04000000 | 30 | #define PVR0_USE_EXC_MASK 0x04000000 |
31 | #define PVR0_USE_ICACHE_MASK 0x02000000 | 31 | #define PVR0_USE_ICACHE_MASK 0x02000000 |
32 | #define PVR0_USE_DCACHE_MASK 0x01000000 | 32 | #define PVR0_USE_DCACHE_MASK 0x01000000 |
33 | #define PVR0_USE_MMU 0x00800000 /* new */ | 33 | #define PVR0_USE_MMU 0x00800000 |
34 | #define PVR0_USE_BTC 0x00400000 | ||
35 | #define PVR0_ENDI 0x00200000 | ||
34 | #define PVR0_VERSION_MASK 0x0000FF00 | 36 | #define PVR0_VERSION_MASK 0x0000FF00 |
35 | #define PVR0_USER1_MASK 0x000000FF | 37 | #define PVR0_USER1_MASK 0x000000FF |
36 | 38 | ||
@@ -38,17 +40,17 @@ struct pvr_s { | |||
38 | #define PVR1_USER2_MASK 0xFFFFFFFF | 40 | #define PVR1_USER2_MASK 0xFFFFFFFF |
39 | 41 | ||
40 | /* Configuration PVR masks */ | 42 | /* Configuration PVR masks */ |
41 | #define PVR2_D_OPB_MASK 0x80000000 | 43 | #define PVR2_D_OPB_MASK 0x80000000 /* or AXI */ |
42 | #define PVR2_D_LMB_MASK 0x40000000 | 44 | #define PVR2_D_LMB_MASK 0x40000000 |
43 | #define PVR2_I_OPB_MASK 0x20000000 | 45 | #define PVR2_I_OPB_MASK 0x20000000 /* or AXI */ |
44 | #define PVR2_I_LMB_MASK 0x10000000 | 46 | #define PVR2_I_LMB_MASK 0x10000000 |
45 | #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 | 47 | #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 |
46 | #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 | 48 | #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 |
47 | #define PVR2_D_PLB_MASK 0x02000000 /* new */ | 49 | #define PVR2_D_PLB_MASK 0x02000000 /* new */ |
48 | #define PVR2_I_PLB_MASK 0x01000000 /* new */ | 50 | #define PVR2_I_PLB_MASK 0x01000000 /* new */ |
49 | #define PVR2_INTERCONNECT 0x00800000 /* new */ | 51 | #define PVR2_INTERCONNECT 0x00800000 /* new */ |
50 | #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ | 52 | #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ |
51 | #define PVR2_USE_FSL_EXC 0x00040000 /* new */ | 53 | #define PVR2_USE_FSL_EXC 0x00040000 /* new */ |
52 | #define PVR2_USE_MSR_INSTR 0x00020000 | 54 | #define PVR2_USE_MSR_INSTR 0x00020000 |
53 | #define PVR2_USE_PCMP_INSTR 0x00010000 | 55 | #define PVR2_USE_PCMP_INSTR 0x00010000 |
54 | #define PVR2_AREA_OPTIMISED 0x00008000 | 56 | #define PVR2_AREA_OPTIMISED 0x00008000 |
@@ -57,14 +59,14 @@ struct pvr_s { | |||
57 | #define PVR2_USE_HW_MUL_MASK 0x00001000 | 59 | #define PVR2_USE_HW_MUL_MASK 0x00001000 |
58 | #define PVR2_USE_FPU_MASK 0x00000800 | 60 | #define PVR2_USE_FPU_MASK 0x00000800 |
59 | #define PVR2_USE_MUL64_MASK 0x00000400 | 61 | #define PVR2_USE_MUL64_MASK 0x00000400 |
60 | #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ | 62 | #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ |
61 | #define PVR2_USE_IPLBEXC 0x00000100 | 63 | #define PVR2_USE_IPLBEXC 0x00000100 |
62 | #define PVR2_USE_DPLBEXC 0x00000080 | 64 | #define PVR2_USE_DPLBEXC 0x00000080 |
63 | #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 | 65 | #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 |
64 | #define PVR2_UNALIGNED_EXC_MASK 0x00000020 | 66 | #define PVR2_UNALIGNED_EXC_MASK 0x00000020 |
65 | #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 | 67 | #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 |
66 | #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 | 68 | #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 /* or AXI */ |
67 | #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 | 69 | #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 /* or AXI */ |
68 | #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 | 70 | #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 |
69 | #define PVR2_FPU_EXC_MASK 0x00000001 | 71 | #define PVR2_FPU_EXC_MASK 0x00000001 |
70 | 72 | ||
@@ -120,94 +122,103 @@ struct pvr_s { | |||
120 | 122 | ||
121 | 123 | ||
122 | /* PVR access macros */ | 124 | /* PVR access macros */ |
123 | #define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK) | 125 | #define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK) |
124 | #define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK) | 126 | #define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK) |
125 | #define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK) | 127 | #define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK) |
126 | #define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) | 128 | #define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) |
127 | #define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK) | 129 | #define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK) |
128 | #define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK) | 130 | #define PVR_USE_FPU2(_pvr) (_pvr.pvr[2] & PVR2_USE_FPU2_MASK) |
129 | #define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK) | 131 | #define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK) |
130 | #define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK) | 132 | #define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK) |
131 | #define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) | 133 | #define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) |
132 | #define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK) | 134 | #define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK) |
133 | #define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK) | 135 | #define PVR_USER2(_pvr) (_pvr.pvr[1] & PVR1_USER2_MASK) |
134 | 136 | ||
135 | #define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK) | 137 | #define PVR_D_OPB(_pvr) (_pvr.pvr[2] & PVR2_D_OPB_MASK) |
136 | #define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK) | 138 | #define PVR_D_LMB(_pvr) (_pvr.pvr[2] & PVR2_D_LMB_MASK) |
137 | #define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK) | 139 | #define PVR_I_OPB(_pvr) (_pvr.pvr[2] & PVR2_I_OPB_MASK) |
138 | #define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK) | 140 | #define PVR_I_LMB(_pvr) (_pvr.pvr[2] & PVR2_I_LMB_MASK) |
139 | #define PVR_INTERRUPT_IS_EDGE(pvr) \ | 141 | #define PVR_INTERRUPT_IS_EDGE(_pvr) \ |
140 | (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) | 142 | (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) |
141 | #define PVR_EDGE_IS_POSITIVE(pvr) \ | 143 | #define PVR_EDGE_IS_POSITIVE(_pvr) \ |
142 | (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) | 144 | (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) |
143 | #define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR) | 145 | #define PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_MSR_INSTR) |
144 | #define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR) | 146 | #define PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR) |
145 | #define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED) | 147 | #define PVR_AREA_OPTIMISED(_pvr) (_pvr.pvr[2] & PVR2_AREA_OPTIMISED) |
146 | #define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK) | 148 | #define PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & PVR2_USE_MUL64_MASK) |
147 | #define PVR_OPCODE_0x0_ILLEGAL(pvr) \ | 149 | #define PVR_OPCODE_0x0_ILLEGAL(_pvr) \ |
148 | (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) | 150 | (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) |
149 | #define PVR_UNALIGNED_EXCEPTION(pvr) \ | 151 | #define PVR_UNALIGNED_EXCEPTION(_pvr) \ |
150 | (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) | 152 | (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) |
151 | #define PVR_ILL_OPCODE_EXCEPTION(pvr) \ | 153 | #define PVR_ILL_OPCODE_EXCEPTION(_pvr) \ |
152 | (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) | 154 | (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) |
153 | #define PVR_IOPB_BUS_EXCEPTION(pvr) \ | 155 | #define PVR_IOPB_BUS_EXCEPTION(_pvr) \ |
154 | (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) | 156 | (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) |
155 | #define PVR_DOPB_BUS_EXCEPTION(pvr) \ | 157 | #define PVR_DOPB_BUS_EXCEPTION(_pvr) \ |
156 | (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) | 158 | (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) |
157 | #define PVR_DIV_ZERO_EXCEPTION(pvr) \ | 159 | #define PVR_DIV_ZERO_EXCEPTION(_pvr) \ |
158 | (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) | 160 | (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) |
159 | #define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK) | 161 | #define PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_FPU_EXC_MASK) |
160 | #define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL) | 162 | #define PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL) |
161 | 163 | ||
162 | #define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) | 164 | #define PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) |
163 | #define PVR_NUMBER_OF_PC_BRK(pvr) \ | 165 | #define PVR_NUMBER_OF_PC_BRK(_pvr) \ |
164 | ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) | 166 | ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) |
165 | #define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \ | 167 | #define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \ |
166 | ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) | 168 | ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) |
167 | #define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \ | 169 | #define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \ |
168 | ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) | 170 | ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) |
169 | #define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) | 171 | #define PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) |
170 | 172 | ||
171 | #define PVR_ICACHE_ADDR_TAG_BITS(pvr) \ | 173 | #define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \ |
172 | ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) | 174 | ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) |
173 | #define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) | 175 | #define PVR_ICACHE_USE_FSL(_pvr) \ |
174 | #define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) | 176 | (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) |
175 | #define PVR_ICACHE_LINE_LEN(pvr) \ | 177 | #define PVR_ICACHE_ALLOW_WR(_pvr) \ |
176 | (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) | 178 | (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) |
177 | #define PVR_ICACHE_BYTE_SIZE(pvr) \ | 179 | #define PVR_ICACHE_LINE_LEN(_pvr) \ |
178 | (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) | 180 | (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) |
179 | 181 | #define PVR_ICACHE_BYTE_SIZE(_pvr) \ | |
180 | #define PVR_DCACHE_ADDR_TAG_BITS(pvr) \ | 182 | (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) |
181 | ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) | 183 | |
182 | #define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) | 184 | #define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \ |
183 | #define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) | 185 | ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) |
186 | #define PVR_DCACHE_USE_FSL(_pvr) (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) | ||
187 | #define PVR_DCACHE_ALLOW_WR(_pvr) \ | ||
188 | (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) | ||
184 | /* FIXME two shifts on one line needs any comment */ | 189 | /* FIXME two shifts on one line needs any comment */ |
185 | #define PVR_DCACHE_LINE_LEN(pvr) \ | 190 | #define PVR_DCACHE_LINE_LEN(_pvr) \ |
186 | (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) | 191 | (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) |
187 | #define PVR_DCACHE_BYTE_SIZE(pvr) \ | 192 | #define PVR_DCACHE_BYTE_SIZE(_pvr) \ |
188 | (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) | 193 | (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) |
189 | 194 | ||
190 | #define PVR_DCACHE_USE_WRITEBACK(pvr) \ | 195 | #define PVR_DCACHE_USE_WRITEBACK(_pvr) \ |
191 | ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) | 196 | ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) |
192 | 197 | ||
193 | #define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) | 198 | #define PVR_ICACHE_BASEADDR(_pvr) \ |
194 | #define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) | 199 | (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) |
200 | #define PVR_ICACHE_HIGHADDR(_pvr) \ | ||
201 | (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) | ||
202 | #define PVR_DCACHE_BASEADDR(_pvr) \ | ||
203 | (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) | ||
204 | #define PVR_DCACHE_HIGHADDR(_pvr) \ | ||
205 | (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) | ||
195 | 206 | ||
196 | #define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) | 207 | #define PVR_TARGET_FAMILY(_pvr) \ |
197 | #define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) | 208 | ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) |
198 | 209 | ||
199 | #define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) | 210 | #define PVR_MSR_RESET_VALUE(_pvr) \ |
200 | 211 | (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK) | |
201 | #define PVR_MSR_RESET_VALUE(pvr) \ | ||
202 | (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK) | ||
203 | 212 | ||
204 | /* mmu */ | 213 | /* mmu */ |
205 | #define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30) | 214 | #define PVR_USE_MMU(_pvr) ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30) |
206 | #define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) | 215 | #define PVR_MMU_ITLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) |
207 | #define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) | 216 | #define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) |
208 | #define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) | 217 | #define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) |
209 | #define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES) | 218 | #define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES) |
210 | 219 | ||
220 | /* endian */ | ||
221 | #define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI) | ||
211 | 222 | ||
212 | int cpu_has_pvr(void); | 223 | int cpu_has_pvr(void); |
213 | void get_pvr(struct pvr_s *pvr); | 224 | void get_pvr(struct pvr_s *pvr); |
diff --git a/arch/microblaze/include/asm/seccomp.h b/arch/microblaze/include/asm/seccomp.h new file mode 100644 index 000000000000..0d912758a0d7 --- /dev/null +++ b/arch/microblaze/include/asm/seccomp.h | |||
@@ -0,0 +1,16 @@ | |||
1 | #ifndef _ASM_MICROBLAZE_SECCOMP_H | ||
2 | #define _ASM_MICROBLAZE_SECCOMP_H | ||
3 | |||
4 | #include <linux/unistd.h> | ||
5 | |||
6 | #define __NR_seccomp_read __NR_read | ||
7 | #define __NR_seccomp_write __NR_write | ||
8 | #define __NR_seccomp_exit __NR_exit | ||
9 | #define __NR_seccomp_sigreturn __NR_sigreturn | ||
10 | |||
11 | #define __NR_seccomp_read_32 __NR_read | ||
12 | #define __NR_seccomp_write_32 __NR_write | ||
13 | #define __NR_seccomp_exit_32 __NR_exit | ||
14 | #define __NR_seccomp_sigreturn_32 __NR_sigreturn | ||
15 | |||
16 | #endif /* _ASM_MICROBLAZE_SECCOMP_H */ | ||
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h index 782b5c89248e..8f3968971e4e 100644 --- a/arch/microblaze/include/asm/setup.h +++ b/arch/microblaze/include/asm/setup.h | |||
@@ -25,6 +25,12 @@ void early_printk(const char *fmt, ...); | |||
25 | int setup_early_printk(char *opt); | 25 | int setup_early_printk(char *opt); |
26 | void disable_early_printk(void); | 26 | void disable_early_printk(void); |
27 | 27 | ||
28 | #if defined(CONFIG_EARLY_PRINTK) | ||
29 | #define eprintk early_printk | ||
30 | #else | ||
31 | #define eprintk printk | ||
32 | #endif | ||
33 | |||
28 | void heartbeat(void); | 34 | void heartbeat(void); |
29 | void setup_heartbeat(void); | 35 | void setup_heartbeat(void); |
30 | 36 | ||
diff --git a/arch/microblaze/include/asm/syscall.h b/arch/microblaze/include/asm/syscall.h index 048dfcd8d89d..9bc431783105 100644 --- a/arch/microblaze/include/asm/syscall.h +++ b/arch/microblaze/include/asm/syscall.h | |||
@@ -96,4 +96,7 @@ static inline void syscall_set_arguments(struct task_struct *task, | |||
96 | microblaze_set_syscall_arg(regs, i++, *args++); | 96 | microblaze_set_syscall_arg(regs, i++, *args++); |
97 | } | 97 | } |
98 | 98 | ||
99 | asmlinkage long do_syscall_trace_enter(struct pt_regs *regs); | ||
100 | asmlinkage void do_syscall_trace_leave(struct pt_regs *regs); | ||
101 | |||
99 | #endif /* __ASM_MICROBLAZE_SYSCALL_H */ | 102 | #endif /* __ASM_MICROBLAZE_SYSCALL_H */ |
diff --git a/arch/microblaze/include/asm/syscalls.h b/arch/microblaze/include/asm/syscalls.h index 720761cc741f..27f2f4c0f39f 100644 --- a/arch/microblaze/include/asm/syscalls.h +++ b/arch/microblaze/include/asm/syscalls.h | |||
@@ -1,5 +1,13 @@ | |||
1 | #ifndef __ASM_MICROBLAZE_SYSCALLS_H | 1 | #ifndef __ASM_MICROBLAZE_SYSCALLS_H |
2 | 2 | ||
3 | asmlinkage long microblaze_vfork(struct pt_regs *regs); | ||
4 | asmlinkage long microblaze_clone(int flags, unsigned long stack, | ||
5 | struct pt_regs *regs); | ||
6 | asmlinkage long microblaze_execve(const char __user *filenamei, | ||
7 | const char __user *const __user *argv, | ||
8 | const char __user *const __user *envp, | ||
9 | struct pt_regs *regs); | ||
10 | |||
3 | asmlinkage long sys_clone(int flags, unsigned long stack, struct pt_regs *regs); | 11 | asmlinkage long sys_clone(int flags, unsigned long stack, struct pt_regs *regs); |
4 | #define sys_clone sys_clone | 12 | #define sys_clone sys_clone |
5 | 13 | ||
diff --git a/arch/microblaze/include/asm/thread_info.h b/arch/microblaze/include/asm/thread_info.h index 8a8e9fc6e0c0..b73da2ac21b3 100644 --- a/arch/microblaze/include/asm/thread_info.h +++ b/arch/microblaze/include/asm/thread_info.h | |||
@@ -127,23 +127,19 @@ static inline struct thread_info *current_thread_info(void) | |||
127 | #define TIF_SECCOMP 10 /* secure computing */ | 127 | #define TIF_SECCOMP 10 /* secure computing */ |
128 | #define TIF_FREEZE 14 /* Freezing for suspend */ | 128 | #define TIF_FREEZE 14 /* Freezing for suspend */ |
129 | 129 | ||
130 | /* FIXME change in entry.S */ | ||
131 | #define TIF_KERNEL_TRACE 8 /* kernel trace active */ | ||
132 | |||
133 | /* true if poll_idle() is polling TIF_NEED_RESCHED */ | 130 | /* true if poll_idle() is polling TIF_NEED_RESCHED */ |
134 | #define TIF_POLLING_NRFLAG 16 | 131 | #define TIF_POLLING_NRFLAG 16 |
135 | 132 | ||
136 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | 133 | #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) |
137 | #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) | 134 | #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) |
138 | #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) | 135 | #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) |
139 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) | 136 | #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) |
140 | #define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) | 137 | #define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) |
141 | #define _TIF_IRET (1<<TIF_IRET) | 138 | #define _TIF_IRET (1 << TIF_IRET) |
142 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | 139 | #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) |
143 | #define _TIF_FREEZE (1<<TIF_FREEZE) | 140 | #define _TIF_FREEZE (1 << TIF_FREEZE) |
144 | #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) | 141 | #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) |
145 | #define _TIF_SECCOMP (1 << TIF_SECCOMP) | 142 | #define _TIF_SECCOMP (1 << TIF_SECCOMP) |
146 | #define _TIF_KERNEL_TRACE (1 << TIF_KERNEL_TRACE) | ||
147 | 143 | ||
148 | /* work to do in syscall trace */ | 144 | /* work to do in syscall trace */ |
149 | #define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ | 145 | #define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \ |
diff --git a/arch/microblaze/include/asm/tlb.h b/arch/microblaze/include/asm/tlb.h index e8abd4a0349c..8aa97817cc8c 100644 --- a/arch/microblaze/include/asm/tlb.h +++ b/arch/microblaze/include/asm/tlb.h | |||
@@ -13,6 +13,7 @@ | |||
13 | 13 | ||
14 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) | 14 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) |
15 | 15 | ||
16 | #include <linux/pagemap.h> | ||
16 | #include <asm-generic/tlb.h> | 17 | #include <asm-generic/tlb.h> |
17 | 18 | ||
18 | #ifdef CONFIG_MMU | 19 | #ifdef CONFIG_MMU |
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h index d840f4a2d3c9..5bb95a11880d 100644 --- a/arch/microblaze/include/asm/uaccess.h +++ b/arch/microblaze/include/asm/uaccess.h | |||
@@ -120,16 +120,16 @@ static inline unsigned long __must_check __clear_user(void __user *to, | |||
120 | { | 120 | { |
121 | /* normal memset with two words to __ex_table */ | 121 | /* normal memset with two words to __ex_table */ |
122 | __asm__ __volatile__ ( \ | 122 | __asm__ __volatile__ ( \ |
123 | "1: sb r0, %2, r0;" \ | 123 | "1: sb r0, %1, r0;" \ |
124 | " addik %0, %0, -1;" \ | 124 | " addik %0, %0, -1;" \ |
125 | " bneid %0, 1b;" \ | 125 | " bneid %0, 1b;" \ |
126 | " addik %2, %2, 1;" \ | 126 | " addik %1, %1, 1;" \ |
127 | "2: " \ | 127 | "2: " \ |
128 | __EX_TABLE_SECTION \ | 128 | __EX_TABLE_SECTION \ |
129 | ".word 1b,2b;" \ | 129 | ".word 1b,2b;" \ |
130 | ".previous;" \ | 130 | ".previous;" \ |
131 | : "=r"(n) \ | 131 | : "=r"(n), "=r"(to) \ |
132 | : "0"(n), "r"(to) | 132 | : "0"(n), "1"(to) |
133 | ); | 133 | ); |
134 | return n; | 134 | return n; |
135 | } | 135 | } |
diff --git a/arch/microblaze/include/asm/unaligned.h b/arch/microblaze/include/asm/unaligned.h index 3658d91ac0fb..b162ed880495 100644 --- a/arch/microblaze/include/asm/unaligned.h +++ b/arch/microblaze/include/asm/unaligned.h | |||
@@ -12,12 +12,19 @@ | |||
12 | 12 | ||
13 | # ifdef __KERNEL__ | 13 | # ifdef __KERNEL__ |
14 | 14 | ||
15 | # include <linux/unaligned/be_struct.h> | 15 | # ifdef __MICROBLAZEEL__ |
16 | # include <linux/unaligned/le_byteshift.h> | 16 | # include <linux/unaligned/le_struct.h> |
17 | # include <linux/unaligned/generic.h> | 17 | # include <linux/unaligned/be_byteshift.h> |
18 | # define get_unaligned __get_unaligned_le | ||
19 | # define put_unaligned __put_unaligned_le | ||
20 | # else | ||
21 | # include <linux/unaligned/be_struct.h> | ||
22 | # include <linux/unaligned/le_byteshift.h> | ||
23 | # define get_unaligned __get_unaligned_be | ||
24 | # define put_unaligned __put_unaligned_be | ||
25 | # endif | ||
18 | 26 | ||
19 | # define get_unaligned __get_unaligned_be | 27 | # include <linux/unaligned/generic.h> |
20 | # define put_unaligned __put_unaligned_be | ||
21 | 28 | ||
22 | # endif /* __KERNEL__ */ | 29 | # endif /* __KERNEL__ */ |
23 | #endif /* _ASM_MICROBLAZE_UNALIGNED_H */ | 30 | #endif /* _ASM_MICROBLAZE_UNALIGNED_H */ |
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h index 2b67e92a773c..7d7092b917ac 100644 --- a/arch/microblaze/include/asm/unistd.h +++ b/arch/microblaze/include/asm/unistd.h | |||
@@ -383,8 +383,16 @@ | |||
383 | #define __NR_rt_tgsigqueueinfo 365 /* new */ | 383 | #define __NR_rt_tgsigqueueinfo 365 /* new */ |
384 | #define __NR_perf_event_open 366 /* new */ | 384 | #define __NR_perf_event_open 366 /* new */ |
385 | #define __NR_recvmmsg 367 /* new */ | 385 | #define __NR_recvmmsg 367 /* new */ |
386 | #define __NR_fanotify_init 368 | ||
387 | #define __NR_fanotify_mark 369 | ||
388 | #define __NR_prlimit64 370 | ||
389 | #define __NR_name_to_handle_at 371 | ||
390 | #define __NR_open_by_handle_at 372 | ||
391 | #define __NR_clock_adjtime 373 | ||
392 | #define __NR_syncfs 374 | ||
393 | #define __NR_setns 375 | ||
386 | 394 | ||
387 | #define __NR_syscalls 368 | 395 | #define __NR_syscalls 376 |
388 | 396 | ||
389 | #ifdef __KERNEL__ | 397 | #ifdef __KERNEL__ |
390 | #ifndef __ASSEMBLY__ | 398 | #ifndef __ASSEMBLY__ |