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-rw-r--r--arch/m68k/Kconfig.cpu3
-rw-r--r--arch/m68k/Makefile6
-rw-r--r--arch/m68k/include/asm/m5249sim.h269
-rw-r--r--arch/m68k/include/asm/m525xsim.h116
-rw-r--r--arch/m68k/include/asm/mcfclk.h9
-rw-r--r--arch/m68k/include/asm/mcfsim.h5
-rw-r--r--arch/m68k/include/asm/page_no.h2
-rw-r--r--arch/m68k/lib/memcpy.c3
-rw-r--r--arch/m68k/platform/68000/Makefile18
-rw-r--r--arch/m68k/platform/68000/bootlogo-vz.h (renamed from arch/m68k/platform/68VZ328/bootlogo.h)0
-rw-r--r--arch/m68k/platform/68000/bootlogo.h (renamed from arch/m68k/platform/68328/bootlogo.h)0
-rw-r--r--arch/m68k/platform/68000/entry.S (renamed from arch/m68k/platform/68328/entry.S)0
-rw-r--r--arch/m68k/platform/68000/head.S240
-rw-r--r--arch/m68k/platform/68000/ints.c (renamed from arch/m68k/platform/68328/ints.c)2
-rw-r--r--arch/m68k/platform/68000/m68328.c (renamed from arch/m68k/platform/68328/config.c)2
-rw-r--r--arch/m68k/platform/68000/m68EZ328.c (renamed from arch/m68k/platform/68EZ328/config.c)2
-rw-r--r--arch/m68k/platform/68000/m68VZ328.c (renamed from arch/m68k/platform/68VZ328/config.c)4
-rw-r--r--arch/m68k/platform/68000/romvec.S (renamed from arch/m68k/platform/68328/romvec.S)2
-rw-r--r--arch/m68k/platform/68000/timers.c (renamed from arch/m68k/platform/68328/timers.c)2
-rw-r--r--arch/m68k/platform/68328/Makefile21
-rw-r--r--arch/m68k/platform/68328/head-de2.S128
-rw-r--r--arch/m68k/platform/68328/head-pilot.S207
-rw-r--r--arch/m68k/platform/68328/head-ram.S141
-rw-r--r--arch/m68k/platform/68328/head-rom.S105
-rw-r--r--arch/m68k/platform/68EZ328/Makefile5
-rw-r--r--arch/m68k/platform/68VZ328/Makefile5
-rw-r--r--arch/m68k/platform/coldfire/clk.c100
-rw-r--r--arch/m68k/platform/coldfire/intc-5249.c8
-rw-r--r--arch/m68k/platform/coldfire/m5206.c20
-rw-r--r--arch/m68k/platform/coldfire/m523x.c28
-rw-r--r--arch/m68k/platform/coldfire/m5249.c28
-rw-r--r--arch/m68k/platform/coldfire/m525x.c20
-rw-r--r--arch/m68k/platform/coldfire/m5272.c26
-rw-r--r--arch/m68k/platform/coldfire/m527x.c30
-rw-r--r--arch/m68k/platform/coldfire/m528x.c28
-rw-r--r--arch/m68k/platform/coldfire/m5307.c20
-rw-r--r--arch/m68k/platform/coldfire/m5407.c20
-rw-r--r--arch/m68k/platform/coldfire/m54xx.c26
38 files changed, 680 insertions, 971 deletions
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index 2f2d87b40341..b1cfff832fb5 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -35,7 +35,8 @@ endchoice
35if M68KCLASSIC 35if M68KCLASSIC
36 36
37config M68000 37config M68000
38 bool 38 bool "MC68000"
39 depends on !MMU
39 select CPU_HAS_NO_BITFIELDS 40 select CPU_HAS_NO_BITFIELDS
40 select CPU_HAS_NO_MULDIV64 41 select CPU_HAS_NO_MULDIV64
41 select CPU_HAS_NO_UNALIGNED 42 select CPU_HAS_NO_UNALIGNED
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 7636751f2f87..2f02acfb8edf 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -92,7 +92,7 @@ endif
92head-y := arch/m68k/kernel/head.o 92head-y := arch/m68k/kernel/head.o
93head-$(CONFIG_SUN3) := arch/m68k/kernel/sun3-head.o 93head-$(CONFIG_SUN3) := arch/m68k/kernel/sun3-head.o
94head-$(CONFIG_M68360) := arch/m68k/platform/68360/head.o 94head-$(CONFIG_M68360) := arch/m68k/platform/68360/head.o
95head-$(CONFIG_M68000) := arch/m68k/platform/68328/head.o 95head-$(CONFIG_M68000) := arch/m68k/platform/68000/head.o
96head-$(CONFIG_COLDFIRE) := arch/m68k/platform/coldfire/head.o 96head-$(CONFIG_COLDFIRE) := arch/m68k/platform/coldfire/head.o
97 97
98core-y += arch/m68k/kernel/ arch/m68k/mm/ 98core-y += arch/m68k/kernel/ arch/m68k/mm/
@@ -114,9 +114,7 @@ core-$(CONFIG_M68040) += arch/m68k/fpsp040/
114core-$(CONFIG_M68060) += arch/m68k/ifpsp060/ 114core-$(CONFIG_M68060) += arch/m68k/ifpsp060/
115core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/ 115core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/
116core-$(CONFIG_M68360) += arch/m68k/platform/68360/ 116core-$(CONFIG_M68360) += arch/m68k/platform/68360/
117core-$(CONFIG_M68000) += arch/m68k/platform/68328/ 117core-$(CONFIG_M68000) += arch/m68k/platform/68000/
118core-$(CONFIG_M68EZ328) += arch/m68k/platform/68EZ328/
119core-$(CONFIG_M68VZ328) += arch/m68k/platform/68VZ328/
120core-$(CONFIG_COLDFIRE) += arch/m68k/platform/coldfire/ 118core-$(CONFIG_COLDFIRE) += arch/m68k/platform/coldfire/
121 119
122 120
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
deleted file mode 100644
index fdf45e6807c9..000000000000
--- a/arch/m68k/include/asm/m5249sim.h
+++ /dev/null
@@ -1,269 +0,0 @@
1/****************************************************************************/
2
3/*
4 * m5249sim.h -- ColdFire 5249 System Integration Module support.
5 *
6 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m5249sim_h
11#define m5249sim_h
12/****************************************************************************/
13
14#define CPU_NAME "COLDFIRE(m5249)"
15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
17
18#include <asm/m52xxacr.h>
19
20/*
21 * The 5249 has a second MBAR region, define its address.
22 */
23#define MCF_MBAR2 0x80000000
24
25/*
26 * Define the 5249 SIM register set addresses.
27 */
28#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
29#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
30#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
31#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
32#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
33#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
34#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
36#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
37#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
38#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
39#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
40#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
41#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
42#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
43#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
44#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
45#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
46#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
47#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
48#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
49#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
50
51#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
57#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
58#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
59#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
60#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
61#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
62#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
63
64#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
65#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
66#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
67#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
68#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
69
70/*
71 * Timer module.
72 */
73#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
74#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
75
76/*
77 * UART module.
78 */
79#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
80#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
81
82/*
83 * QSPI module.
84 */
85#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
86#define MCFQSPI_SIZE 0x40 /* Register set size */
87
88#define MCFQSPI_CS0 29
89#define MCFQSPI_CS1 24
90#define MCFQSPI_CS2 21
91#define MCFQSPI_CS3 22
92
93/*
94 * DMA unit base addresses.
95 */
96#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
97#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
98#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
99#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
100
101/*
102 * Some symbol defines for the above...
103 */
104#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
105#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
106#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
107#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
108#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
109#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
110#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
111#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
112#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
113#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
114
115/*
116 * Define system peripheral IRQ usage.
117 */
118#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
119#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
120#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
121
122#define MCF_IRQ_UART0 73 /* UART0 */
123#define MCF_IRQ_UART1 74 /* UART1 */
124
125/*
126 * General purpose IO registers (in MBAR2).
127 */
128#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
129#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
130#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
131#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
132#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
133#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
134#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
135#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
136
137#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
138#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
139#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
140
141#define MCFSIM2_INTLEVEL1 (MCF_MBAR2 + 0x140) /* Intr level reg 1 */
142#define MCFSIM2_INTLEVEL2 (MCF_MBAR2 + 0x144) /* Intr level reg 2 */
143#define MCFSIM2_INTLEVEL3 (MCF_MBAR2 + 0x148) /* Intr level reg 3 */
144#define MCFSIM2_INTLEVEL4 (MCF_MBAR2 + 0x14c) /* Intr level reg 4 */
145#define MCFSIM2_INTLEVEL5 (MCF_MBAR2 + 0x150) /* Intr level reg 5 */
146#define MCFSIM2_INTLEVEL6 (MCF_MBAR2 + 0x154) /* Intr level reg 6 */
147#define MCFSIM2_INTLEVEL7 (MCF_MBAR2 + 0x158) /* Intr level reg 7 */
148#define MCFSIM2_INTLEVEL8 (MCF_MBAR2 + 0x15c) /* Intr level reg 8 */
149
150#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
151
152#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
153#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
154
155/*
156 * Define the base interrupt for the second interrupt controller.
157 * We set it to 128, out of the way of the base interrupts, and plenty
158 * of room for its 64 interrupts.
159 */
160#define MCFINTC2_VECBASE 128
161
162#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32)
163#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33)
164#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34)
165#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35)
166#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36)
167#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37)
168#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38)
169#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39)
170
171/*
172 * Generic GPIO support
173 */
174#define MCFGPIO_PIN_MAX 64
175#define MCFGPIO_IRQ_MAX -1
176#define MCFGPIO_IRQ_VECBASE -1
177
178/****************************************************************************/
179
180#ifdef __ASSEMBLER__
181
182/*
183 * The M5249C3 board needs a little help getting all its SIM devices
184 * initialized at kernel start time. dBUG doesn't set much up, so
185 * we need to do it manually.
186 */
187.macro m5249c3_setup
188 /*
189 * Set MBAR1 and MBAR2, just incase they are not set.
190 */
191 movel #0x10000001,%a0
192 movec %a0,%MBAR /* map MBAR region */
193 subql #1,%a0 /* get MBAR address in a0 */
194
195 movel #0x80000001,%a1
196 movec %a1,#3086 /* map MBAR2 region */
197 subql #1,%a1 /* get MBAR2 address in a1 */
198
199 /*
200 * Move secondary interrupts to their base (128).
201 */
202 moveb #MCFINTC2_VECBASE,%d0
203 moveb %d0,0x16b(%a1) /* interrupt base register */
204
205 /*
206 * Work around broken CSMR0/DRAM vector problem.
207 */
208 movel #0x001F0021,%d0 /* disable C/I bit */
209 movel %d0,0x84(%a0) /* set CSMR0 */
210
211 /*
212 * Disable the PLL firstly. (Who knows what state it is
213 * in here!).
214 */
215 movel 0x180(%a1),%d0 /* get current PLL value */
216 andl #0xfffffffe,%d0 /* PLL bypass first */
217 movel %d0,0x180(%a1) /* set PLL register */
218 nop
219
220#if CONFIG_CLOCK_FREQ == 140000000
221 /*
222 * Set initial clock frequency. This assumes M5249C3 board
223 * is fitted with 11.2896MHz crystal. It will program the
224 * PLL for 140MHz. Lets go fast :-)
225 */
226 movel #0x125a40f0,%d0 /* set for 140MHz */
227 movel %d0,0x180(%a1) /* set PLL register */
228 orl #0x1,%d0
229 movel %d0,0x180(%a1) /* set PLL register */
230#endif
231
232 /*
233 * Setup CS1 for ethernet controller.
234 * (Setup as per M5249C3 doco).
235 */
236 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
237 movel %d0,0x8c(%a0)
238 movel #0x001f0021,%d0 /* CS1 size of 1Mb */
239 movel %d0,0x90(%a0)
240 movew #0x0080,%d0 /* CS1 = 16bit port, AA */
241 movew %d0,0x96(%a0)
242
243 /*
244 * Setup CS2 for IDE interface.
245 */
246 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
247 movel %d0,0x98(%a0)
248 movel #0x001f0001,%d0 /* CS2 size of 1MB */
249 movel %d0,0x9c(%a0)
250 movew #0x0080,%d0 /* CS2 = 16bit, TA */
251 movew %d0,0xa2(%a0)
252
253 movel #0x00107000,%d0 /* IDEconfig1 */
254 movel %d0,0x18c(%a1)
255 movel #0x000c0400,%d0 /* IDEconfig2 */
256 movel %d0,0x190(%a1)
257
258 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
259 orl %d0,0xc(%a1) /* function GPIO19 */
260 orl %d0,0x8(%a1) /* enable GPIO19 as output */
261 orl %d0,0x4(%a1) /* de-assert IDE reset */
262.endm
263
264#define PLATFORM_SETUP m5249c3_setup
265
266#endif /* __ASSEMBLER__ */
267
268/****************************************************************************/
269#endif /* m5249sim_h */
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
index acab61cb91ed..e33f5bb6aca8 100644
--- a/arch/m68k/include/asm/m525xsim.h
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -12,6 +12,11 @@
12#define m525xsim_h 12#define m525xsim_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15/*
16 * This header supports ColdFire 5249, 5251 and 5253. There are a few
17 * little differences between them, but most of the peripheral support
18 * can be used by all of them.
19 */
15#define CPU_NAME "COLDFIRE(m525x)" 20#define CPU_NAME "COLDFIRE(m525x)"
16#define CPU_INSTR_PER_JIFFY 3 21#define CPU_INSTR_PER_JIFFY 3
17#define MCF_BUSCLK (MCF_CLK / 2) 22#define MCF_BUSCLK (MCF_CLK / 2)
@@ -65,6 +70,8 @@
65#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 70#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
66#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 71#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
67#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ 72#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
73#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
74#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
68 75
69/* 76/*
70 * Secondary Interrupt Controller (in MBAR2) 77 * Secondary Interrupt Controller (in MBAR2)
@@ -101,11 +108,17 @@
101#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */ 108#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
102#define MCFQSPI_SIZE 0x40 /* Register set size */ 109#define MCFQSPI_SIZE 0x40 /* Register set size */
103 110
104 111#ifdef CONFIG_M5249
112#define MCFQSPI_CS0 29
113#define MCFQSPI_CS1 24
114#define MCFQSPI_CS2 21
115#define MCFQSPI_CS3 22
116#else
105#define MCFQSPI_CS0 15 117#define MCFQSPI_CS0 15
106#define MCFQSPI_CS1 16 118#define MCFQSPI_CS1 16
107#define MCFQSPI_CS2 24 119#define MCFQSPI_CS2 24
108#define MCFQSPI_CS3 28 120#define MCFQSPI_CS3 28
121#endif
109 122
110/* 123/*
111 * I2C module. 124 * I2C module.
@@ -115,6 +128,7 @@
115 128
116#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */ 129#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
117#define MCFI2C_SIZE1 0x20 /* Register set size */ 130#define MCFI2C_SIZE1 0x20 /* Register set size */
131
118/* 132/*
119 * DMA unit base addresses. 133 * DMA unit base addresses.
120 */ 134 */
@@ -163,6 +177,7 @@
163#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36) 177#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
164#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37) 178#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
165#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38) 179#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
180#define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39)
166 181
167#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40) 182#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
168#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62) 183#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
@@ -183,12 +198,111 @@
183#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */ 198#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
184#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */ 199#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
185 200
201#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
202#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
203#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
204
186/* 205/*
187 * Generic GPIO support 206 * Generic GPIO support
188 */ 207 */
189#define MCFGPIO_PIN_MAX 64 208#define MCFGPIO_PIN_MAX 64
209#ifdef CONFIG_M5249
210#define MCFGPIO_IRQ_MAX -1
211#define MCFGPIO_IRQ_VECBASE -1
212#else
190#define MCFGPIO_IRQ_MAX 7 213#define MCFGPIO_IRQ_MAX 7
191#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0 214#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
215#endif
216
217/****************************************************************************/
218
219#ifdef __ASSEMBLER__
220#ifdef CONFIG_M5249C3
221/*
222 * The M5249C3 board needs a little help getting all its SIM devices
223 * initialized at kernel start time. dBUG doesn't set much up, so
224 * we need to do it manually.
225 */
226.macro m5249c3_setup
227 /*
228 * Set MBAR1 and MBAR2, just incase they are not set.
229 */
230 movel #0x10000001,%a0
231 movec %a0,%MBAR /* map MBAR region */
232 subql #1,%a0 /* get MBAR address in a0 */
233
234 movel #0x80000001,%a1
235 movec %a1,#3086 /* map MBAR2 region */
236 subql #1,%a1 /* get MBAR2 address in a1 */
237
238 /*
239 * Move secondary interrupts to their base (128).
240 */
241 moveb #MCFINTC2_VECBASE,%d0
242 moveb %d0,0x16b(%a1) /* interrupt base register */
243
244 /*
245 * Work around broken CSMR0/DRAM vector problem.
246 */
247 movel #0x001F0021,%d0 /* disable C/I bit */
248 movel %d0,0x84(%a0) /* set CSMR0 */
249
250 /*
251 * Disable the PLL firstly. (Who knows what state it is
252 * in here!).
253 */
254 movel 0x180(%a1),%d0 /* get current PLL value */
255 andl #0xfffffffe,%d0 /* PLL bypass first */
256 movel %d0,0x180(%a1) /* set PLL register */
257 nop
258
259#if CONFIG_CLOCK_FREQ == 140000000
260 /*
261 * Set initial clock frequency. This assumes M5249C3 board
262 * is fitted with 11.2896MHz crystal. It will program the
263 * PLL for 140MHz. Lets go fast :-)
264 */
265 movel #0x125a40f0,%d0 /* set for 140MHz */
266 movel %d0,0x180(%a1) /* set PLL register */
267 orl #0x1,%d0
268 movel %d0,0x180(%a1) /* set PLL register */
269#endif
270
271 /*
272 * Setup CS1 for ethernet controller.
273 * (Setup as per M5249C3 doco).
274 */
275 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
276 movel %d0,0x8c(%a0)
277 movel #0x001f0021,%d0 /* CS1 size of 1Mb */
278 movel %d0,0x90(%a0)
279 movew #0x0080,%d0 /* CS1 = 16bit port, AA */
280 movew %d0,0x96(%a0)
281
282 /*
283 * Setup CS2 for IDE interface.
284 */
285 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
286 movel %d0,0x98(%a0)
287 movel #0x001f0001,%d0 /* CS2 size of 1MB */
288 movel %d0,0x9c(%a0)
289 movew #0x0080,%d0 /* CS2 = 16bit, TA */
290 movew %d0,0xa2(%a0)
291
292 movel #0x00107000,%d0 /* IDEconfig1 */
293 movel %d0,0x18c(%a1)
294 movel #0x000c0400,%d0 /* IDEconfig2 */
295 movel %d0,0x190(%a1)
296
297 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
298 orl %d0,0xc(%a1) /* function GPIO19 */
299 orl %d0,0x8(%a1) /* enable GPIO19 as output */
300 orl %d0,0x4(%a1) /* de-assert IDE reset */
301.endm
302
303#define PLATFORM_SETUP m5249c3_setup
192 304
305#endif /* CONFIG_M5249C3 */
306#endif /* __ASSEMBLER__ */
193/****************************************************************************/ 307/****************************************************************************/
194#endif /* m525xsim_h */ 308#endif /* m525xsim_h */
diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h
index b676a02bb392..ea4791e3a557 100644
--- a/arch/m68k/include/asm/mcfclk.h
+++ b/arch/m68k/include/asm/mcfclk.h
@@ -8,7 +8,6 @@
8 8
9struct clk; 9struct clk;
10 10
11#ifdef MCFPM_PPMCR0
12struct clk_ops { 11struct clk_ops {
13 void (*enable)(struct clk *); 12 void (*enable)(struct clk *);
14 void (*disable)(struct clk *); 13 void (*disable)(struct clk *);
@@ -23,6 +22,8 @@ struct clk {
23}; 22};
24 23
25extern struct clk *mcf_clks[]; 24extern struct clk *mcf_clks[];
25
26#ifdef MCFPM_PPMCR0
26extern struct clk_ops clk_ops0; 27extern struct clk_ops clk_ops0;
27#ifdef MCFPM_PPMCR1 28#ifdef MCFPM_PPMCR1
28extern struct clk_ops clk_ops1; 29extern struct clk_ops clk_ops1;
@@ -38,6 +39,12 @@ static struct clk __clk_##clk_bank##_##clk_slot = { \
38 39
39void __clk_init_enabled(struct clk *); 40void __clk_init_enabled(struct clk *);
40void __clk_init_disabled(struct clk *); 41void __clk_init_disabled(struct clk *);
42#else
43#define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
44 static struct clk clk_##clk_ref = { \
45 .name = clk_name, \
46 .rate = clk_rate, \
47 }
41#endif /* MCFPM_PPMCR0 */ 48#endif /* MCFPM_PPMCR0 */
42 49
43#endif /* mcfclk_h */ 50#endif /* mcfclk_h */
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index 7a83e619e73b..a04fd9b2714c 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -24,10 +24,7 @@
24#elif defined(CONFIG_M523x) 24#elif defined(CONFIG_M523x)
25#include <asm/m523xsim.h> 25#include <asm/m523xsim.h>
26#include <asm/mcfintc.h> 26#include <asm/mcfintc.h>
27#elif defined(CONFIG_M5249) 27#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
28#include <asm/m5249sim.h>
29#include <asm/mcfintc.h>
30#elif defined(CONFIG_M525x)
31#include <asm/m525xsim.h> 28#include <asm/m525xsim.h>
32#include <asm/mcfintc.h> 29#include <asm/mcfintc.h>
33#elif defined(CONFIG_M527x) 30#elif defined(CONFIG_M527x)
diff --git a/arch/m68k/include/asm/page_no.h b/arch/m68k/include/asm/page_no.h
index 90595721185f..ef209169579a 100644
--- a/arch/m68k/include/asm/page_no.h
+++ b/arch/m68k/include/asm/page_no.h
@@ -26,7 +26,7 @@ extern unsigned long memory_end;
26#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) 26#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
27 27
28#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) 28#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
29#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) 29#define page_to_virt(page) __va(((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET))
30 30
31#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) 31#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn))
32#define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) 32#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))
diff --git a/arch/m68k/lib/memcpy.c b/arch/m68k/lib/memcpy.c
index 10ca051d56b8..c1e2dfb206f3 100644
--- a/arch/m68k/lib/memcpy.c
+++ b/arch/m68k/lib/memcpy.c
@@ -10,7 +10,7 @@
10void *memcpy(void *to, const void *from, size_t n) 10void *memcpy(void *to, const void *from, size_t n)
11{ 11{
12 void *xto = to; 12 void *xto = to;
13 size_t temp, temp1; 13 size_t temp;
14 14
15 if (!n) 15 if (!n)
16 return xto; 16 return xto;
@@ -47,6 +47,7 @@ void *memcpy(void *to, const void *from, size_t n)
47 for (; temp; temp--) 47 for (; temp; temp--)
48 *lto++ = *lfrom++; 48 *lto++ = *lfrom++;
49#else 49#else
50 size_t temp1;
50 asm volatile ( 51 asm volatile (
51 " movel %2,%3\n" 52 " movel %2,%3\n"
52 " andw #7,%3\n" 53 " andw #7,%3\n"
diff --git a/arch/m68k/platform/68000/Makefile b/arch/m68k/platform/68000/Makefile
new file mode 100644
index 000000000000..1eab70c7194b
--- /dev/null
+++ b/arch/m68k/platform/68000/Makefile
@@ -0,0 +1,18 @@
1##################################################
2#
3# Makefile for 68000 core based cpus
4#
5# 2012.10.21, Luis Alves <ljalvs@gmail.com>
6# Merged all 68000 based cpu's config
7# files into a single directory.
8#
9
10# 68328, 68EZ328, 68VZ328
11
12obj-y += entry.o ints.o timers.o
13obj-$(CONFIG_M68328) += m68328.o
14obj-$(CONFIG_M68EZ328) += m68EZ328.o
15obj-$(CONFIG_M68VZ328) += m68VZ328.o
16obj-$(CONFIG_ROM) += romvec.o
17
18extra-y := head.o
diff --git a/arch/m68k/platform/68VZ328/bootlogo.h b/arch/m68k/platform/68000/bootlogo-vz.h
index b38e2b255142..b38e2b255142 100644
--- a/arch/m68k/platform/68VZ328/bootlogo.h
+++ b/arch/m68k/platform/68000/bootlogo-vz.h
diff --git a/arch/m68k/platform/68328/bootlogo.h b/arch/m68k/platform/68000/bootlogo.h
index b896c933fafc..b896c933fafc 100644
--- a/arch/m68k/platform/68328/bootlogo.h
+++ b/arch/m68k/platform/68000/bootlogo.h
diff --git a/arch/m68k/platform/68328/entry.S b/arch/m68k/platform/68000/entry.S
index 7f91c2fde509..7f91c2fde509 100644
--- a/arch/m68k/platform/68328/entry.S
+++ b/arch/m68k/platform/68000/entry.S
diff --git a/arch/m68k/platform/68000/head.S b/arch/m68k/platform/68000/head.S
new file mode 100644
index 000000000000..536ef9616dad
--- /dev/null
+++ b/arch/m68k/platform/68000/head.S
@@ -0,0 +1,240 @@
1/*
2 * head.S - Common startup code for 68000 core based CPU's
3 *
4 * 2012.10.21, Luis Alves <ljalvs@gmail.com>, Single head.S file for all
5 * 68000 core based CPU's. Based on the sources from:
6 * Coldfire by Greg Ungerer <gerg@snapgear.com>
7 * 68328 by D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
8 * Kenneth Albanowski <kjahds@kjahds.com>,
9 * The Silver Hammer Group, Ltd.
10 *
11 */
12
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <asm/asm-offsets.h>
16#include <asm/thread_info.h>
17
18
19/*****************************************************************************
20 * UCSIMM and UCDIMM use CONFIG_MEMORY_RESERVE to reserve some RAM
21 *****************************************************************************/
22#ifdef CONFIG_MEMORY_RESERVE
23#define RAMEND (CONFIG_RAMBASE+CONFIG_RAMSIZE)-(CONFIG_MEMORY_RESERVE*0x100000)
24#else
25#define RAMEND (CONFIG_RAMBASE+CONFIG_RAMSIZE)
26#endif
27/*****************************************************************************/
28
29.global _start
30.global _rambase
31.global _ramvec
32.global _ramstart
33.global _ramend
34
35#if defined(CONFIG_PILOT) || defined(CONFIG_INIT_LCD)
36.global bootlogo_bits
37#endif
38
39/* Defining DEBUG_HEAD_CODE, serial port in 68x328 is inited */
40/* #define DEBUG_HEAD_CODE */
41#undef DEBUG_HEAD_CODE
42
43.data
44
45/*****************************************************************************
46 * RAM setup pointers. Used by the kernel to determine RAM location and size.
47 *****************************************************************************/
48
49_rambase:
50 .long 0
51_ramvec:
52 .long 0
53_ramstart:
54 .long 0
55_ramend:
56 .long 0
57
58__HEAD
59
60/*****************************************************************************
61 * Entry point, where all begins!
62 *****************************************************************************/
63
64_start:
65
66/* Pilot need this specific signature at the start of ROM */
67#ifdef CONFIG_PILOT
68 .byte 0x4e, 0xfa, 0x00, 0x0a /* bra opcode (jmp 10 bytes) */
69 .byte 'b', 'o', 'o', 't'
70 .word 10000
71 nop
72 moveq #0, %d0
73 movew %d0, 0xfffff618 /* Watchdog off */
74 movel #0x00011f07, 0xfffff114 /* CS A1 Mask */
75#endif /* CONFIG_PILOT */
76
77 movew #0x2700, %sr /* disable all interrupts */
78
79/*****************************************************************************
80 * Setup PLL and wait for it to settle (in 68x328 cpu's).
81 * Also, if enabled, init serial port.
82 *****************************************************************************/
83#if defined(CONFIG_M68328) || \
84 defined(CONFIG_M68EZ328) || \
85 defined(CONFIG_M68VZ328)
86
87/* Serial port setup. Should only be needed if debugging this startup code. */
88#ifdef DEBUG_HEAD_CODE
89 movew #0x0800, 0xfffff906 /* Ignore CTS */
90 movew #0x010b, 0xfffff902 /* BAUD to 9600 */
91 movew #0xe100, 0xfffff900 /* enable */
92#endif /* DEBUG_HEAD */
93
94#ifdef CONFIG_PILOT
95 movew #0x2410, 0xfffff200 /* PLLCR */
96#else
97 movew #0x2400, 0xfffff200 /* PLLCR */
98#endif
99 movew #0x0123, 0xfffff202 /* PLLFSR */
100 moveq #0, %d0
101 movew #16384, %d0 /* PLL settle wait loop */
102_pll_settle:
103 subw #1, %d0
104 bne _pll_settle
105#endif /* CONFIG_M68x328 */
106
107
108/*****************************************************************************
109 * If running kernel from ROM some specific initialization has to be done.
110 * (Assuming that everything is already init'ed when running from RAM)
111 *****************************************************************************/
112#ifdef CONFIG_ROMKERNEL
113
114/*****************************************************************************
115 * Init chip registers (uCsimm specific)
116 *****************************************************************************/
117#ifdef CONFIG_UCSIMM
118 moveb #0x00, 0xfffffb0b /* Watchdog off */
119 moveb #0x10, 0xfffff000 /* SCR */
120 moveb #0x00, 0xfffff40b /* enable chip select */
121 moveb #0x00, 0xfffff423 /* enable /DWE */
122 moveb #0x08, 0xfffffd0d /* disable hardmap */
123 moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */
124 movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */
125 movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */
126 movew #0x8f00, 0xfffffc00 /* DRAM configuration */
127 movew #0x9667, 0xfffffc02 /* DRAM control */
128 movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */
129 movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */
130 moveb #0x40, 0xfffff300 /* IVR */
131 movel #0x007FFFFF, %d0 /* IMR */
132 movel %d0, 0xfffff304
133 moveb 0xfffff42b, %d0
134 andb #0xe0, %d0
135 moveb %d0, 0xfffff42b
136#endif
137
138/*****************************************************************************
139 * Init LCD controller.
140 * (Assuming that LCD controller is already init'ed when running from RAM)
141 *****************************************************************************/
142#ifdef CONFIG_INIT_LCD
143#ifdef CONFIG_PILOT
144 moveb #0, 0xfffffA27 /* LCKCON */
145 movel #_start, 0xfffffA00 /* LSSA */
146 moveb #0xa, 0xfffffA05 /* LVPW */
147 movew #0x9f, 0xFFFFFa08 /* LXMAX */
148 movew #0x9f, 0xFFFFFa0a /* LYMAX */
149 moveb #9, 0xfffffa29 /* LBAR */
150 moveb #0, 0xfffffa25 /* LPXCD */
151 moveb #0x04, 0xFFFFFa20 /* LPICF */
152 moveb #0x58, 0xfffffA27 /* LCKCON */
153 moveb #0x85, 0xfffff429 /* PFDATA */
154 moveb #0xd8, 0xfffffA27 /* LCKCON */
155 moveb #0xc5, 0xfffff429 /* PFDATA */
156 moveb #0xd5, 0xfffff429 /* PFDATA */
157 movel #bootlogo_bits, 0xFFFFFA00 /* LSSA */
158 moveb #10, 0xFFFFFA05 /* LVPW */
159 movew #160, 0xFFFFFA08 /* LXMAX */
160 movew #160, 0xFFFFFA0A /* LYMAX */
161#else /* CONFIG_PILOT */
162 movel #bootlogo_bits, 0xfffffA00 /* LSSA */
163 moveb #0x28, 0xfffffA05 /* LVPW */
164 movew #0x280, 0xFFFFFa08 /* LXMAX */
165 movew #0x1df, 0xFFFFFa0a /* LYMAX */
166 moveb #0, 0xfffffa29 /* LBAR */
167 moveb #0, 0xfffffa25 /* LPXCD */
168 moveb #0x08, 0xFFFFFa20 /* LPICF */
169 moveb #0x01, 0xFFFFFA21 /* -ve pol */
170 moveb #0x81, 0xfffffA27 /* LCKCON */
171 movew #0xff00, 0xfffff412 /* LCD pins */
172#endif /* CONFIG_PILOT */
173#endif /* CONFIG_INIT_LCD */
174
175/*****************************************************************************
176 * Kernel is running from FLASH/ROM (XIP)
177 * Copy init text & data to RAM
178 *****************************************************************************/
179 moveal #_etext, %a0
180 moveal #_sdata, %a1
181 moveal #__bss_start, %a2
182_copy_initmem:
183 movel %a0@+, %a1@+
184 cmpal %a1, %a2
185 bhi _copy_initmem
186#endif /* CONFIG_ROMKERNEL */
187
188/*****************************************************************************
189 * Setup basic memory information for kernel
190 *****************************************************************************/
191 movel #CONFIG_VECTORBASE,_ramvec /* set vector base location */
192 movel #CONFIG_RAMBASE,_rambase /* set the base of RAM */
193 movel #RAMEND, _ramend /* set end ram addr */
194 lea __bss_stop,%a1
195 movel %a1,_ramstart
196
197/*****************************************************************************
198 * If the kernel is in RAM, move romfs to right above bss and
199 * adjust _ramstart to where romfs ends.
200 *
201 * (Do this only if CONFIG_MTD_UCLINUX is true)
202 *****************************************************************************/
203
204#if defined(CONFIG_ROMFS_FS) && defined(CONFIG_RAMKERNEL) && \
205 defined(CONFIG_MTD_UCLINUX)
206 lea __bss_start, %a0 /* get start of bss */
207 lea __bss_stop, %a1 /* set up destination */
208 movel %a0, %a2 /* copy of bss start */
209
210 movel 8(%a0), %d0 /* get size of ROMFS */
211 addql #8, %d0 /* allow for rounding */
212 andl #0xfffffffc, %d0 /* whole words */
213
214 addl %d0, %a0 /* copy from end */
215 addl %d0, %a1 /* copy from end */
216 movel %a1, _ramstart /* set start of ram */
217_copy_romfs:
218 movel -(%a0), -(%a1) /* copy dword */
219 cmpl %a0, %a2 /* check if at end */
220 bne _copy_romfs
221#endif /* CONFIG_ROMFS_FS && CONFIG_RAMKERNEL && CONFIG_MTD_UCLINUX */
222
223/*****************************************************************************
224 * Clear bss region
225 *****************************************************************************/
226 lea __bss_start, %a0 /* get start of bss */
227 lea __bss_stop, %a1 /* get end of bss */
228_clear_bss:
229 movel #0, (%a0)+ /* clear each word */
230 cmpl %a0, %a1 /* check if at end */
231 bne _clear_bss
232
233/*****************************************************************************
234 * Load the current task pointer and stack.
235 *****************************************************************************/
236 lea init_thread_union,%a0
237 lea THREAD_SIZE(%a0),%sp
238 jsr start_kernel /* start Linux kernel */
239_exit:
240 jmp _exit /* should never get here */
diff --git a/arch/m68k/platform/68328/ints.c b/arch/m68k/platform/68000/ints.c
index b3810febb3e3..cda49b12d7be 100644
--- a/arch/m68k/platform/68328/ints.c
+++ b/arch/m68k/platform/68000/ints.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/m68knommu/platform/68328/ints.c 2 * ints.c - Generic interrupt controller support
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General Public 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive 5 * License. See the file COPYING in the main directory of this archive
diff --git a/arch/m68k/platform/68328/config.c b/arch/m68k/platform/68000/m68328.c
index 8c20e891e981..a86eb66835aa 100644
--- a/arch/m68k/platform/68328/config.c
+++ b/arch/m68k/platform/68000/m68328.c
@@ -1,7 +1,7 @@
1/***************************************************************************/ 1/***************************************************************************/
2 2
3/* 3/*
4 * linux/arch/m68knommu/platform/68328/config.c 4 * m68328.c - 68328 specific config
5 * 5 *
6 * Copyright (C) 1993 Hamish Macdonald 6 * Copyright (C) 1993 Hamish Macdonald
7 * Copyright (C) 1999 D. Jeff Dionne 7 * Copyright (C) 1999 D. Jeff Dionne
diff --git a/arch/m68k/platform/68EZ328/config.c b/arch/m68k/platform/68000/m68EZ328.c
index 4f158d551f02..a6eb72d75008 100644
--- a/arch/m68k/platform/68EZ328/config.c
+++ b/arch/m68k/platform/68000/m68EZ328.c
@@ -1,7 +1,7 @@
1/***************************************************************************/ 1/***************************************************************************/
2 2
3/* 3/*
4 * linux/arch/m68knommu/platform/68EZ328/config.c 4 * m68EZ328.c - 68EZ328 specific config
5 * 5 *
6 * Copyright (C) 1993 Hamish Macdonald 6 * Copyright (C) 1993 Hamish Macdonald
7 * Copyright (C) 1999 D. Jeff Dionne 7 * Copyright (C) 1999 D. Jeff Dionne
diff --git a/arch/m68k/platform/68VZ328/config.c b/arch/m68k/platform/68000/m68VZ328.c
index 2ed8dc305e42..eb6964fbec09 100644
--- a/arch/m68k/platform/68VZ328/config.c
+++ b/arch/m68k/platform/68000/m68VZ328.c
@@ -1,7 +1,7 @@
1/***************************************************************************/ 1/***************************************************************************/
2 2
3/* 3/*
4 * linux/arch/m68knommu/platform/68VZ328/config.c 4 * m68VZ328.c - 68VZ328 specific config
5 * 5 *
6 * Copyright (C) 1993 Hamish Macdonald 6 * Copyright (C) 1993 Hamish Macdonald
7 * Copyright (C) 1999 D. Jeff Dionne 7 * Copyright (C) 1999 D. Jeff Dionne
@@ -28,7 +28,7 @@
28#include <asm/bootstd.h> 28#include <asm/bootstd.h>
29 29
30#ifdef CONFIG_INIT_LCD 30#ifdef CONFIG_INIT_LCD
31#include "bootlogo.h" 31#include "bootlogo-vz.h"
32#endif 32#endif
33 33
34/***************************************************************************/ 34/***************************************************************************/
diff --git a/arch/m68k/platform/68328/romvec.S b/arch/m68k/platform/68000/romvec.S
index 31084466eae8..15c70cd6453f 100644
--- a/arch/m68k/platform/68328/romvec.S
+++ b/arch/m68k/platform/68000/romvec.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/m68knommu/platform/68328/romvec.S 2 * romvec.S - Vector table for 68000 cpus
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General Public 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive 5 * License. See the file COPYING in the main directory of this archive
diff --git a/arch/m68k/platform/68328/timers.c b/arch/m68k/platform/68000/timers.c
index f4dc9b295609..ec30acbfe6db 100644
--- a/arch/m68k/platform/68328/timers.c
+++ b/arch/m68k/platform/68000/timers.c
@@ -1,7 +1,7 @@
1/***************************************************************************/ 1/***************************************************************************/
2 2
3/* 3/*
4 * linux/arch/m68knommu/platform/68328/timers.c 4 * timers.c - Generic hardware timer support.
5 * 5 *
6 * Copyright (C) 1993 Hamish Macdonald 6 * Copyright (C) 1993 Hamish Macdonald
7 * Copyright (C) 1999 D. Jeff Dionne 7 * Copyright (C) 1999 D. Jeff Dionne
diff --git a/arch/m68k/platform/68328/Makefile b/arch/m68k/platform/68328/Makefile
deleted file mode 100644
index ee61bf84d4a0..000000000000
--- a/arch/m68k/platform/68328/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
1#
2# Makefile for arch/m68knommu/platform/68328.
3#
4
5model-y := ram
6model-$(CONFIG_ROMKERNEL) := rom
7
8head-y = head-$(model-y).o
9head-$(CONFIG_PILOT) = head-pilot.o
10head-$(CONFIG_DRAGEN2) = head-de2.o
11
12obj-y += entry.o ints.o timers.o
13obj-$(CONFIG_M68328) += config.o
14obj-$(CONFIG_ROM) += romvec.o
15
16extra-y := head.o
17
18$(obj)/head.o: $(obj)/$(head-y)
19 ln -sf $(head-y) $(obj)/head.o
20
21clean-files := $(obj)/head.o $(head-y)
diff --git a/arch/m68k/platform/68328/head-de2.S b/arch/m68k/platform/68328/head-de2.S
deleted file mode 100644
index 537d3245b539..000000000000
--- a/arch/m68k/platform/68328/head-de2.S
+++ /dev/null
@@ -1,128 +0,0 @@
1
2#define MEM_END 0x00800000 /* Memory size 8Mb */
3
4#undef CRT_DEBUG
5
6.macro PUTC CHAR
7#ifdef CRT_DEBUG
8 moveq #\CHAR, %d7
9 jsr putc
10#endif
11.endm
12
13 .global _start
14 .global _rambase
15 .global _ramvec
16 .global _ramstart
17 .global _ramend
18
19 .data
20
21/*
22 * Set up the usable of RAM stuff
23 */
24_rambase:
25 .long 0
26_ramvec:
27 .long 0
28_ramstart:
29 .long 0
30_ramend:
31 .long 0
32
33 .text
34
35_start:
36
37/*
38 * Setup initial stack
39 */
40 /* disable all interrupts */
41 movew #0x2700, %sr
42 movel #-1, 0xfffff304
43 movel #MEM_END-4, %sp
44
45 PUTC '\r'
46 PUTC '\n'
47 PUTC 'A'
48 PUTC 'B'
49
50/*
51 * Determine end of RAM
52 */
53
54 movel #MEM_END, %a0
55 movel %a0, _ramend
56
57 PUTC 'C'
58
59/*
60 * Move ROM filesystem above bss :-)
61 */
62
63 moveal #__bss_start, %a0 /* romfs at the start of bss */
64 moveal #__bss_stop, %a1 /* Set up destination */
65 movel %a0, %a2 /* Copy of bss start */
66
67 movel 8(%a0), %d1 /* Get size of ROMFS */
68 addql #8, %d1 /* Allow for rounding */
69 andl #0xfffffffc, %d1 /* Whole words */
70
71 addl %d1, %a0 /* Copy from end */
72 addl %d1, %a1 /* Copy from end */
73 movel %a1, _ramstart /* Set start of ram */
74
751:
76 movel -(%a0), %d0 /* Copy dword */
77 movel %d0, -(%a1)
78 cmpl %a0, %a2 /* Check if at end */
79 bne 1b
80
81 PUTC 'D'
82
83/*
84 * Initialize BSS segment to 0
85 */
86
87 lea __bss_start, %a0
88 lea __bss_stop, %a1
89
90 /* Copy 0 to %a0 until %a0 == %a1 */
912: cmpal %a0, %a1
92 beq 1f
93 clrl (%a0)+
94 bra 2b
951:
96
97 PUTC 'E'
98
99/*
100 * Load the current task pointer and stack
101 */
102
103 lea init_thread_union, %a0
104 lea 0x2000(%a0), %sp
105
106 PUTC 'F'
107 PUTC '\r'
108 PUTC '\n'
109
110/*
111 * Go
112 */
113
114 jmp start_kernel
115
116/*
117 * Local functions
118 */
119
120#ifdef CRT_DEBUG
121putc:
122 moveb %d7, 0xfffff907
1231:
124 movew 0xfffff906, %d7
125 andw #0x2000, %d7
126 beq 1b
127 rts
128#endif
diff --git a/arch/m68k/platform/68328/head-pilot.S b/arch/m68k/platform/68328/head-pilot.S
deleted file mode 100644
index 45a9dad29e3d..000000000000
--- a/arch/m68k/platform/68328/head-pilot.S
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * linux/arch/m68knommu/platform/68328/head-pilot.S
3 * - A startup file for the MC68328
4 *
5 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
6 * Kenneth Albanowski <kjahds@kjahds.com>,
7 * The Silver Hammer Group, Ltd.
8 *
9 * (c) 1995, Dionne & Associates
10 * (c) 1995, DKG Display Tech.
11 */
12
13#define ASSEMBLY
14
15#define IMMED #
16#define DBG_PUTC(x) moveb IMMED x, 0xfffff907
17
18
19.global _stext
20.global _start
21
22.global _rambase
23.global _ramvec
24.global _ramstart
25.global _ramend
26
27.global bootlogo_bits
28
29/*****************************************************************************/
30
31.data
32
33/*
34 * Set up the usable of RAM stuff. Size of RAM is determined then
35 * an initial stack set up at the end.
36 */
37.align 4
38_ramvec:
39.long 0
40_rambase:
41.long 0
42_ramstart:
43.long 0
44_ramend:
45.long 0
46
47.text
48
49_start:
50_stext:
51
52
53#ifdef CONFIG_M68328
54
55#ifdef CONFIG_PILOT
56 .byte 0x4e, 0xfa, 0x00, 0x0a /* Jmp +X bytes */
57 .byte 'b', 'o', 'o', 't'
58 .word 10000
59
60 nop
61#endif
62
63 moveq #0, %d0
64 movew %d0, 0xfffff618 /* Watchdog off */
65 movel #0x00011f07, 0xfffff114 /* CS A1 Mask */
66
67 movew #0x0800, 0xfffff906 /* Ignore CTS */
68 movew #0x010b, 0xfffff902 /* BAUD to 9600 */
69
70 movew #0x2410, 0xfffff200 /* PLLCR */
71 movew #0x123, 0xfffff202 /* PLLFSR */
72
73#ifdef CONFIG_PILOT
74 moveb #0, 0xfffffA27 /* LCKCON */
75 movel #_start, 0xfffffA00 /* LSSA */
76 moveb #0xa, 0xfffffA05 /* LVPW */
77 movew #0x9f, 0xFFFFFa08 /* LXMAX */
78 movew #0x9f, 0xFFFFFa0a /* LYMAX */
79 moveb #9, 0xfffffa29 /* LBAR */
80 moveb #0, 0xfffffa25 /* LPXCD */
81 moveb #0x04, 0xFFFFFa20 /* LPICF */
82 moveb #0x58, 0xfffffA27 /* LCKCON */
83 moveb #0x85, 0xfffff429 /* PFDATA */
84 moveb #0xd8, 0xfffffA27 /* LCKCON */
85 moveb #0xc5, 0xfffff429 /* PFDATA */
86 moveb #0xd5, 0xfffff429 /* PFDATA */
87
88 moveal #0x00100000, %a3
89 moveal #0x100ffc00, %a4
90#endif /* CONFIG_PILOT */
91
92#endif /* CONFIG_M68328 */
93
94 movew #0x2700, %sr
95 lea %a4@(-4), %sp
96
97 DBG_PUTC('\r')
98 DBG_PUTC('\n')
99 DBG_PUTC('A')
100
101 moveq #0,%d0
102 movew #16384, %d0 /* PLL settle wait loop */
103L0:
104 subw #1, %d0
105 bne L0
106
107 DBG_PUTC('B')
108
109 /* Copy command line from beginning of RAM (+16) to end of bss */
110 movel #CONFIG_VECTORBASE, %d7
111 addl #16, %d7
112 moveal %d7, %a0
113 moveal #__bss_stop, %a1
114 lea %a1@(512), %a2
115
116 DBG_PUTC('C')
117
118 /* Copy %a0 to %a1 until %a1 == %a2 */
119L2:
120 movel %a0@+, %d0
121 movel %d0, %a1@+
122 cmpal %a1, %a2
123 bhi L2
124
125 /* Copy data+init segment from ROM to RAM */
126 moveal #_etext, %a0
127 moveal #_sdata, %a1
128 moveal #__init_end, %a2
129
130 DBG_PUTC('D')
131
132 /* Copy %a0 to %a1 until %a1 == %a2 */
133LD1:
134 movel %a0@+, %d0
135 movel %d0, %a1@+
136 cmpal %a1, %a2
137 bhi LD1
138
139 DBG_PUTC('E')
140
141 moveal #__bss_start, %a0
142 moveal #__bss_stop, %a1
143
144 /* Copy 0 to %a0 until %a0 == %a1 */
145L1:
146 movel #0, %a0@+
147 cmpal %a0, %a1
148 bhi L1
149
150 DBG_PUTC('F')
151
152 /* Copy command line from end of bss to command line */
153 moveal #__bss_stop, %a0
154 moveal #command_line, %a1
155 lea %a1@(512), %a2
156
157 DBG_PUTC('G')
158
159 /* Copy %a0 to %a1 until %a1 == %a2 */
160L3:
161 movel %a0@+, %d0
162 movel %d0, %a1@+
163 cmpal %a1, %a2
164 bhi L3
165
166 movel #_sdata, %d0
167 movel %d0, _rambase
168 movel #__bss_stop, %d0
169 movel %d0, _ramstart
170
171 movel %a4, %d0
172 subl #4096, %d0 /* Reserve 4K of stack */
173 moveq #79, %d7
174 movel %d0, _ramend
175
176 pea 0
177 pea env
178 pea %sp@(4)
179 pea 0
180
181 DBG_PUTC('H')
182
183#ifdef CONFIG_PILOT
184 movel #bootlogo_bits, 0xFFFFFA00
185 moveb #10, 0xFFFFFA05
186 movew #160, 0xFFFFFA08
187 movew #160, 0xFFFFFA0A
188#endif /* CONFIG_PILOT */
189
190 DBG_PUTC('I')
191
192 lea init_thread_union, %a0
193 lea 0x2000(%a0), %sp
194
195 DBG_PUTC('J')
196 DBG_PUTC('\r')
197 DBG_PUTC('\n')
198
199 jsr start_kernel
200_exit:
201
202 jmp _exit
203
204
205 .data
206env:
207 .long 0
diff --git a/arch/m68k/platform/68328/head-ram.S b/arch/m68k/platform/68328/head-ram.S
deleted file mode 100644
index 5189ef926098..000000000000
--- a/arch/m68k/platform/68328/head-ram.S
+++ /dev/null
@@ -1,141 +0,0 @@
1
2 .global __main
3 .global __rom_start
4
5 .global _rambase
6 .global _ramstart
7
8 .global splash_bits
9 .global _start
10 .global _stext
11 .global _edata
12
13#define DEBUG
14#define ROM_OFFSET 0x10C00000
15#define STACK_GAURD 0x10
16
17 .text
18
19_start:
20_stext:
21 movew #0x2700, %sr /* Exceptions off! */
22
23#if 0
24 /* Init chip registers. uCsimm specific */
25 moveb #0x00, 0xfffffb0b /* Watchdog off */
26 moveb #0x10, 0xfffff000 /* SCR */
27
28 movew #0x2400, 0xfffff200 /* PLLCR */
29 movew #0x0123, 0xfffff202 /* PLLFSR */
30
31 moveb #0x00, 0xfffff40b /* enable chip select */
32 moveb #0x00, 0xfffff423 /* enable /DWE */
33 moveb #0x08, 0xfffffd0d /* disable hardmap */
34 moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */
35
36 movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */
37 movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */
38
39 movew #0x8f00, 0xfffffc00 /* DRAM configuration */
40 movew #0x9667, 0xfffffc02 /* DRAM control */
41 movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */
42 movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */
43
44 moveb #0x40, 0xfffff300 /* IVR */
45 movel #0x007FFFFF, %d0 /* IMR */
46 movel %d0, 0xfffff304
47
48 moveb 0xfffff42b, %d0
49 andb #0xe0, %d0
50 moveb %d0, 0xfffff42b
51
52 moveb #0x08, 0xfffff907 /* Ignore CTS */
53 movew #0x010b, 0xfffff902 /* BAUD to 9600 */
54 movew #0xe100, 0xfffff900 /* enable */
55#endif
56
57 movew #16384, %d0 /* PLL settle wait loop */
58L0:
59 subw #1, %d0
60 bne L0
61#ifdef DEBUG
62 moveq #70, %d7 /* 'F' */
63 moveb %d7,0xfffff907 /* No absolute addresses */
64pclp1:
65 movew 0xfffff906, %d7
66 andw #0x2000, %d7
67 beq pclp1
68#endif /* DEBUG */
69
70#ifdef DEBUG
71 moveq #82, %d7 /* 'R' */
72 moveb %d7,0xfffff907 /* No absolute addresses */
73pclp3:
74 movew 0xfffff906, %d7
75 andw #0x2000, %d7
76 beq pclp3
77#endif /* DEBUG */
78 moveal #0x007ffff0, %ssp
79 moveal #__bss_start, %a0
80 moveal #__bss_stop, %a1
81
82 /* Copy 0 to %a0 until %a0 >= %a1 */
83L1:
84 movel #0, %a0@+
85 cmpal %a0, %a1
86 bhi L1
87
88#ifdef DEBUG
89 moveq #67, %d7 /* 'C' */
90 jsr putc
91#endif /* DEBUG */
92
93 pea 0
94 pea env
95 pea %sp@(4)
96 pea 0
97
98#ifdef DEBUG
99 moveq #70, %d7 /* 'F' */
100 jsr putc
101#endif /* DEBUG */
102
103lp:
104 jsr start_kernel
105 jmp lp
106_exit:
107
108 jmp _exit
109
110__main:
111 /* nothing */
112 rts
113
114#ifdef DEBUG
115putc:
116 moveb %d7,0xfffff907
117pclp:
118 movew 0xfffff906, %d7
119 andw #0x2000, %d7
120 beq pclp
121 rts
122#endif /* DEBUG */
123
124 .data
125
126/*
127 * Set up the usable of RAM stuff. Size of RAM is determined then
128 * an initial stack set up at the end.
129 */
130.align 4
131_ramvec:
132.long 0
133_rambase:
134.long 0
135_ramstart:
136.long 0
137_ramend:
138.long 0
139
140env:
141 .long 0
diff --git a/arch/m68k/platform/68328/head-rom.S b/arch/m68k/platform/68328/head-rom.S
deleted file mode 100644
index 3dff98ba2e97..000000000000
--- a/arch/m68k/platform/68328/head-rom.S
+++ /dev/null
@@ -1,105 +0,0 @@
1
2 .global _start
3 .global _stext
4
5 .global _rambase
6 .global _ramvec
7 .global _ramstart
8 .global _ramend
9
10#ifdef CONFIG_INIT_LCD
11 .global bootlogo_bits
12#endif
13
14 .data
15
16/*
17 * Set up the usable of RAM stuff. Size of RAM is determined then
18 * an initial stack set up at the end.
19 */
20.align 4
21_ramvec:
22.long 0
23_rambase:
24.long 0
25_ramstart:
26.long 0
27_ramend:
28.long 0
29
30#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
31
32 .text
33_start:
34_stext: movew #0x2700,%sr
35#ifdef CONFIG_INIT_LCD
36 movel #bootlogo_bits, 0xfffffA00 /* LSSA */
37 moveb #0x28, 0xfffffA05 /* LVPW */
38 movew #0x280, 0xFFFFFa08 /* LXMAX */
39 movew #0x1df, 0xFFFFFa0a /* LYMAX */
40 moveb #0, 0xfffffa29 /* LBAR */
41 moveb #0, 0xfffffa25 /* LPXCD */
42 moveb #0x08, 0xFFFFFa20 /* LPICF */
43 moveb #0x01, 0xFFFFFA21 /* -ve pol */
44 moveb #0x81, 0xfffffA27 /* LCKCON */
45 movew #0xff00, 0xfffff412 /* LCD pins */
46#endif
47 moveal #RAMEND-CONFIG_MEMORY_RESERVE*0x100000 - 0x10, %sp
48 movew #32767, %d0 /* PLL settle wait loop */
491: subq #1, %d0
50 bne 1b
51
52 /* Copy data segment from ROM to RAM */
53 moveal #_etext, %a0
54 moveal #_sdata, %a1
55 moveal #_edata, %a2
56
57 /* Copy %a0 to %a1 until %a1 == %a2 */
581: movel %a0@+, %a1@+
59 cmpal %a1, %a2
60 bhi 1b
61
62 moveal #__bss_start, %a0
63 moveal #__bss_stop, %a1
64 /* Copy 0 to %a0 until %a0 == %a1 */
65
661:
67 clrl %a0@+
68 cmpal %a0, %a1
69 bhi 1b
70
71 movel #_sdata, %d0
72 movel %d0, _rambase
73 movel #__bss_stop, %d0
74 movel %d0, _ramstart
75 movel #RAMEND-CONFIG_MEMORY_RESERVE*0x100000, %d0
76 movel %d0, _ramend
77 movel #CONFIG_VECTORBASE, %d0
78 movel %d0, _ramvec
79
80/*
81 * load the current task pointer and stack
82 */
83 lea init_thread_union, %a0
84 lea 0x2000(%a0), %sp
85
861: jsr start_kernel
87 bra 1b
88_exit:
89
90 jmp _exit
91
92
93putc:
94 moveb %d7,0xfffff907
951:
96 movew 0xfffff906, %d7
97 andw #0x2000, %d7
98 beq 1b
99 rts
100
101 .data
102env:
103 .long 0
104 .text
105
diff --git a/arch/m68k/platform/68EZ328/Makefile b/arch/m68k/platform/68EZ328/Makefile
deleted file mode 100644
index b44d799b1115..000000000000
--- a/arch/m68k/platform/68EZ328/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for arch/m68knommu/platform/68EZ328.
3#
4
5obj-y := config.o
diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile
deleted file mode 100644
index 816674164682..000000000000
--- a/arch/m68k/platform/68VZ328/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for arch/m68k/platform/68VZ328.
3#
4
5obj-y := config.o
diff --git a/arch/m68k/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c
index 9cd13b4ce42b..fddfdccae63b 100644
--- a/arch/m68k/platform/coldfire/clk.c
+++ b/arch/m68k/platform/coldfire/clk.c
@@ -19,37 +19,58 @@
19#include <asm/mcfsim.h> 19#include <asm/mcfsim.h>
20#include <asm/mcfclk.h> 20#include <asm/mcfclk.h>
21 21
22/***************************************************************************/ 22static DEFINE_SPINLOCK(clk_lock);
23#ifndef MCFPM_PPMCR0 23
24struct clk *clk_get(struct device *dev, const char *id) 24#ifdef MCFPM_PPMCR0
25/*
26 * For more advanced ColdFire parts that have clocks that can be enabled
27 * we supply enable/disable functions. These must properly define their
28 * clocks in their platform specific code.
29 */
30void __clk_init_enabled(struct clk *clk)
25{ 31{
26 return NULL; 32 clk->enabled = 1;
33 clk->clk_ops->enable(clk);
27} 34}
28EXPORT_SYMBOL(clk_get);
29 35
30int clk_enable(struct clk *clk) 36void __clk_init_disabled(struct clk *clk)
31{ 37{
32 return 0; 38 clk->enabled = 0;
39 clk->clk_ops->disable(clk);
33} 40}
34EXPORT_SYMBOL(clk_enable);
35 41
36void clk_disable(struct clk *clk) 42static void __clk_enable0(struct clk *clk)
37{ 43{
44 __raw_writeb(clk->slot, MCFPM_PPMCR0);
38} 45}
39EXPORT_SYMBOL(clk_disable);
40 46
41void clk_put(struct clk *clk) 47static void __clk_disable0(struct clk *clk)
48{
49 __raw_writeb(clk->slot, MCFPM_PPMSR0);
50}
51
52struct clk_ops clk_ops0 = {
53 .enable = __clk_enable0,
54 .disable = __clk_disable0,
55};
56
57#ifdef MCFPM_PPMCR1
58static void __clk_enable1(struct clk *clk)
42{ 59{
60 __raw_writeb(clk->slot, MCFPM_PPMCR1);
43} 61}
44EXPORT_SYMBOL(clk_put);
45 62
46unsigned long clk_get_rate(struct clk *clk) 63static void __clk_disable1(struct clk *clk)
47{ 64{
48 return MCF_CLK; 65 __raw_writeb(clk->slot, MCFPM_PPMSR1);
49} 66}
50EXPORT_SYMBOL(clk_get_rate); 67
51#else 68struct clk_ops clk_ops1 = {
52static DEFINE_SPINLOCK(clk_lock); 69 .enable = __clk_enable1,
70 .disable = __clk_disable1,
71};
72#endif /* MCFPM_PPMCR1 */
73#endif /* MCFPM_PPMCR0 */
53 74
54struct clk *clk_get(struct device *dev, const char *id) 75struct clk *clk_get(struct device *dev, const char *id)
55{ 76{
@@ -101,48 +122,3 @@ unsigned long clk_get_rate(struct clk *clk)
101EXPORT_SYMBOL(clk_get_rate); 122EXPORT_SYMBOL(clk_get_rate);
102 123
103/***************************************************************************/ 124/***************************************************************************/
104
105void __clk_init_enabled(struct clk *clk)
106{
107 clk->enabled = 1;
108 clk->clk_ops->enable(clk);
109}
110
111void __clk_init_disabled(struct clk *clk)
112{
113 clk->enabled = 0;
114 clk->clk_ops->disable(clk);
115}
116
117static void __clk_enable0(struct clk *clk)
118{
119 __raw_writeb(clk->slot, MCFPM_PPMCR0);
120}
121
122static void __clk_disable0(struct clk *clk)
123{
124 __raw_writeb(clk->slot, MCFPM_PPMSR0);
125}
126
127struct clk_ops clk_ops0 = {
128 .enable = __clk_enable0,
129 .disable = __clk_disable0,
130};
131
132#ifdef MCFPM_PPMCR1
133static void __clk_enable1(struct clk *clk)
134{
135 __raw_writeb(clk->slot, MCFPM_PPMCR1);
136}
137
138static void __clk_disable1(struct clk *clk)
139{
140 __raw_writeb(clk->slot, MCFPM_PPMSR1);
141}
142
143struct clk_ops clk_ops1 = {
144 .enable = __clk_enable1,
145 .disable = __clk_disable1,
146};
147#endif /* MCFPM_PPMCR1 */
148#endif /* MCFPM_PPMCR0 */
diff --git a/arch/m68k/platform/coldfire/intc-5249.c b/arch/m68k/platform/coldfire/intc-5249.c
index 0864b836699a..b0d1641053e4 100644
--- a/arch/m68k/platform/coldfire/intc-5249.c
+++ b/arch/m68k/platform/coldfire/intc-5249.c
@@ -21,7 +21,7 @@ static void intc2_irq_gpio_mask(struct irq_data *d)
21{ 21{
22 u32 imr; 22 u32 imr;
23 imr = readl(MCFSIM2_GPIOINTENABLE); 23 imr = readl(MCFSIM2_GPIOINTENABLE);
24 imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); 24 imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0));
25 writel(imr, MCFSIM2_GPIOINTENABLE); 25 writel(imr, MCFSIM2_GPIOINTENABLE);
26} 26}
27 27
@@ -29,13 +29,13 @@ static void intc2_irq_gpio_unmask(struct irq_data *d)
29{ 29{
30 u32 imr; 30 u32 imr;
31 imr = readl(MCFSIM2_GPIOINTENABLE); 31 imr = readl(MCFSIM2_GPIOINTENABLE);
32 imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); 32 imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0));
33 writel(imr, MCFSIM2_GPIOINTENABLE); 33 writel(imr, MCFSIM2_GPIOINTENABLE);
34} 34}
35 35
36static void intc2_irq_gpio_ack(struct irq_data *d) 36static void intc2_irq_gpio_ack(struct irq_data *d)
37{ 37{
38 writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR); 38 writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
39} 39}
40 40
41static struct irq_chip intc2_irq_gpio_chip = { 41static struct irq_chip intc2_irq_gpio_chip = {
@@ -50,7 +50,7 @@ static int __init mcf_intc2_init(void)
50 int irq; 50 int irq;
51 51
52 /* GPIO interrupt sources */ 52 /* GPIO interrupt sources */
53 for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { 53 for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) {
54 irq_set_chip(irq, &intc2_irq_gpio_chip); 54 irq_set_chip(irq, &intc2_irq_gpio_chip);
55 irq_set_handler(irq, handle_edge_irq); 55 irq_set_handler(irq, handle_edge_irq);
56 } 56 }
diff --git a/arch/m68k/platform/coldfire/m5206.c b/arch/m68k/platform/coldfire/m5206.c
index 6bfbeebd231b..0e55f449a88c 100644
--- a/arch/m68k/platform/coldfire/m5206.c
+++ b/arch/m68k/platform/coldfire/m5206.c
@@ -16,6 +16,26 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29
30struct clk *mcf_clks[] = {
31 &clk_pll,
32 &clk_sys,
33 &clk_mcftmr0,
34 &clk_mcftmr1,
35 &clk_mcfuart0,
36 &clk_mcfuart1,
37 NULL
38};
19 39
20/***************************************************************************/ 40/***************************************************************************/
21 41
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
index ff37fe9553ea..2b10e9f198cd 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -19,6 +19,34 @@
19#include <asm/machdep.h> 19#include <asm/machdep.h>
20#include <asm/coldfire.h> 20#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
22#include <asm/mcfclk.h>
23
24/***************************************************************************/
25
26DEFINE_CLK(pll, "pll.0", MCF_CLK);
27DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
28DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
29DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
30DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
31DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
32DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
33DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
34DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
35DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
36
37struct clk *mcf_clks[] = {
38 &clk_pll,
39 &clk_sys,
40 &clk_mcfpit0,
41 &clk_mcfpit1,
42 &clk_mcfpit2,
43 &clk_mcfpit3,
44 &clk_mcfuart0,
45 &clk_mcfuart1,
46 &clk_mcfuart2,
47 &clk_fec0,
48 NULL
49};
22 50
23/***************************************************************************/ 51/***************************************************************************/
24 52
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
index 23b19cb7ab50..c80b5e51d29a 100644
--- a/arch/m68k/platform/coldfire/m5249.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -16,6 +16,26 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29
30struct clk *mcf_clks[] = {
31 &clk_pll,
32 &clk_sys,
33 &clk_mcftmr0,
34 &clk_mcftmr1,
35 &clk_mcfuart0,
36 &clk_mcfuart1,
37 NULL
38};
19 39
20/***************************************************************************/ 40/***************************************************************************/
21 41
@@ -28,8 +48,8 @@ static struct resource m5249_smc91x_resources[] = {
28 .flags = IORESOURCE_MEM, 48 .flags = IORESOURCE_MEM,
29 }, 49 },
30 { 50 {
31 .start = MCFINTC2_GPIOIRQ6, 51 .start = MCF_IRQ_GPIO6,
32 .end = MCFINTC2_GPIOIRQ6, 52 .end = MCF_IRQ_GPIO6,
33 .flags = IORESOURCE_IRQ, 53 .flags = IORESOURCE_IRQ,
34 }, 54 },
35}; 55};
@@ -75,8 +95,8 @@ static void __init m5249_smc91x_init(void)
75 gpio = readl(MCFSIM2_GPIOINTENABLE); 95 gpio = readl(MCFSIM2_GPIOINTENABLE);
76 writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE); 96 writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
77 97
78 gpio = readl(MCFSIM2_INTLEVEL5); 98 gpio = readl(MCFINTC2_INTPRI5);
79 writel(gpio | 0x04000000, MCFSIM2_INTLEVEL5); 99 writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
80} 100}
81 101
82#endif /* CONFIG_M5249C3 */ 102#endif /* CONFIG_M5249C3 */
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
index fce8f8a45bf0..5b9f657b2df0 100644
--- a/arch/m68k/platform/coldfire/m525x.c
+++ b/arch/m68k/platform/coldfire/m525x.c
@@ -16,6 +16,26 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29
30struct clk *mcf_clks[] = {
31 &clk_pll,
32 &clk_sys,
33 &clk_mcftmr0,
34 &clk_mcftmr1,
35 &clk_mcfuart0,
36 &clk_mcfuart1,
37 NULL
38};
19 39
20/***************************************************************************/ 40/***************************************************************************/
21 41
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
index 45b246d052ef..a8c5856fe5ec 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -19,6 +19,7 @@
19#include <asm/coldfire.h> 19#include <asm/coldfire.h>
20#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
21#include <asm/mcfuart.h> 21#include <asm/mcfuart.h>
22#include <asm/mcfclk.h>
22 23
23/***************************************************************************/ 24/***************************************************************************/
24 25
@@ -30,6 +31,31 @@ unsigned char ledbank = 0xff;
30 31
31/***************************************************************************/ 32/***************************************************************************/
32 33
34DEFINE_CLK(pll, "pll.0", MCF_CLK);
35DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
36DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
37DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
38DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
39DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
40DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
41DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
42DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
43
44struct clk *mcf_clks[] = {
45 &clk_pll,
46 &clk_sys,
47 &clk_mcftmr0,
48 &clk_mcftmr1,
49 &clk_mcftmr2,
50 &clk_mcftmr3,
51 &clk_mcfuart0,
52 &clk_mcfuart1,
53 &clk_fec0,
54 NULL
55};
56
57/***************************************************************************/
58
33static void __init m5272_uarts_init(void) 59static void __init m5272_uarts_init(void)
34{ 60{
35 u32 v; 61 u32 v;
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index 1431ba03c602..6fbfe9096c3e 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -20,6 +20,36 @@
20#include <asm/coldfire.h> 20#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 21#include <asm/mcfsim.h>
22#include <asm/mcfuart.h> 22#include <asm/mcfuart.h>
23#include <asm/mcfclk.h>
24
25/***************************************************************************/
26
27DEFINE_CLK(pll, "pll.0", MCF_CLK);
28DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
29DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
30DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
31DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
32DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
33DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
34DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
35DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
36DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
37DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
38
39struct clk *mcf_clks[] = {
40 &clk_pll,
41 &clk_sys,
42 &clk_mcfpit0,
43 &clk_mcfpit1,
44 &clk_mcfpit2,
45 &clk_mcfpit3,
46 &clk_mcfuart0,
47 &clk_mcfuart1,
48 &clk_mcfuart2,
49 &clk_fec0,
50 &clk_fec1,
51 NULL
52};
23 53
24/***************************************************************************/ 54/***************************************************************************/
25 55
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
index f9f7e6a13d04..83b7dad7a84e 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -21,6 +21,34 @@
21#include <asm/coldfire.h> 21#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
23#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
24#include <asm/mcfclk.h>
25
26/***************************************************************************/
27
28DEFINE_CLK(pll, "pll.0", MCF_CLK);
29DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
30DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
31DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
32DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
33DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
34DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
35DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
36DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
37DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
38
39struct clk *mcf_clks[] = {
40 &clk_pll,
41 &clk_sys,
42 &clk_mcfpit0,
43 &clk_mcfpit1,
44 &clk_mcfpit2,
45 &clk_mcfpit3,
46 &clk_mcfuart0,
47 &clk_mcfuart1,
48 &clk_mcfuart2,
49 &clk_fec0,
50 NULL
51};
24 52
25/***************************************************************************/ 53/***************************************************************************/
26 54
diff --git a/arch/m68k/platform/coldfire/m5307.c b/arch/m68k/platform/coldfire/m5307.c
index a568d2870d15..887435361386 100644
--- a/arch/m68k/platform/coldfire/m5307.c
+++ b/arch/m68k/platform/coldfire/m5307.c
@@ -17,6 +17,7 @@
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfwdebug.h> 19#include <asm/mcfwdebug.h>
20#include <asm/mcfclk.h>
20 21
21/***************************************************************************/ 22/***************************************************************************/
22 23
@@ -28,6 +29,25 @@ unsigned char ledbank = 0xff;
28 29
29/***************************************************************************/ 30/***************************************************************************/
30 31
32DEFINE_CLK(pll, "pll.0", MCF_CLK);
33DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
34DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
35DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
36DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
37DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
38
39struct clk *mcf_clks[] = {
40 &clk_pll,
41 &clk_sys,
42 &clk_mcftmr0,
43 &clk_mcftmr1,
44 &clk_mcfuart0,
45 &clk_mcfuart1,
46 NULL
47};
48
49/***************************************************************************/
50
31void __init config_BSP(char *commandp, int size) 51void __init config_BSP(char *commandp, int size)
32{ 52{
33#if defined(CONFIG_NETtel) || \ 53#if defined(CONFIG_NETtel) || \
diff --git a/arch/m68k/platform/coldfire/m5407.c b/arch/m68k/platform/coldfire/m5407.c
index bb6c746ae819..2fb3cdbfde30 100644
--- a/arch/m68k/platform/coldfire/m5407.c
+++ b/arch/m68k/platform/coldfire/m5407.c
@@ -16,6 +16,26 @@
16#include <asm/machdep.h> 16#include <asm/machdep.h>
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29
30struct clk *mcf_clks[] = {
31 &clk_pll,
32 &clk_sys,
33 &clk_mcftmr0,
34 &clk_mcftmr1,
35 &clk_mcfuart0,
36 &clk_mcfuart1,
37 NULL
38};
19 39
20/***************************************************************************/ 40/***************************************************************************/
21 41
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index b587bf35175b..952da53aa0bc 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -14,19 +14,45 @@
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/mm.h> 16#include <linux/mm.h>
17#include <linux/clk.h>
17#include <linux/bootmem.h> 18#include <linux/bootmem.h>
18#include <asm/pgalloc.h> 19#include <asm/pgalloc.h>
19#include <asm/machdep.h> 20#include <asm/machdep.h>
20#include <asm/coldfire.h> 21#include <asm/coldfire.h>
21#include <asm/m54xxsim.h> 22#include <asm/m54xxsim.h>
22#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
24#include <asm/mcfclk.h>
23#include <asm/m54xxgpt.h> 25#include <asm/m54xxgpt.h>
26#include <asm/mcfclk.h>
24#ifdef CONFIG_MMU 27#ifdef CONFIG_MMU
25#include <asm/mmu_context.h> 28#include <asm/mmu_context.h>
26#endif 29#endif
27 30
28/***************************************************************************/ 31/***************************************************************************/
29 32
33DEFINE_CLK(pll, "pll.0", MCF_CLK);
34DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
35DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
36DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
37DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
38DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
39DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
40DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
41
42struct clk *mcf_clks[] = {
43 &clk_pll,
44 &clk_sys,
45 &clk_mcfslt0,
46 &clk_mcfslt1,
47 &clk_mcfuart0,
48 &clk_mcfuart1,
49 &clk_mcfuart2,
50 &clk_mcfuart3,
51 NULL
52};
53
54/***************************************************************************/
55
30static void __init m54xx_uarts_init(void) 56static void __init m54xx_uarts_init(void)
31{ 57{
32 /* enable io pins */ 58 /* enable io pins */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 10:27:07 -0400