1 files changed, 5 insertions, 5 deletions

diff --git a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c
index 91a64016956e..e7609abf3796 100644
--- a/arch/i386/kernel/mpparse.c
+++ b/arch/i386/kernel/mpparse.c
@@ -710,7 +710,7 @@ void __init get_smp_config (void)
                  * Read the physical hardware table.  Anything here will
                  * override the defaults.
                  */
-                if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
+                if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
                         smp_found_config = 0;
                         printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
                         printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
@@ -1080,7 +1080,7 @@ void __init mp_config_acpi_legacy_irqs (void)
 
 #define MAX_GSI_NUM     4096
 
-int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
+int mp_register_gsi (u32 gsi, int triggering, int polarity)
 {
         int                     ioapic = -1;
         int                     ioapic_pin = 0;
@@ -1129,7 +1129,7 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
 
         mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 
-        if (edge_level) {
+        if (triggering == ACPI_LEVEL_SENSITIVE) {
                 /*
                  * For PCI devices assign IRQs in order, avoiding gaps
                  * due to unused I/O APIC pins.
@@ -1151,8 +1151,8 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
         }
 
         io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
-                    edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
-                    active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
+                    triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
+                    polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
         return gsi;
 }