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-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h102
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h102
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h91
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h91
-rw-r--r--arch/blackfin/mach-bf538/include/mach/cdefBF538.h103
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h114
-rw-r--r--arch/blackfin/mach-bf561/include/mach/cdefBF561.h103
7 files changed, 365 insertions, 341 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
index 95d54e625970..45a7ff88d863 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
@@ -31,7 +31,6 @@
31#ifndef _CDEF_BF52X_H 31#ifndef _CDEF_BF52X_H
32#define _CDEF_BF52X_H 32#define _CDEF_BF52X_H
33 33
34#include <asm/system.h>
35#include <asm/blackfin.h> 34#include <asm/blackfin.h>
36 35
37#include "defBF51x_base.h" 36#include "defBF51x_base.h"
@@ -43,57 +42,9 @@
43 42
44/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 43/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
60 bfin_write32(SIC_IWR1, 0);
61
62 bfin_write16(PLL_CTL, val);
63 SSYNC();
64 asm("IDLE;");
65
66 bfin_write32(SIC_IWR0, iwr0);
67 bfin_write32(SIC_IWR1, iwr1);
68 local_irq_restore(flags);
69}
70#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 45#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
71#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 46#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
72#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 47#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
73/* Writing to VR_CTL initiates a PLL relock sequence. */
74static __inline__ void bfin_write_VR_CTL(unsigned int val)
75{
76 unsigned long flags, iwr0, iwr1;
77
78 if (val == bfin_read_VR_CTL())
79 return;
80
81 local_irq_save(flags);
82 /* Enable the PLL Wakeup bit in SIC IWR */
83 iwr0 = bfin_read32(SIC_IWR0);
84 iwr1 = bfin_read32(SIC_IWR1);
85 /* Only allow PPL Wakeup) */
86 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
87 bfin_write32(SIC_IWR1, 0);
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR0, iwr0);
94 bfin_write32(SIC_IWR1, iwr1);
95 local_irq_restore(flags);
96}
97#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
98#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
99#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -1201,4 +1152,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1201#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) 1152#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1202#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) 1153#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1203 1154
1155/* These need to be last due to the cdef/linux inter-dependencies */
1156#include <asm/system.h>
1157
1158/* Writing to PLL_CTL initiates a PLL relock sequence. */
1159static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1160{
1161 unsigned long flags, iwr0, iwr1;
1162
1163 if (val == bfin_read_PLL_CTL())
1164 return;
1165
1166 local_irq_save(flags);
1167 /* Enable the PLL Wakeup bit in SIC IWR */
1168 iwr0 = bfin_read32(SIC_IWR0);
1169 iwr1 = bfin_read32(SIC_IWR1);
1170 /* Only allow PPL Wakeup) */
1171 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1172 bfin_write32(SIC_IWR1, 0);
1173
1174 bfin_write16(PLL_CTL, val);
1175 SSYNC();
1176 asm("IDLE;");
1177
1178 bfin_write32(SIC_IWR0, iwr0);
1179 bfin_write32(SIC_IWR1, iwr1);
1180 local_irq_restore(flags);
1181}
1182
1183/* Writing to VR_CTL initiates a PLL relock sequence. */
1184static __inline__ void bfin_write_VR_CTL(unsigned int val)
1185{
1186 unsigned long flags, iwr0, iwr1;
1187
1188 if (val == bfin_read_VR_CTL())
1189 return;
1190
1191 local_irq_save(flags);
1192 /* Enable the PLL Wakeup bit in SIC IWR */
1193 iwr0 = bfin_read32(SIC_IWR0);
1194 iwr1 = bfin_read32(SIC_IWR1);
1195 /* Only allow PPL Wakeup) */
1196 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1197 bfin_write32(SIC_IWR1, 0);
1198
1199 bfin_write16(VR_CTL, val);
1200 SSYNC();
1201 asm("IDLE;");
1202
1203 bfin_write32(SIC_IWR0, iwr0);
1204 bfin_write32(SIC_IWR1, iwr1);
1205 local_irq_restore(flags);
1206}
1207
1204#endif /* _CDEF_BF52X_H */ 1208#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 9a814b9a12b9..008603f332a6 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -31,7 +31,6 @@
31#ifndef _CDEF_BF52X_H 31#ifndef _CDEF_BF52X_H
32#define _CDEF_BF52X_H 32#define _CDEF_BF52X_H
33 33
34#include <asm/system.h>
35#include <asm/blackfin.h> 34#include <asm/blackfin.h>
36 35
37#include "defBF52x_base.h" 36#include "defBF52x_base.h"
@@ -43,57 +42,9 @@
43 42
44/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 43/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
60 bfin_write32(SIC_IWR1, 0);
61
62 bfin_write16(PLL_CTL, val);
63 SSYNC();
64 asm("IDLE;");
65
66 bfin_write32(SIC_IWR0, iwr0);
67 bfin_write32(SIC_IWR1, iwr1);
68 local_irq_restore(flags);
69}
70#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 45#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
71#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 46#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
72#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 47#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
73/* Writing to VR_CTL initiates a PLL relock sequence. */
74static __inline__ void bfin_write_VR_CTL(unsigned int val)
75{
76 unsigned long flags, iwr0, iwr1;
77
78 if (val == bfin_read_VR_CTL())
79 return;
80
81 local_irq_save(flags);
82 /* Enable the PLL Wakeup bit in SIC IWR */
83 iwr0 = bfin_read32(SIC_IWR0);
84 iwr1 = bfin_read32(SIC_IWR1);
85 /* Only allow PPL Wakeup) */
86 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
87 bfin_write32(SIC_IWR1, 0);
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR0, iwr0);
94 bfin_write32(SIC_IWR1, iwr1);
95 local_irq_restore(flags);
96}
97#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
98#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
99#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -1201,4 +1152,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1201#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) 1152#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1202#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) 1153#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1203 1154
1155/* These need to be last due to the cdef/linux inter-dependencies */
1156#include <asm/system.h>
1157
1158/* Writing to PLL_CTL initiates a PLL relock sequence. */
1159static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1160{
1161 unsigned long flags, iwr0, iwr1;
1162
1163 if (val == bfin_read_PLL_CTL())
1164 return;
1165
1166 local_irq_save(flags);
1167 /* Enable the PLL Wakeup bit in SIC IWR */
1168 iwr0 = bfin_read32(SIC_IWR0);
1169 iwr1 = bfin_read32(SIC_IWR1);
1170 /* Only allow PPL Wakeup) */
1171 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1172 bfin_write32(SIC_IWR1, 0);
1173
1174 bfin_write16(PLL_CTL, val);
1175 SSYNC();
1176 asm("IDLE;");
1177
1178 bfin_write32(SIC_IWR0, iwr0);
1179 bfin_write32(SIC_IWR1, iwr1);
1180 local_irq_restore(flags);
1181}
1182
1183/* Writing to VR_CTL initiates a PLL relock sequence. */
1184static __inline__ void bfin_write_VR_CTL(unsigned int val)
1185{
1186 unsigned long flags, iwr0, iwr1;
1187
1188 if (val == bfin_read_VR_CTL())
1189 return;
1190
1191 local_irq_save(flags);
1192 /* Enable the PLL Wakeup bit in SIC IWR */
1193 iwr0 = bfin_read32(SIC_IWR0);
1194 iwr1 = bfin_read32(SIC_IWR1);
1195 /* Only allow PPL Wakeup) */
1196 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
1197 bfin_write32(SIC_IWR1, 0);
1198
1199 bfin_write16(VR_CTL, val);
1200 SSYNC();
1201 asm("IDLE;");
1202
1203 bfin_write32(SIC_IWR0, iwr0);
1204 bfin_write32(SIC_IWR1, iwr1);
1205 local_irq_restore(flags);
1206}
1207
1204#endif /* _CDEF_BF52X_H */ 1208#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index 3d8978a52c17..24ff2cb967f6 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -39,31 +39,8 @@
39/*include core specific register pointer definitions*/ 39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h> 40#include <asm/cdef_LPBlackfin.h>
41 41
42#include <asm/system.h>
43
44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ 42/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 43#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr = bfin_read32(SIC_IWR);
57 /* Only allow PPL Wakeup) */
58 bfin_write32(SIC_IWR, IWR_ENABLE(0));
59
60 bfin_write16(PLL_CTL, val);
61 SSYNC();
62 asm("IDLE;");
63
64 bfin_write32(SIC_IWR, iwr);
65 local_irq_restore(flags);
66}
67#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 44#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
68#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
69#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -72,27 +49,6 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
72#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 49#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
73#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 50#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
74#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 51#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
75/* Writing to VR_CTL initiates a PLL relock sequence. */
76static __inline__ void bfin_write_VR_CTL(unsigned int val)
77{
78 unsigned long flags, iwr;
79
80 if (val == bfin_read_VR_CTL())
81 return;
82
83 local_irq_save(flags);
84 /* Enable the PLL Wakeup bit in SIC IWR */
85 iwr = bfin_read32(SIC_IWR);
86 /* Only allow PPL Wakeup) */
87 bfin_write32(SIC_IWR, IWR_ENABLE(0));
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR, iwr);
94 local_irq_restore(flags);
95}
96 52
97/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ 53/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
98#define bfin_read_SWRST() bfin_read16(SWRST) 54#define bfin_read_SWRST() bfin_read16(SWRST)
@@ -764,4 +720,51 @@ BFIN_READ_FIO_FLAG(T)
764#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 720#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
765#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) 721#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
766 722
723/* These need to be last due to the cdef/linux inter-dependencies */
724#include <asm/system.h>
725
726/* Writing to PLL_CTL initiates a PLL relock sequence. */
727static __inline__ void bfin_write_PLL_CTL(unsigned int val)
728{
729 unsigned long flags, iwr;
730
731 if (val == bfin_read_PLL_CTL())
732 return;
733
734 local_irq_save(flags);
735 /* Enable the PLL Wakeup bit in SIC IWR */
736 iwr = bfin_read32(SIC_IWR);
737 /* Only allow PPL Wakeup) */
738 bfin_write32(SIC_IWR, IWR_ENABLE(0));
739
740 bfin_write16(PLL_CTL, val);
741 SSYNC();
742 asm("IDLE;");
743
744 bfin_write32(SIC_IWR, iwr);
745 local_irq_restore(flags);
746}
747
748/* Writing to VR_CTL initiates a PLL relock sequence. */
749static __inline__ void bfin_write_VR_CTL(unsigned int val)
750{
751 unsigned long flags, iwr;
752
753 if (val == bfin_read_VR_CTL())
754 return;
755
756 local_irq_save(flags);
757 /* Enable the PLL Wakeup bit in SIC IWR */
758 iwr = bfin_read32(SIC_IWR);
759 /* Only allow PPL Wakeup) */
760 bfin_write32(SIC_IWR, IWR_ENABLE(0));
761
762 bfin_write16(VR_CTL, val);
763 SSYNC();
764 asm("IDLE;");
765
766 bfin_write32(SIC_IWR, iwr);
767 local_irq_restore(flags);
768}
769
767#endif /* _CDEF_BF532_H */ 770#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index 88d491cd9f36..76135607e35b 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -40,55 +40,11 @@
40/* Include core specific register pointer definitions */ 40/* Include core specific register pointer definitions */
41#include <asm/cdef_LPBlackfin.h> 41#include <asm/cdef_LPBlackfin.h>
42 42
43#include <asm/system.h>
44
45/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 43/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
46#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
47/* Writing to PLL_CTL initiates a PLL relock sequence. */
48static __inline__ void bfin_write_PLL_CTL(unsigned int val)
49{
50 unsigned long flags, iwr;
51
52 if (val == bfin_read_PLL_CTL())
53 return;
54
55 local_irq_save(flags);
56 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR, IWR_ENABLE(0));
60
61 bfin_write16(PLL_CTL, val);
62 SSYNC();
63 asm("IDLE;");
64
65 bfin_write32(SIC_IWR, iwr);
66 local_irq_restore(flags);
67}
68#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 45#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
69#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 46#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
70#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 47#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
71/* Writing to VR_CTL initiates a PLL relock sequence. */
72static __inline__ void bfin_write_VR_CTL(unsigned int val)
73{
74 unsigned long flags, iwr;
75
76 if (val == bfin_read_VR_CTL())
77 return;
78
79 local_irq_save(flags);
80 /* Enable the PLL Wakeup bit in SIC IWR */
81 iwr = bfin_read32(SIC_IWR);
82 /* Only allow PPL Wakeup) */
83 bfin_write32(SIC_IWR, IWR_ENABLE(0));
84
85 bfin_write16(VR_CTL, val);
86 SSYNC();
87 asm("IDLE;");
88
89 bfin_write32(SIC_IWR, iwr);
90 local_irq_restore(flags);
91}
92#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
93#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
94#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -1816,4 +1772,51 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1816#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) 1772#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1817#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) 1773#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1818 1774
1775/* These need to be last due to the cdef/linux inter-dependencies */
1776#include <asm/system.h>
1777
1778/* Writing to PLL_CTL initiates a PLL relock sequence. */
1779static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1780{
1781 unsigned long flags, iwr;
1782
1783 if (val == bfin_read_PLL_CTL())
1784 return;
1785
1786 local_irq_save(flags);
1787 /* Enable the PLL Wakeup bit in SIC IWR */
1788 iwr = bfin_read32(SIC_IWR);
1789 /* Only allow PPL Wakeup) */
1790 bfin_write32(SIC_IWR, IWR_ENABLE(0));
1791
1792 bfin_write16(PLL_CTL, val);
1793 SSYNC();
1794 asm("IDLE;");
1795
1796 bfin_write32(SIC_IWR, iwr);
1797 local_irq_restore(flags);
1798}
1799
1800/* Writing to VR_CTL initiates a PLL relock sequence. */
1801static __inline__ void bfin_write_VR_CTL(unsigned int val)
1802{
1803 unsigned long flags, iwr;
1804
1805 if (val == bfin_read_VR_CTL())
1806 return;
1807
1808 local_irq_save(flags);
1809 /* Enable the PLL Wakeup bit in SIC IWR */
1810 iwr = bfin_read32(SIC_IWR);
1811 /* Only allow PPL Wakeup) */
1812 bfin_write32(SIC_IWR, IWR_ENABLE(0));
1813
1814 bfin_write16(VR_CTL, val);
1815 SSYNC();
1816 asm("IDLE;");
1817
1818 bfin_write32(SIC_IWR, iwr);
1819 local_irq_restore(flags);
1820}
1821
1819#endif /* _CDEF_BF534_H */ 1822#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index f92e7c3932f3..1d768a65d139 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -39,62 +39,12 @@
39/*include core specific register pointer definitions*/ 39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h> 40#include <asm/cdef_LPBlackfin.h>
41 41
42#include <asm/system.h>
43
44#define bfin_writePTR(addr, val) bfin_write32(addr, val) 42#define bfin_writePTR(addr, val) bfin_write32(addr, val)
45 43
46#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
47/* Writing to PLL_CTL initiates a PLL relock sequence. */
48static __inline__ void bfin_write_PLL_CTL(unsigned int val)
49{
50 unsigned long flags, iwr0, iwr1;
51
52 if (val == bfin_read_PLL_CTL())
53 return;
54
55 local_irq_save(flags);
56 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr0 = bfin_read32(SIC_IWR0);
58 iwr1 = bfin_read32(SIC_IWR1);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62
63 bfin_write16(PLL_CTL, val);
64 SSYNC();
65 asm("IDLE;");
66
67 bfin_write32(SIC_IWR0, iwr0);
68 bfin_write32(SIC_IWR1, iwr1);
69 local_irq_restore(flags);
70}
71#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 45#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
72#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 46#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
73#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 47#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
74/* Writing to VR_CTL initiates a PLL relock sequence. */
75static __inline__ void bfin_write_VR_CTL(unsigned int val)
76{
77 unsigned long flags, iwr0, iwr1;
78
79 if (val == bfin_read_VR_CTL())
80 return;
81
82 local_irq_save(flags);
83 /* Enable the PLL Wakeup bit in SIC IWR */
84 iwr0 = bfin_read32(SIC_IWR0);
85 iwr1 = bfin_read32(SIC_IWR1);
86 /* Only allow PPL Wakeup) */
87 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
88 bfin_write32(SIC_IWR1, 0);
89
90 bfin_write16(VR_CTL, val);
91 SSYNC();
92 asm("IDLE;");
93
94 bfin_write32(SIC_IWR0, iwr0);
95 bfin_write32(SIC_IWR1, iwr1);
96 local_irq_restore(flags);
97}
98#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
99#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
100#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -2102,4 +2052,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2102#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) 2052#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
2103#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) 2053#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
2104 2054
2055/* These need to be last due to the cdef/linux inter-dependencies */
2056#include <asm/system.h>
2057
2058/* Writing to PLL_CTL initiates a PLL relock sequence. */
2059static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2060{
2061 unsigned long flags, iwr0, iwr1;
2062
2063 if (val == bfin_read_PLL_CTL())
2064 return;
2065
2066 local_irq_save(flags);
2067 /* Enable the PLL Wakeup bit in SIC IWR */
2068 iwr0 = bfin_read32(SIC_IWR0);
2069 iwr1 = bfin_read32(SIC_IWR1);
2070 /* Only allow PPL Wakeup) */
2071 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2072 bfin_write32(SIC_IWR1, 0);
2073
2074 bfin_write16(PLL_CTL, val);
2075 SSYNC();
2076 asm("IDLE;");
2077
2078 bfin_write32(SIC_IWR0, iwr0);
2079 bfin_write32(SIC_IWR1, iwr1);
2080 local_irq_restore(flags);
2081}
2082
2083/* Writing to VR_CTL initiates a PLL relock sequence. */
2084static __inline__ void bfin_write_VR_CTL(unsigned int val)
2085{
2086 unsigned long flags, iwr0, iwr1;
2087
2088 if (val == bfin_read_VR_CTL())
2089 return;
2090
2091 local_irq_save(flags);
2092 /* Enable the PLL Wakeup bit in SIC IWR */
2093 iwr0 = bfin_read32(SIC_IWR0);
2094 iwr1 = bfin_read32(SIC_IWR1);
2095 /* Only allow PPL Wakeup) */
2096 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2097 bfin_write32(SIC_IWR1, 0);
2098
2099 bfin_write16(VR_CTL, val);
2100 SSYNC();
2101 asm("IDLE;");
2102
2103 bfin_write32(SIC_IWR0, iwr0);
2104 bfin_write32(SIC_IWR1, iwr1);
2105 local_irq_restore(flags);
2106}
2107
2105#endif 2108#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index 57ac8cb9b1f6..c376fb7acda0 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -34,7 +34,6 @@
34#include <asm/blackfin.h> 34#include <asm/blackfin.h>
35 35
36#include "defBF54x_base.h" 36#include "defBF54x_base.h"
37#include <asm/system.h>
38 37
39/* ************************************************************** */ 38/* ************************************************************** */
40/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 39/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
@@ -43,63 +42,9 @@
43/* PLL Registers */ 42/* PLL Registers */
44 43
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1, iwr2;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(PLL_CTL, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71 local_irq_restore(flags);
72}
73#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 45#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
74#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 46#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
75#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 47#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
76/* Writing to VR_CTL initiates a PLL relock sequence. */
77static __inline__ void bfin_write_VR_CTL(unsigned int val)
78{
79 unsigned long flags, iwr0, iwr1, iwr2;
80
81 if (val == bfin_read_VR_CTL())
82 return;
83
84 local_irq_save(flags);
85 /* Enable the PLL Wakeup bit in SIC IWR */
86 iwr0 = bfin_read32(SIC_IWR0);
87 iwr1 = bfin_read32(SIC_IWR1);
88 iwr2 = bfin_read32(SIC_IWR2);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
91 bfin_write32(SIC_IWR1, 0);
92 bfin_write32(SIC_IWR2, 0);
93
94 bfin_write16(VR_CTL, val);
95 SSYNC();
96 asm("IDLE;");
97
98 bfin_write32(SIC_IWR0, iwr0);
99 bfin_write32(SIC_IWR1, iwr1);
100 bfin_write32(SIC_IWR2, iwr2);
101 local_irq_restore(flags);
102}
103#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
104#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
105#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -2746,5 +2691,64 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
2746#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST 2691#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2747#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST 2692#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2748 2693
2694/* These need to be last due to the cdef/linux inter-dependencies */
2695#include <asm/system.h>
2696
2697/* Writing to PLL_CTL initiates a PLL relock sequence. */
2698static __inline__ void bfin_write_PLL_CTL(unsigned int val)
2699{
2700 unsigned long flags, iwr0, iwr1, iwr2;
2701
2702 if (val == bfin_read_PLL_CTL())
2703 return;
2704
2705 local_irq_save(flags);
2706 /* Enable the PLL Wakeup bit in SIC IWR */
2707 iwr0 = bfin_read32(SIC_IWR0);
2708 iwr1 = bfin_read32(SIC_IWR1);
2709 iwr2 = bfin_read32(SIC_IWR2);
2710 /* Only allow PPL Wakeup) */
2711 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2712 bfin_write32(SIC_IWR1, 0);
2713 bfin_write32(SIC_IWR2, 0);
2714
2715 bfin_write16(PLL_CTL, val);
2716 SSYNC();
2717 asm("IDLE;");
2718
2719 bfin_write32(SIC_IWR0, iwr0);
2720 bfin_write32(SIC_IWR1, iwr1);
2721 bfin_write32(SIC_IWR2, iwr2);
2722 local_irq_restore(flags);
2723}
2724
2725/* Writing to VR_CTL initiates a PLL relock sequence. */
2726static __inline__ void bfin_write_VR_CTL(unsigned int val)
2727{
2728 unsigned long flags, iwr0, iwr1, iwr2;
2729
2730 if (val == bfin_read_VR_CTL())
2731 return;
2732
2733 local_irq_save(flags);
2734 /* Enable the PLL Wakeup bit in SIC IWR */
2735 iwr0 = bfin_read32(SIC_IWR0);
2736 iwr1 = bfin_read32(SIC_IWR1);
2737 iwr2 = bfin_read32(SIC_IWR2);
2738 /* Only allow PPL Wakeup) */
2739 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2740 bfin_write32(SIC_IWR1, 0);
2741 bfin_write32(SIC_IWR2, 0);
2742
2743 bfin_write16(VR_CTL, val);
2744 SSYNC();
2745 asm("IDLE;");
2746
2747 bfin_write32(SIC_IWR0, iwr0);
2748 bfin_write32(SIC_IWR1, iwr1);
2749 bfin_write32(SIC_IWR2, iwr2);
2750 local_irq_restore(flags);
2751}
2752
2749#endif /* _CDEF_BF54X_H */ 2753#endif /* _CDEF_BF54X_H */
2750 2754
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index c14d63402e70..eb349ca88cc4 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -39,65 +39,15 @@
39/*include core specific register pointer definitions*/ 39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h> 40#include <asm/cdef_LPBlackfin.h>
41 41
42#include <asm/system.h>
43
44/*********************************************************************************** */ 42/*********************************************************************************** */
45/* System MMR Register Map */ 43/* System MMR Register Map */
46/*********************************************************************************** */ 44/*********************************************************************************** */
47 45
48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 46/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 47#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
50/* Writing to PLL_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_PLL_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1;
54
55 if (val == bfin_read_PLL_CTL())
56 return;
57
58 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1);
62 /* Only allow PPL Wakeup) */
63 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
64 bfin_write32(SICA_IWR1, 0);
65
66 bfin_write16(PLL_CTL, val);
67 SSYNC();
68 asm("IDLE;");
69
70 bfin_write32(SICA_IWR0, iwr0);
71 bfin_write32(SICA_IWR1, iwr1);
72 local_irq_restore(flags);
73}
74#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 48#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
75#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 49#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
76#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 50#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
77/* Writing to VR_CTL initiates a PLL relock sequence. */
78static __inline__ void bfin_write_VR_CTL(unsigned int val)
79{
80 unsigned long flags, iwr0, iwr1;
81
82 if (val == bfin_read_VR_CTL())
83 return;
84
85 local_irq_save(flags);
86 /* Enable the PLL Wakeup bit in SIC IWR */
87 iwr0 = bfin_read32(SICA_IWR0);
88 iwr1 = bfin_read32(SICA_IWR1);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
91 bfin_write32(SICA_IWR1, 0);
92
93 bfin_write16(VR_CTL, val);
94 SSYNC();
95 asm("IDLE;");
96
97 bfin_write32(SICA_IWR0, iwr0);
98 bfin_write32(SICA_IWR1, iwr1);
99 local_irq_restore(flags);
100}
101#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 51#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
102#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 52#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
103#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 53#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -1576,4 +1526,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1576#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() 1526#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1577#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) 1527#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1578 1528
1529/* These need to be last due to the cdef/linux inter-dependencies */
1530#include <asm/system.h>
1531
1532/* Writing to PLL_CTL initiates a PLL relock sequence. */
1533static __inline__ void bfin_write_PLL_CTL(unsigned int val)
1534{
1535 unsigned long flags, iwr0, iwr1;
1536
1537 if (val == bfin_read_PLL_CTL())
1538 return;
1539
1540 local_irq_save(flags);
1541 /* Enable the PLL Wakeup bit in SIC IWR */
1542 iwr0 = bfin_read32(SICA_IWR0);
1543 iwr1 = bfin_read32(SICA_IWR1);
1544 /* Only allow PPL Wakeup) */
1545 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1546 bfin_write32(SICA_IWR1, 0);
1547
1548 bfin_write16(PLL_CTL, val);
1549 SSYNC();
1550 asm("IDLE;");
1551
1552 bfin_write32(SICA_IWR0, iwr0);
1553 bfin_write32(SICA_IWR1, iwr1);
1554 local_irq_restore(flags);
1555}
1556
1557/* Writing to VR_CTL initiates a PLL relock sequence. */
1558static __inline__ void bfin_write_VR_CTL(unsigned int val)
1559{
1560 unsigned long flags, iwr0, iwr1;
1561
1562 if (val == bfin_read_VR_CTL())
1563 return;
1564
1565 local_irq_save(flags);
1566 /* Enable the PLL Wakeup bit in SIC IWR */
1567 iwr0 = bfin_read32(SICA_IWR0);
1568 iwr1 = bfin_read32(SICA_IWR1);
1569 /* Only allow PPL Wakeup) */
1570 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
1571 bfin_write32(SICA_IWR1, 0);
1572
1573 bfin_write16(VR_CTL, val);
1574 SSYNC();
1575 asm("IDLE;");
1576
1577 bfin_write32(SICA_IWR0, iwr0);
1578 bfin_write32(SICA_IWR1, iwr1);
1579 local_irq_restore(flags);
1580}
1581
1579#endif /* _CDEF_BF561_H */ 1582#endif /* _CDEF_BF561_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 04:31:42 -0400