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-rw-r--r--arch/blackfin/Kconfig7
-rw-r--r--arch/blackfin/Kconfig.debug6
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig63
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig4
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig14
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig6
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BlackStamp_defconfig4
-rw-r--r--arch/blackfin/configs/CM-BF527_defconfig4
-rw-r--r--arch/blackfin/configs/CM-BF548_defconfig6
-rw-r--r--arch/blackfin/configs/IP0X_defconfig2
-rw-r--r--arch/blackfin/configs/SRV1_defconfig4
-rw-r--r--arch/blackfin/include/asm/Kbuild1
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h45
-rw-r--r--arch/blackfin/include/asm/ipipe.h100
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h12
-rw-r--r--arch/blackfin/include/asm/irq.h36
-rw-r--r--arch/blackfin/include/asm/thread_info.h2
-rw-r--r--arch/blackfin/kernel/Makefile8
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c4
-rw-r--r--arch/blackfin/kernel/ipipe.c176
-rw-r--r--arch/blackfin/kernel/irqchip.c14
-rw-r--r--arch/blackfin/kernel/kgdb_test.c9
-rw-r--r--arch/blackfin/kernel/ptrace.c5
-rw-r--r--arch/blackfin/kernel/setup.c10
-rw-r--r--arch/blackfin/kernel/time.c5
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c33
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h17
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c26
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c24
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h6
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf533/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf533/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf533/boards/blackstamp.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/generic_board.c126
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c13
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h2
-rw-r--r--arch/blackfin/mach-bf537/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537.c26
-rw-r--r--arch/blackfin/mach-bf537/boards/generic_board.c745
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c24
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c24
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c24
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h6
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h8
-rw-r--r--arch/blackfin/mach-bf561/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf561/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c15
-rw-r--r--arch/blackfin/mach-bf561/boards/generic_board.c113
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h2
-rw-r--r--arch/blackfin/mach-common/arch_checks.c9
-rw-r--r--arch/blackfin/mach-common/cache.S22
-rw-r--r--arch/blackfin/mach-common/clocks-init.c2
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S24
-rw-r--r--arch/blackfin/mach-common/entry.S61
-rw-r--r--arch/blackfin/mach-common/interrupt.S12
-rw-r--r--arch/blackfin/mach-common/ints-priority.c126
-rw-r--r--arch/blackfin/mach-common/smp.c6
-rw-r--r--arch/blackfin/mm/init.c2
73 files changed, 607 insertions, 1601 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8f1f97d56e1e..0c1f86e3e44a 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -1129,6 +1129,7 @@ endchoice
1129 1129
1130config PM_WAKEUP_BY_GPIO 1130config PM_WAKEUP_BY_GPIO
1131 bool "Allow Wakeup from Standby by GPIO" 1131 bool "Allow Wakeup from Standby by GPIO"
1132 depends on PM && !BF54x
1132 1133
1133config PM_WAKEUP_GPIO_NUMBER 1134config PM_WAKEUP_GPIO_NUMBER
1134 int "GPIO number" 1135 int "GPIO number"
@@ -1168,6 +1169,12 @@ config PM_BFIN_WAKE_GP
1168 default n 1169 default n
1169 help 1170 help
1170 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1171 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1172 (all processors, except ADSP-BF549). This option sets
1173 the general-purpose wake-up enable (GPWE) control bit to enable
1174 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1175 On ADSP-BF549 this option enables the the same functionality on the
1176 /MRXON pin also PH7.
1177
1171endmenu 1178endmenu
1172 1179
1173menu "CPU Frequency scaling" 1180menu "CPU Frequency scaling"
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 5f981d9ca625..79e7e63ab709 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -21,12 +21,6 @@ config DEBUG_STACK_USAGE
21config HAVE_ARCH_KGDB 21config HAVE_ARCH_KGDB
22 def_bool y 22 def_bool y
23 23
24config KGDB_TESTCASE
25 tristate "KGDB: for test case in expect"
26 default n
27 help
28 This is a kgdb test case for automated testing.
29
30config DEBUG_VERBOSE 24config DEBUG_VERBOSE
31 bool "Verbose fault messages" 25 bool "Verbose fault messages"
32 default y 26 default y
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index 4fdb9e04759f..281f4b60e603 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc2 3# Linux kernel version: 2.6.28
4# Fri Jan 9 17:58:41 2009 4# Fri Feb 20 10:01:44 2009
5# 5#
6# CONFIG_MMU is not set 6# CONFIG_MMU is not set
7# CONFIG_FPU is not set 7# CONFIG_FPU is not set
@@ -133,10 +133,15 @@ CONFIG_BF518=y
133# CONFIG_BF538 is not set 133# CONFIG_BF538 is not set
134# CONFIG_BF539 is not set 134# CONFIG_BF539 is not set
135# CONFIG_BF542 is not set 135# CONFIG_BF542 is not set
136# CONFIG_BF542M is not set
136# CONFIG_BF544 is not set 137# CONFIG_BF544 is not set
138# CONFIG_BF544M is not set
137# CONFIG_BF547 is not set 139# CONFIG_BF547 is not set
140# CONFIG_BF547M is not set
138# CONFIG_BF548 is not set 141# CONFIG_BF548 is not set
142# CONFIG_BF548M is not set
139# CONFIG_BF549 is not set 143# CONFIG_BF549 is not set
144# CONFIG_BF549M is not set
140# CONFIG_BF561 is not set 145# CONFIG_BF561 is not set
141CONFIG_BF_REV_MIN=0 146CONFIG_BF_REV_MIN=0
142CONFIG_BF_REV_MAX=2 147CONFIG_BF_REV_MAX=2
@@ -426,7 +431,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
426# CONFIG_TIPC is not set 431# CONFIG_TIPC is not set
427# CONFIG_ATM is not set 432# CONFIG_ATM is not set
428# CONFIG_BRIDGE is not set 433# CONFIG_BRIDGE is not set
429# CONFIG_NET_DSA is not set 434CONFIG_NET_DSA=y
435# CONFIG_NET_DSA_TAG_DSA is not set
436# CONFIG_NET_DSA_TAG_EDSA is not set
437# CONFIG_NET_DSA_TAG_TRAILER is not set
438CONFIG_NET_DSA_TAG_STPID=y
439# CONFIG_NET_DSA_MV88E6XXX is not set
440# CONFIG_NET_DSA_MV88E6060 is not set
441# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
442# CONFIG_NET_DSA_MV88E6131 is not set
443# CONFIG_NET_DSA_MV88E6123_61_65 is not set
444CONFIG_NET_DSA_KSZ8893M=y
430# CONFIG_VLAN_8021Q is not set 445# CONFIG_VLAN_8021Q is not set
431# CONFIG_DECNET is not set 446# CONFIG_DECNET is not set
432# CONFIG_LLC2 is not set 447# CONFIG_LLC2 is not set
@@ -529,6 +544,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
529# 544#
530# Self-contained MTD device drivers 545# Self-contained MTD device drivers
531# 546#
547# CONFIG_MTD_DATAFLASH is not set
548# CONFIG_MTD_M25P80 is not set
532# CONFIG_MTD_SLRAM is not set 549# CONFIG_MTD_SLRAM is not set
533# CONFIG_MTD_PHRAM is not set 550# CONFIG_MTD_PHRAM is not set
534# CONFIG_MTD_MTDRAM is not set 551# CONFIG_MTD_MTDRAM is not set
@@ -561,7 +578,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
561# CONFIG_BLK_DEV_HD is not set 578# CONFIG_BLK_DEV_HD is not set
562CONFIG_MISC_DEVICES=y 579CONFIG_MISC_DEVICES=y
563# CONFIG_EEPROM_93CX6 is not set 580# CONFIG_EEPROM_93CX6 is not set
581# CONFIG_ICS932S401 is not set
564# CONFIG_ENCLOSURE_SERVICES is not set 582# CONFIG_ENCLOSURE_SERVICES is not set
583# CONFIG_C2PORT is not set
565CONFIG_HAVE_IDE=y 584CONFIG_HAVE_IDE=y
566# CONFIG_IDE is not set 585# CONFIG_IDE is not set
567 586
@@ -607,6 +626,7 @@ CONFIG_BFIN_RX_DESC_NUM=20
607# CONFIG_SMC91X is not set 626# CONFIG_SMC91X is not set
608# CONFIG_SMSC911X is not set 627# CONFIG_SMSC911X is not set
609# CONFIG_DM9000 is not set 628# CONFIG_DM9000 is not set
629# CONFIG_ENC28J60 is not set
610# CONFIG_IBM_NEW_EMAC_ZMII is not set 630# CONFIG_IBM_NEW_EMAC_ZMII is not set
611# CONFIG_IBM_NEW_EMAC_RGMII is not set 631# CONFIG_IBM_NEW_EMAC_RGMII is not set
612# CONFIG_IBM_NEW_EMAC_TAH is not set 632# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -764,7 +784,23 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
764# CONFIG_I2C_DEBUG_ALGO is not set 784# CONFIG_I2C_DEBUG_ALGO is not set
765# CONFIG_I2C_DEBUG_BUS is not set 785# CONFIG_I2C_DEBUG_BUS is not set
766# CONFIG_I2C_DEBUG_CHIP is not set 786# CONFIG_I2C_DEBUG_CHIP is not set
767# CONFIG_SPI is not set 787CONFIG_SPI=y
788# CONFIG_SPI_DEBUG is not set
789CONFIG_SPI_MASTER=y
790
791#
792# SPI Master Controller Drivers
793#
794CONFIG_SPI_BFIN=y
795# CONFIG_SPI_BFIN_LOCK is not set
796# CONFIG_SPI_BITBANG is not set
797
798#
799# SPI Protocol Masters
800#
801# CONFIG_SPI_AT25 is not set
802# CONFIG_SPI_SPIDEV is not set
803# CONFIG_SPI_TLE62X0 is not set
768CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 804CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
769# CONFIG_GPIOLIB is not set 805# CONFIG_GPIOLIB is not set
770# CONFIG_W1 is not set 806# CONFIG_W1 is not set
@@ -788,8 +824,10 @@ CONFIG_BFIN_WDT=y
788# CONFIG_MFD_SM501 is not set 824# CONFIG_MFD_SM501 is not set
789# CONFIG_HTC_PASIC3 is not set 825# CONFIG_HTC_PASIC3 is not set
790# CONFIG_MFD_TMIO is not set 826# CONFIG_MFD_TMIO is not set
827# CONFIG_PMIC_DA903X is not set
791# CONFIG_MFD_WM8400 is not set 828# CONFIG_MFD_WM8400 is not set
792# CONFIG_MFD_WM8350_I2C is not set 829# CONFIG_MFD_WM8350_I2C is not set
830# CONFIG_REGULATOR is not set
793 831
794# 832#
795# Multimedia devices 833# Multimedia devices
@@ -861,10 +899,18 @@ CONFIG_RTC_INTF_DEV=y
861# CONFIG_RTC_DRV_M41T80 is not set 899# CONFIG_RTC_DRV_M41T80 is not set
862# CONFIG_RTC_DRV_S35390A is not set 900# CONFIG_RTC_DRV_S35390A is not set
863# CONFIG_RTC_DRV_FM3130 is not set 901# CONFIG_RTC_DRV_FM3130 is not set
902# CONFIG_RTC_DRV_RX8581 is not set
864 903
865# 904#
866# SPI RTC drivers 905# SPI RTC drivers
867# 906#
907# CONFIG_RTC_DRV_M41T94 is not set
908# CONFIG_RTC_DRV_DS1305 is not set
909# CONFIG_RTC_DRV_DS1390 is not set
910# CONFIG_RTC_DRV_MAX6902 is not set
911# CONFIG_RTC_DRV_R9701 is not set
912# CONFIG_RTC_DRV_RS5C348 is not set
913# CONFIG_RTC_DRV_DS3234 is not set
868 914
869# 915#
870# Platform RTC drivers 916# Platform RTC drivers
@@ -1062,12 +1108,20 @@ CONFIG_DEBUG_INFO=y
1062# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1108# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1063# CONFIG_FAULT_INJECTION is not set 1109# CONFIG_FAULT_INJECTION is not set
1064CONFIG_SYSCTL_SYSCALL_CHECK=y 1110CONFIG_SYSCTL_SYSCALL_CHECK=y
1111
1112#
1113# Tracers
1114#
1115# CONFIG_SCHED_TRACER is not set
1116# CONFIG_CONTEXT_SWITCH_TRACER is not set
1117# CONFIG_BOOT_TRACER is not set
1065# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1118# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1066# CONFIG_SAMPLES is not set 1119# CONFIG_SAMPLES is not set
1067CONFIG_HAVE_ARCH_KGDB=y 1120CONFIG_HAVE_ARCH_KGDB=y
1068# CONFIG_KGDB is not set 1121# CONFIG_KGDB is not set
1069# CONFIG_DEBUG_STACKOVERFLOW is not set 1122# CONFIG_DEBUG_STACKOVERFLOW is not set
1070# CONFIG_DEBUG_STACK_USAGE is not set 1123# CONFIG_DEBUG_STACK_USAGE is not set
1124# CONFIG_KGDB_TESTCASE is not set
1071CONFIG_DEBUG_VERBOSE=y 1125CONFIG_DEBUG_VERBOSE=y
1072CONFIG_DEBUG_MMRS=y 1126CONFIG_DEBUG_MMRS=y
1073# CONFIG_DEBUG_HWERR is not set 1127# CONFIG_DEBUG_HWERR is not set
@@ -1100,6 +1154,7 @@ CONFIG_CRYPTO=y
1100# 1154#
1101# CONFIG_CRYPTO_FIPS is not set 1155# CONFIG_CRYPTO_FIPS is not set
1102# CONFIG_CRYPTO_MANAGER is not set 1156# CONFIG_CRYPTO_MANAGER is not set
1157# CONFIG_CRYPTO_MANAGER2 is not set
1103# CONFIG_CRYPTO_GF128MUL is not set 1158# CONFIG_CRYPTO_GF128MUL is not set
1104# CONFIG_CRYPTO_NULL is not set 1159# CONFIG_CRYPTO_NULL is not set
1105# CONFIG_CRYPTO_CRYPTD is not set 1160# CONFIG_CRYPTO_CRYPTD is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 833128b39724..a50050f17706 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -327,8 +327,8 @@ CONFIG_BFIN_ICACHE=y
327CONFIG_BFIN_DCACHE=y 327CONFIG_BFIN_DCACHE=y
328# CONFIG_BFIN_DCACHE_BANKA is not set 328# CONFIG_BFIN_DCACHE_BANKA is not set
329# CONFIG_BFIN_ICACHE_LOCK is not set 329# CONFIG_BFIN_ICACHE_LOCK is not set
330# CONFIG_BFIN_WB is not set 330CONFIG_BFIN_WB=y
331CONFIG_BFIN_WT=y 331# CONFIG_BFIN_WT is not set
332# CONFIG_MPU is not set 332# CONFIG_MPU is not set
333 333
334# 334#
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 334c94b51c40..0a2a00d63887 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y
290CONFIG_BFIN_DCACHE=y 290CONFIG_BFIN_DCACHE=y
291# CONFIG_BFIN_DCACHE_BANKA is not set 291# CONFIG_BFIN_DCACHE_BANKA is not set
292# CONFIG_BFIN_ICACHE_LOCK is not set 292# CONFIG_BFIN_ICACHE_LOCK is not set
293# CONFIG_BFIN_WB is not set 293CONFIG_BFIN_WB=y
294CONFIG_BFIN_WT=y 294# CONFIG_BFIN_WT is not set
295# CONFIG_MPU is not set 295# CONFIG_MPU is not set
296 296
297# 297#
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index 9d733436e300..eb027587a355 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y
290CONFIG_BFIN_DCACHE=y 290CONFIG_BFIN_DCACHE=y
291# CONFIG_BFIN_DCACHE_BANKA is not set 291# CONFIG_BFIN_DCACHE_BANKA is not set
292# CONFIG_BFIN_ICACHE_LOCK is not set 292# CONFIG_BFIN_ICACHE_LOCK is not set
293# CONFIG_BFIN_WB is not set 293CONFIG_BFIN_WB=y
294CONFIG_BFIN_WT=y 294# CONFIG_BFIN_WT is not set
295# CONFIG_MPU is not set 295# CONFIG_MPU is not set
296 296
297# 297#
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 4fb4108d3103..9e62b9f40eb1 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -298,8 +298,8 @@ CONFIG_BFIN_ICACHE=y
298CONFIG_BFIN_DCACHE=y 298CONFIG_BFIN_DCACHE=y
299# CONFIG_BFIN_DCACHE_BANKA is not set 299# CONFIG_BFIN_DCACHE_BANKA is not set
300# CONFIG_BFIN_ICACHE_LOCK is not set 300# CONFIG_BFIN_ICACHE_LOCK is not set
301# CONFIG_BFIN_WB is not set 301CONFIG_BFIN_WB=y
302CONFIG_BFIN_WT=y 302# CONFIG_BFIN_WT is not set
303# CONFIG_MPU is not set 303# CONFIG_MPU is not set
304 304
305# 305#
@@ -568,15 +568,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
568# CONFIG_MTD_DOC2000 is not set 568# CONFIG_MTD_DOC2000 is not set
569# CONFIG_MTD_DOC2001 is not set 569# CONFIG_MTD_DOC2001 is not set
570# CONFIG_MTD_DOC2001PLUS is not set 570# CONFIG_MTD_DOC2001PLUS is not set
571CONFIG_MTD_NAND=m 571# CONFIG_MTD_NAND is not set
572# CONFIG_MTD_NAND_VERIFY_WRITE is not set
573# CONFIG_MTD_NAND_ECC_SMC is not set
574# CONFIG_MTD_NAND_MUSEUM_IDS is not set
575# CONFIG_MTD_NAND_BFIN is not set
576CONFIG_MTD_NAND_IDS=m
577# CONFIG_MTD_NAND_DISKONCHIP is not set
578# CONFIG_MTD_NAND_NANDSIM is not set
579CONFIG_MTD_NAND_PLATFORM=m
580# CONFIG_MTD_ONENAND is not set 572# CONFIG_MTD_ONENAND is not set
581 573
582# 574#
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index cb32f5624a1b..dd6ad6be1c87 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -306,8 +306,8 @@ CONFIG_BFIN_ICACHE=y
306CONFIG_BFIN_DCACHE=y 306CONFIG_BFIN_DCACHE=y
307# CONFIG_BFIN_DCACHE_BANKA is not set 307# CONFIG_BFIN_DCACHE_BANKA is not set
308# CONFIG_BFIN_ICACHE_LOCK is not set 308# CONFIG_BFIN_ICACHE_LOCK is not set
309# CONFIG_BFIN_WB is not set 309CONFIG_BFIN_WB=y
310CONFIG_BFIN_WT=y 310# CONFIG_BFIN_WT is not set
311# CONFIG_MPU is not set 311# CONFIG_MPU is not set
312 312
313# 313#
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 0f8697618aa5..6bc2fb1b2a70 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -361,8 +361,8 @@ CONFIG_BFIN_ICACHE=y
361CONFIG_BFIN_DCACHE=y 361CONFIG_BFIN_DCACHE=y
362# CONFIG_BFIN_DCACHE_BANKA is not set 362# CONFIG_BFIN_DCACHE_BANKA is not set
363# CONFIG_BFIN_ICACHE_LOCK is not set 363# CONFIG_BFIN_ICACHE_LOCK is not set
364# CONFIG_BFIN_WB is not set 364CONFIG_BFIN_WB=y
365CONFIG_BFIN_WT=y 365# CONFIG_BFIN_WT is not set
366# CONFIG_BFIN_L2_CACHEABLE is not set 366# CONFIG_BFIN_L2_CACHEABLE is not set
367# CONFIG_MPU is not set 367# CONFIG_MPU is not set
368 368
@@ -680,7 +680,7 @@ CONFIG_SCSI=y
680CONFIG_SCSI_DMA=y 680CONFIG_SCSI_DMA=y
681# CONFIG_SCSI_TGT is not set 681# CONFIG_SCSI_TGT is not set
682# CONFIG_SCSI_NETLINK is not set 682# CONFIG_SCSI_NETLINK is not set
683CONFIG_SCSI_PROC_FS=y 683# CONFIG_SCSI_PROC_FS is not set
684 684
685# 685#
686# SCSI support type (disk, tape, CD-ROM) 686# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 042c7adfccfa..69714fb3e608 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -329,8 +329,8 @@ CONFIG_BFIN_ICACHE=y
329CONFIG_BFIN_DCACHE=y 329CONFIG_BFIN_DCACHE=y
330# CONFIG_BFIN_DCACHE_BANKA is not set 330# CONFIG_BFIN_DCACHE_BANKA is not set
331# CONFIG_BFIN_ICACHE_LOCK is not set 331# CONFIG_BFIN_ICACHE_LOCK is not set
332# CONFIG_BFIN_WB is not set 332CONFIG_BFIN_WB=y
333CONFIG_BFIN_WT=y 333# CONFIG_BFIN_WT is not set
334# CONFIG_BFIN_L2_CACHEABLE is not set 334# CONFIG_BFIN_L2_CACHEABLE is not set
335# CONFIG_MPU is not set 335# CONFIG_MPU is not set
336 336
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 3a20e281d23c..017c6ea071b5 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -288,8 +288,8 @@ CONFIG_BFIN_ICACHE=y
288CONFIG_BFIN_DCACHE=y 288CONFIG_BFIN_DCACHE=y
289# CONFIG_BFIN_DCACHE_BANKA is not set 289# CONFIG_BFIN_DCACHE_BANKA is not set
290# CONFIG_BFIN_ICACHE_LOCK is not set 290# CONFIG_BFIN_ICACHE_LOCK is not set
291# CONFIG_BFIN_WB is not set 291CONFIG_BFIN_WB=y
292CONFIG_BFIN_WT=y 292# CONFIG_BFIN_WT is not set
293# CONFIG_MPU is not set 293# CONFIG_MPU is not set
294 294
295# 295#
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index 865ed85a5760..d880ef786770 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -332,8 +332,8 @@ CONFIG_BFIN_ICACHE=y
332CONFIG_BFIN_DCACHE=y 332CONFIG_BFIN_DCACHE=y
333# CONFIG_BFIN_DCACHE_BANKA is not set 333# CONFIG_BFIN_DCACHE_BANKA is not set
334# CONFIG_BFIN_ICACHE_LOCK is not set 334# CONFIG_BFIN_ICACHE_LOCK is not set
335# CONFIG_BFIN_WB is not set 335CONFIG_BFIN_WB=y
336CONFIG_BFIN_WT=y 336# CONFIG_BFIN_WT is not set
337# CONFIG_MPU is not set 337# CONFIG_MPU is not set
338 338
339# 339#
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index efe9741b1f14..f410430b4e3d 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -336,8 +336,8 @@ CONFIG_BFIN_ICACHE=y
336CONFIG_BFIN_DCACHE=y 336CONFIG_BFIN_DCACHE=y
337# CONFIG_BFIN_DCACHE_BANKA is not set 337# CONFIG_BFIN_DCACHE_BANKA is not set
338# CONFIG_BFIN_ICACHE_LOCK is not set 338# CONFIG_BFIN_ICACHE_LOCK is not set
339# CONFIG_BFIN_WB is not set 339CONFIG_BFIN_WB=y
340CONFIG_BFIN_WT=y 340# CONFIG_BFIN_WT is not set
341CONFIG_L1_MAX_PIECE=16 341CONFIG_L1_MAX_PIECE=16
342# CONFIG_MPU is not set 342# CONFIG_MPU is not set
343 343
@@ -595,7 +595,7 @@ CONFIG_SCSI=y
595CONFIG_SCSI_DMA=y 595CONFIG_SCSI_DMA=y
596# CONFIG_SCSI_TGT is not set 596# CONFIG_SCSI_TGT is not set
597# CONFIG_SCSI_NETLINK is not set 597# CONFIG_SCSI_NETLINK is not set
598CONFIG_SCSI_PROC_FS=y 598# CONFIG_SCSI_PROC_FS is not set
599 599
600# 600#
601# SCSI support type (disk, tape, CD-ROM) 601# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
index eae83b5de92f..7db93874c987 100644
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@@ -612,7 +612,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
612CONFIG_SCSI=y 612CONFIG_SCSI=y
613# CONFIG_SCSI_TGT is not set 613# CONFIG_SCSI_TGT is not set
614# CONFIG_SCSI_NETLINK is not set 614# CONFIG_SCSI_NETLINK is not set
615CONFIG_SCSI_PROC_FS=y 615# CONFIG_SCSI_PROC_FS is not set
616 616
617# 617#
618# SCSI support type (disk, tape, CD-ROM) 618# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index fa580affc9d6..a46529c6ade3 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -282,8 +282,8 @@ CONFIG_BFIN_ICACHE=y
282CONFIG_BFIN_DCACHE=y 282CONFIG_BFIN_DCACHE=y
283# CONFIG_BFIN_DCACHE_BANKA is not set 283# CONFIG_BFIN_DCACHE_BANKA is not set
284# CONFIG_BFIN_ICACHE_LOCK is not set 284# CONFIG_BFIN_ICACHE_LOCK is not set
285# CONFIG_BFIN_WB is not set 285CONFIG_BFIN_WB=y
286CONFIG_BFIN_WT=y 286# CONFIG_BFIN_WT is not set
287CONFIG_L1_MAX_PIECE=16 287CONFIG_L1_MAX_PIECE=16
288 288
289# 289#
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index 606ecfdcc962..09c31418cc08 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,3 +1,4 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3unifdef-y += bfin_sport.h
3unifdef-y += fixed_code.h 4unifdef-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index fe88a2c19213..65a651db5b07 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -1,30 +1,9 @@
1/* 1/*
2 * File: include/asm-blackfin/bfin_sport.h 2 * bfin_sport.h - userspace header for bfin sport driver
3 * Based on:
4 * Author: Roy Huang (roy.huang@analog.com)
5 * 3 *
6 * Created: Thu Aug. 24 2006 4 * Copyright 2004-2008 Analog Devices Inc.
7 * Description:
8 * 5 *
9 * Modified: 6 * Licensed under the GPL-2 or later.
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 7 */
29 8
30#ifndef __BFIN_SPORT_H__ 9#ifndef __BFIN_SPORT_H__
@@ -42,11 +21,10 @@
42#define NORM_FORMAT 0x0 21#define NORM_FORMAT 0x0
43#define ALAW_FORMAT 0x2 22#define ALAW_FORMAT 0x2
44#define ULAW_FORMAT 0x3 23#define ULAW_FORMAT 0x3
45struct sport_register;
46 24
47/* Function driver which use sport must initialize the structure */ 25/* Function driver which use sport must initialize the structure */
48struct sport_config { 26struct sport_config {
49 /*TDM (multichannels), I2S or other mode */ 27 /* TDM (multichannels), I2S or other mode */
50 unsigned int mode:3; 28 unsigned int mode:3;
51 29
52 /* if TDM mode is selected, channels must be set */ 30 /* if TDM mode is selected, channels must be set */
@@ -72,12 +50,18 @@ struct sport_config {
72 int serial_clk; 50 int serial_clk;
73 int fsync_clk; 51 int fsync_clk;
74 52
75 unsigned int data_format:2; /*Normal, u-law or a-law */ 53 unsigned int data_format:2; /* Normal, u-law or a-law */
76 54
77 int word_len; /* How length of the word in bits, 3-32 bits */ 55 int word_len; /* How length of the word in bits, 3-32 bits */
78 int dma_enabled; 56 int dma_enabled;
79}; 57};
80 58
59/* Userspace interface */
60#define SPORT_IOC_MAGIC 'P'
61#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
62
63#ifdef __KERNEL__
64
81struct sport_register { 65struct sport_register {
82 unsigned short tcr1; 66 unsigned short tcr1;
83 unsigned short reserved0; 67 unsigned short reserved0;
@@ -117,9 +101,6 @@ struct sport_register {
117 unsigned long mrcs3; 101 unsigned long mrcs3;
118}; 102};
119 103
120#define SPORT_IOC_MAGIC 'P'
121#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
122
123struct sport_dev { 104struct sport_dev {
124 struct cdev cdev; /* Char device structure */ 105 struct cdev cdev; /* Char device structure */
125 106
@@ -149,6 +130,8 @@ struct sport_dev {
149 struct sport_config config; 130 struct sport_config config;
150}; 131};
151 132
133#endif
134
152#define SPORT_TCR1 0 135#define SPORT_TCR1 0
153#define SPORT_TCR2 1 136#define SPORT_TCR2 1
154#define SPORT_TCLKDIV 2 137#define SPORT_TCLKDIV 2
@@ -169,4 +152,4 @@ struct sport_dev {
169#define SPORT_MRCS2 22 152#define SPORT_MRCS2 22
170#define SPORT_MRCS3 23 153#define SPORT_MRCS3 23
171 154
172#endif /*__BFIN_SPORT_H__*/ 155#endif
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 76f53d8b9a0d..343b56361ec9 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37 37
38#define IPIPE_ARCH_STRING "1.8-00" 38#define IPIPE_ARCH_STRING "1.9-00"
39#define IPIPE_MAJOR_NUMBER 1 39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 8 40#define IPIPE_MINOR_NUMBER 9
41#define IPIPE_PATCH_NUMBER 0 41#define IPIPE_PATCH_NUMBER 0
42 42
43#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
@@ -83,9 +83,9 @@ struct ipipe_sysinfo {
83 "%2 = CYCLES2\n" \ 83 "%2 = CYCLES2\n" \
84 "CC = %2 == %0\n" \ 84 "CC = %2 == %0\n" \
85 "if ! CC jump 1b\n" \ 85 "if ! CC jump 1b\n" \
86 : "=r" (((unsigned long *)&t)[1]), \ 86 : "=d,a" (((unsigned long *)&t)[1]), \
87 "=r" (((unsigned long *)&t)[0]), \ 87 "=d,a" (((unsigned long *)&t)[0]), \
88 "=r" (__cy2) \ 88 "=d,a" (__cy2) \
89 : /*no input*/ : "CC"); \ 89 : /*no input*/ : "CC"); \
90 t; \ 90 t; \
91 }) 91 })
@@ -118,35 +118,40 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
118 118
119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) 119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq))
120 120
121#define __ipipe_lock_root() \ 121static inline int __ipipe_check_tickdev(const char *devname)
122 set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) 122{
123 return 1;
124}
123 125
124#define __ipipe_unlock_root() \ 126static inline void __ipipe_lock_root(void)
125 clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) 127{
128 set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
129}
130
131static inline void __ipipe_unlock_root(void)
132{
133 clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
134}
126 135
127void __ipipe_enable_pipeline(void); 136void __ipipe_enable_pipeline(void);
128 137
129#define __ipipe_hook_critical_ipi(ipd) do { } while (0) 138#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
130 139
131#define __ipipe_sync_pipeline(syncmask) \ 140#define __ipipe_sync_pipeline ___ipipe_sync_pipeline
132 do { \ 141void ___ipipe_sync_pipeline(unsigned long syncmask);
133 struct ipipe_domain *ipd = ipipe_current_domain; \
134 if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \
135 __ipipe_sync_stage(syncmask); \
136 } while (0)
137 142
138void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); 143void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
139 144
140int __ipipe_get_irq_priority(unsigned irq); 145int __ipipe_get_irq_priority(unsigned irq);
141 146
142int __ipipe_get_irqthread_priority(unsigned irq);
143
144void __ipipe_stall_root_raw(void); 147void __ipipe_stall_root_raw(void);
145 148
146void __ipipe_unstall_root_raw(void); 149void __ipipe_unstall_root_raw(void);
147 150
148void __ipipe_serial_debug(const char *fmt, ...); 151void __ipipe_serial_debug(const char *fmt, ...);
149 152
153asmlinkage void __ipipe_call_irqtail(unsigned long addr);
154
150DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); 155DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
151 156
152extern unsigned long __ipipe_core_clock; 157extern unsigned long __ipipe_core_clock;
@@ -162,42 +167,25 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
162 167
163#define __ipipe_run_irqtail() /* Must be a macro */ \ 168#define __ipipe_run_irqtail() /* Must be a macro */ \
164 do { \ 169 do { \
165 asmlinkage void __ipipe_call_irqtail(void); \
166 unsigned long __pending; \ 170 unsigned long __pending; \
167 CSYNC(); \ 171 CSYNC(); \
168 __pending = bfin_read_IPEND(); \ 172 __pending = bfin_read_IPEND(); \
169 if (__pending & 0x8000) { \ 173 if (__pending & 0x8000) { \
170 __pending &= ~0x8010; \ 174 __pending &= ~0x8010; \
171 if (__pending && (__pending & (__pending - 1)) == 0) \ 175 if (__pending && (__pending & (__pending - 1)) == 0) \
172 __ipipe_call_irqtail(); \ 176 __ipipe_call_irqtail(__ipipe_irq_tail_hook); \
173 } \ 177 } \
174 } while (0) 178 } while (0)
175 179
176#define __ipipe_run_isr(ipd, irq) \ 180#define __ipipe_run_isr(ipd, irq) \
177 do { \ 181 do { \
178 if (ipd == ipipe_root_domain) { \ 182 if (ipd == ipipe_root_domain) { \
179 /* \ 183 local_irq_enable_hw(); \
180 * Note: the I-pipe implements a threaded interrupt model on \ 184 if (ipipe_virtual_irq_p(irq)) \
181 * this arch for Linux external IRQs. The interrupt handler we \
182 * call here only wakes up the associated IRQ thread. \
183 */ \
184 if (ipipe_virtual_irq_p(irq)) { \
185 /* No irqtail here; virtual interrupts have no effect \
186 on IPEND so there is no need for processing \
187 deferral. */ \
188 local_irq_enable_nohead(ipd); \
189 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ 185 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
190 local_irq_disable_nohead(ipd); \ 186 else \
191 } else \
192 /* \
193 * No need to run the irqtail here either; \
194 * we can't be preempted by hw IRQs, so \
195 * non-Linux IRQs cannot stack over the short \
196 * thread wakeup code. Which in turn means \
197 * that no irqtail condition could be pending \
198 * for domains above Linux in the pipeline. \
199 */ \
200 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ 187 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
188 local_irq_disable_hw(); \
201 } else { \ 189 } else { \
202 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ 190 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
203 local_irq_enable_nohead(ipd); \ 191 local_irq_enable_nohead(ipd); \
@@ -217,42 +205,24 @@ void ipipe_init_irq_threads(void);
217 205
218int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); 206int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
219 207
220#define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS) 208#ifdef CONFIG_GENERIC_CLOCKEVENTS
221#define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS) 209#define IRQ_SYSTMR IRQ_CORETMR
222 210#define IRQ_PRIOTMR IRQ_CORETMR
211#else
223#define IRQ_SYSTMR IRQ_TIMER0 212#define IRQ_SYSTMR IRQ_TIMER0
224#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 213#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
214#endif
225 215
226#if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) 216#ifdef CONFIG_BF561
227#define PRIO_GPIODEMUX(irq) CONFIG_PFA
228#elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
229#define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA
230#elif defined(CONFIG_BF52x)
231#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \
232 (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \
233 (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \
234 -1)
235#elif defined(CONFIG_BF561)
236#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \
237 (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \
238 (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \
239 -1)
240#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) 217#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
241#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) 218#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
242#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) 219#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
243#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() 220#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
244#elif defined(CONFIG_BF54x) 221#elif defined(CONFIG_BF54x)
245#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \
246 (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \
247 (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \
248 (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \
249 -1)
250#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) 222#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
251#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) 223#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
252#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) 224#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
253#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) 225#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
254#else
255# error "no PRIO_GPIODEMUX() for this part"
256#endif 226#endif
257 227
258#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) 228#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
@@ -275,4 +245,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
275 245
276#endif /* !CONFIG_IPIPE */ 246#endif /* !CONFIG_IPIPE */
277 247
248#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
249
278#endif /* !__ASM_BLACKFIN_IPIPE_H */ 250#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index cb1025aeabcf..3e8acbd1a3be 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -1,5 +1,5 @@
1/* -*- linux-c -*- 1/* -*- linux-c -*-
2 * include/asm-blackfin/_baseipipe.h 2 * include/asm-blackfin/ipipe_base.h
3 * 3 *
4 * Copyright (C) 2007 Philippe Gerum. 4 * Copyright (C) 2007 Philippe Gerum.
5 * 5 *
@@ -27,8 +27,9 @@
27#define IPIPE_NR_XIRQS NR_IRQS 27#define IPIPE_NR_XIRQS NR_IRQS
28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ 28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
29 29
30/* Blackfin-specific, global domain flags */ 30/* Blackfin-specific, per-cpu pipeline status */
31#define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */ 31#define IPIPE_SYNCDEFER_FLAG 15
32#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK)
32 33
33 /* Blackfin traps -- i.e. exception vector numbers */ 34 /* Blackfin traps -- i.e. exception vector numbers */
34#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ 35#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
@@ -48,11 +49,6 @@
48 49
49#ifndef __ASSEMBLY__ 50#ifndef __ASSEMBLY__
50 51
51#include <linux/bitops.h>
52
53extern int test_bit(int nr, const void *addr);
54
55
56extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ 52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
57 53
58static inline void __ipipe_stall_root(void) 54static inline void __ipipe_stall_root(void)
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 3d977909ce7d..7645e85a5f6f 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -61,20 +61,38 @@ void __ipipe_restore_root(unsigned long flags);
61#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) 61#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags))
62#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) 62#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x)
63 63
64#define local_save_flags(x) \ 64#define local_save_flags(x) \
65 do { \ 65 do { \
66 (x) = __ipipe_test_root() ? \ 66 (x) = __ipipe_test_root() ? \
67 __all_masked_irq_flags : bfin_irq_flags; \ 67 __all_masked_irq_flags : bfin_irq_flags; \
68 barrier(); \
68 } while (0) 69 } while (0)
69 70
70#define local_irq_save(x) \ 71#define local_irq_save(x) \
71 do { \ 72 do { \
72 (x) = __ipipe_test_and_stall_root(); \ 73 (x) = __ipipe_test_and_stall_root() ? \
74 __all_masked_irq_flags : bfin_irq_flags; \
75 barrier(); \
76 } while (0)
77
78static inline void local_irq_restore(unsigned long x)
79{
80 barrier();
81 __ipipe_restore_root(x == __all_masked_irq_flags);
82}
83
84#define local_irq_disable() \
85 do { \
86 __ipipe_stall_root(); \
87 barrier(); \
73 } while (0) 88 } while (0)
74 89
75#define local_irq_restore(x) __ipipe_restore_root(x) 90static inline void local_irq_enable(void)
76#define local_irq_disable() __ipipe_stall_root() 91{
77#define local_irq_enable() __ipipe_unstall_root() 92 barrier();
93 __ipipe_unstall_root();
94}
95
78#define irqs_disabled() __ipipe_test_root() 96#define irqs_disabled() __ipipe_test_root()
79 97
80#define local_save_flags_hw(x) \ 98#define local_save_flags_hw(x) \
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index e721ce55956c..2920087516f2 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -122,6 +122,7 @@ static inline struct thread_info *current_thread_info(void)
122#define TIF_MEMDIE 4 122#define TIF_MEMDIE 4
123#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ 123#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
124#define TIF_FREEZE 6 /* is freezing for suspend */ 124#define TIF_FREEZE 6 /* is freezing for suspend */
125#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
125 126
126/* as above, but as bit values */ 127/* as above, but as bit values */
127#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 128#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -130,6 +131,7 @@ static inline struct thread_info *current_thread_info(void)
130#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 131#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
131#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) 132#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
132#define _TIF_FREEZE (1<<TIF_FREEZE) 133#define _TIF_FREEZE (1<<TIF_FREEZE)
134#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
133 135
134#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ 136#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
135 137
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 4a92a86824b7..fd4d4328a0f2 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -15,13 +15,15 @@ else
15 obj-y += time.o 15 obj-y += time.o
16endif 16endif
17 17
18CFLAGS_kgdb_test.o := -mlong-calls -O0
19
20obj-$(CONFIG_IPIPE) += ipipe.o 18obj-$(CONFIG_IPIPE) += ipipe.o
21obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o 19obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o
22obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o 20obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
23obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 21obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
24obj-$(CONFIG_MODULES) += module.o 22obj-$(CONFIG_MODULES) += module.o
25obj-$(CONFIG_KGDB) += kgdb.o 23obj-$(CONFIG_KGDB) += kgdb.o
26obj-$(CONFIG_KGDB_TESTCASE) += kgdb_test.o 24obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o
27obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 25obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
26
27# the kgdb test puts code into L2 and without linker
28# relaxation, we need to force long calls to/from it
29CFLAGS_kgdb_test.o := -mlong-calls -O0
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 0e28f7595733..d6c067782e63 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -53,9 +53,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
53 53
54 i_d = i_i = 0; 54 i_d = i_i = 0;
55 55
56#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
56 /* Set up the zero page. */ 57 /* Set up the zero page. */
57 d_tbl[i_d].addr = 0; 58 d_tbl[i_d].addr = 0;
58 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; 59 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
60 i_tbl[i_i].addr = 0;
61 i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
62#endif
59 63
60 /* Cover kernel memory with 4M pages. */ 64 /* Cover kernel memory with 4M pages. */
61 addr = 0; 65 addr = 0;
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 339be5a3ae6a..a5de8d45424c 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -35,14 +35,8 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/io.h> 36#include <asm/io.h>
37 37
38static int create_irq_threads;
39
40DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); 38DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
41 39
42static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask);
43
44static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count);
45
46asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); 40asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
47 41
48static void __ipipe_no_irqtail(void); 42static void __ipipe_no_irqtail(void);
@@ -93,6 +87,7 @@ void __ipipe_enable_pipeline(void)
93 */ 87 */
94void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) 88void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
95{ 89{
90 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
96 struct ipipe_domain *this_domain, *next_domain; 91 struct ipipe_domain *this_domain, *next_domain;
97 struct list_head *head, *pos; 92 struct list_head *head, *pos;
98 int m_ack, s = -1; 93 int m_ack, s = -1;
@@ -104,7 +99,6 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
104 * interrupt. 99 * interrupt.
105 */ 100 */
106 m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); 101 m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
107
108 this_domain = ipipe_current_domain; 102 this_domain = ipipe_current_domain;
109 103
110 if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) 104 if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control)))
@@ -114,49 +108,28 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
114 next_domain = list_entry(head, struct ipipe_domain, p_link); 108 next_domain = list_entry(head, struct ipipe_domain, p_link);
115 if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { 109 if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) {
116 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) 110 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL)
117 next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); 111 next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq));
118 if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) 112 if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
119 s = __test_and_set_bit(IPIPE_STALL_FLAG, 113 s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
120 &ipipe_root_cpudom_var(status));
121 __ipipe_dispatch_wired(next_domain, irq); 114 __ipipe_dispatch_wired(next_domain, irq);
122 goto finalize; 115 goto out;
123 return;
124 } 116 }
125 } 117 }
126 118
127 /* Ack the interrupt. */ 119 /* Ack the interrupt. */
128 120
129 pos = head; 121 pos = head;
130
131 while (pos != &__ipipe_pipeline) { 122 while (pos != &__ipipe_pipeline) {
132 next_domain = list_entry(pos, struct ipipe_domain, p_link); 123 next_domain = list_entry(pos, struct ipipe_domain, p_link);
133 /*
134 * For each domain handling the incoming IRQ, mark it
135 * as pending in its log.
136 */
137 if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { 124 if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) {
138 /*
139 * Domains that handle this IRQ are polled for
140 * acknowledging it by decreasing priority
141 * order. The interrupt must be made pending
142 * _first_ in the domain's status flags before
143 * the PIC is unlocked.
144 */
145 __ipipe_set_irq_pending(next_domain, irq); 125 __ipipe_set_irq_pending(next_domain, irq);
146
147 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { 126 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) {
148 next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); 127 next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq));
149 m_ack = 1; 128 m_ack = 1;
150 } 129 }
151 } 130 }
152
153 /*
154 * If the domain does not want the IRQ to be passed
155 * down the interrupt pipe, exit the loop now.
156 */
157 if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) 131 if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control))
158 break; 132 break;
159
160 pos = next_domain->p_link.next; 133 pos = next_domain->p_link.next;
161 } 134 }
162 135
@@ -166,18 +139,24 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
166 * immediately to the current domain if the interrupt has been 139 * immediately to the current domain if the interrupt has been
167 * marked as 'sticky'. This search does not go beyond the 140 * marked as 'sticky'. This search does not go beyond the
168 * current domain in the pipeline. We also enforce the 141 * current domain in the pipeline. We also enforce the
169 * additional root stage lock (blackfin-specific). */ 142 * additional root stage lock (blackfin-specific).
143 */
144 if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
145 s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
170 146
171 if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) 147 /*
172 s = __test_and_set_bit(IPIPE_STALL_FLAG, 148 * If the interrupt preempted the head domain, then do not
173 &ipipe_root_cpudom_var(status)); 149 * even try to walk the pipeline, unless an interrupt is
174finalize: 150 * pending for it.
151 */
152 if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
153 ipipe_head_cpudom_var(irqpend_himask) == 0)
154 goto out;
175 155
176 __ipipe_walk_pipeline(head); 156 __ipipe_walk_pipeline(head);
177 157out:
178 if (!s) 158 if (!s)
179 __clear_bit(IPIPE_STALL_FLAG, 159 __clear_bit(IPIPE_STALL_FLAG, &p->status);
180 &ipipe_root_cpudom_var(status));
181} 160}
182 161
183int __ipipe_check_root(void) 162int __ipipe_check_root(void)
@@ -187,7 +166,7 @@ int __ipipe_check_root(void)
187 166
188void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) 167void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
189{ 168{
190 struct irq_desc *desc = irq_desc + irq; 169 struct irq_desc *desc = irq_to_desc(irq);
191 int prio = desc->ic_prio; 170 int prio = desc->ic_prio;
192 171
193 desc->depth = 0; 172 desc->depth = 0;
@@ -199,7 +178,7 @@ EXPORT_SYMBOL(__ipipe_enable_irqdesc);
199 178
200void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) 179void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
201{ 180{
202 struct irq_desc *desc = irq_desc + irq; 181 struct irq_desc *desc = irq_to_desc(irq);
203 int prio = desc->ic_prio; 182 int prio = desc->ic_prio;
204 183
205 if (ipd != &ipipe_root && 184 if (ipd != &ipipe_root &&
@@ -236,15 +215,18 @@ int __ipipe_syscall_root(struct pt_regs *regs)
236{ 215{
237 unsigned long flags; 216 unsigned long flags;
238 217
239 /* We need to run the IRQ tail hook whenever we don't 218 /*
219 * We need to run the IRQ tail hook whenever we don't
240 * propagate a syscall to higher domains, because we know that 220 * propagate a syscall to higher domains, because we know that
241 * important operations might be pending there (e.g. Xenomai 221 * important operations might be pending there (e.g. Xenomai
242 * deferred rescheduling). */ 222 * deferred rescheduling).
223 */
243 224
244 if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) { 225 if (regs->orig_p0 < NR_syscalls) {
245 void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; 226 void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
246 hook(); 227 hook();
247 return 0; 228 if ((current->flags & PF_EVNOTIFY) == 0)
229 return 0;
248 } 230 }
249 231
250 /* 232 /*
@@ -312,112 +294,46 @@ int ipipe_trigger_irq(unsigned irq)
312{ 294{
313 unsigned long flags; 295 unsigned long flags;
314 296
297#ifdef CONFIG_IPIPE_DEBUG
315 if (irq >= IPIPE_NR_IRQS || 298 if (irq >= IPIPE_NR_IRQS ||
316 (ipipe_virtual_irq_p(irq) 299 (ipipe_virtual_irq_p(irq)
317 && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) 300 && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
318 return -EINVAL; 301 return -EINVAL;
302#endif
319 303
320 local_irq_save_hw(flags); 304 local_irq_save_hw(flags);
321
322 __ipipe_handle_irq(irq, NULL); 305 __ipipe_handle_irq(irq, NULL);
323
324 local_irq_restore_hw(flags); 306 local_irq_restore_hw(flags);
325 307
326 return 1; 308 return 1;
327} 309}
328 310
329/* Move Linux IRQ to threads. */ 311asmlinkage void __ipipe_sync_root(void)
330
331static int do_irqd(void *__desc)
332{ 312{
333 struct irq_desc *desc = __desc; 313 unsigned long flags;
334 unsigned irq = desc - irq_desc;
335 int thrprio = desc->thr_prio;
336 int thrmask = 1 << thrprio;
337 int cpu = smp_processor_id();
338 cpumask_t cpumask;
339
340 sigfillset(&current->blocked);
341 current->flags |= PF_NOFREEZE;
342 cpumask = cpumask_of_cpu(cpu);
343 set_cpus_allowed(current, cpumask);
344 ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio);
345
346 while (!kthread_should_stop()) {
347 local_irq_disable();
348 if (!(desc->status & IRQ_SCHEDULED)) {
349 set_current_state(TASK_INTERRUPTIBLE);
350resched:
351 local_irq_enable();
352 schedule();
353 local_irq_disable();
354 }
355 __set_current_state(TASK_RUNNING);
356 /*
357 * If higher priority interrupt servers are ready to
358 * run, reschedule immediately. We need this for the
359 * GPIO demux IRQ handler to unmask the interrupt line
360 * _last_, after all GPIO IRQs have run.
361 */
362 if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1)))
363 goto resched;
364 if (--per_cpu(pending_irq_count[thrprio], cpu) == 0)
365 per_cpu(pending_irqthread_mask, cpu) &= ~thrmask;
366 desc->status &= ~IRQ_SCHEDULED;
367 desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs));
368 local_irq_enable();
369 }
370 __set_current_state(TASK_RUNNING);
371 return 0;
372}
373 314
374static void kick_irqd(unsigned irq, void *cookie) 315 BUG_ON(irqs_disabled());
375{
376 struct irq_desc *desc = irq_desc + irq;
377 int thrprio = desc->thr_prio;
378 int thrmask = 1 << thrprio;
379 int cpu = smp_processor_id();
380
381 if (!(desc->status & IRQ_SCHEDULED)) {
382 desc->status |= IRQ_SCHEDULED;
383 per_cpu(pending_irqthread_mask, cpu) |= thrmask;
384 ++per_cpu(pending_irq_count[thrprio], cpu);
385 wake_up_process(desc->thread);
386 }
387}
388 316
389int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc) 317 local_irq_save_hw(flags);
390{
391 if (desc->thread || !create_irq_threads)
392 return 0;
393
394 desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq);
395 if (desc->thread == NULL) {
396 printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq);
397 return -ENOMEM;
398 }
399 318
400 wake_up_process(desc->thread); 319 clear_thread_flag(TIF_IRQ_SYNC);
401 320
402 desc->thr_handler = ipipe_root_domain->irqs[irq].handler; 321 if (ipipe_root_cpudom_var(irqpend_himask) != 0)
403 ipipe_root_domain->irqs[irq].handler = &kick_irqd; 322 __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
404 323
405 return 0; 324 local_irq_restore_hw(flags);
406} 325}
407 326
408void __init ipipe_init_irq_threads(void) 327void ___ipipe_sync_pipeline(unsigned long syncmask)
409{ 328{
410 unsigned irq; 329 struct ipipe_domain *ipd = ipipe_current_domain;
411 struct irq_desc *desc;
412
413 create_irq_threads = 1;
414 330
415 for (irq = 0; irq < NR_IRQS; irq++) { 331 if (ipd == ipipe_root_domain) {
416 desc = irq_desc + irq; 332 if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
417 if (desc->action != NULL || 333 return;
418 (desc->status & IRQ_NOREQUEST) != 0)
419 ipipe_start_irq_thread(irq, desc);
420 } 334 }
335
336 __ipipe_sync_stage(syncmask);
421} 337}
422 338
423EXPORT_SYMBOL(show_stack); 339EXPORT_SYMBOL(show_stack);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 75724eee6494..7fd126564846 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -144,11 +144,15 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
144#endif 144#endif
145 generic_handle_irq(irq); 145 generic_handle_irq(irq);
146 146
147#ifndef CONFIG_IPIPE /* Useless and bugous over the I-pipe: IRQs are threaded. */ 147#ifndef CONFIG_IPIPE
148 /* If we're the only interrupt running (ignoring IRQ15 which is for 148 /*
149 syscalls), lower our priority to IRQ14 so that softirqs run at 149 * If we're the only interrupt running (ignoring IRQ15 which
150 that level. If there's another, lower-level interrupt, irq_exit 150 * is for syscalls), lower our priority to IRQ14 so that
151 will defer softirqs to that. */ 151 * softirqs run at that level. If there's another,
152 * lower-level interrupt, irq_exit will defer softirqs to
153 * that. If the interrupt pipeline is enabled, we are already
154 * running at IRQ14 priority, so we don't need this code.
155 */
152 CSYNC(); 156 CSYNC();
153 pending = bfin_read_IPEND() & ~0x8000; 157 pending = bfin_read_IPEND() & ~0x8000;
154 other_ints = pending & (pending - 1); 158 other_ints = pending & (pending - 1);
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 3dba9c17304a..dbcf3e45cb0b 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -20,6 +20,7 @@
20static char cmdline[256]; 20static char cmdline[256];
21static unsigned long len; 21static unsigned long len;
22 22
23#ifndef CONFIG_SMP
23static int num1 __attribute__((l1_data)); 24static int num1 __attribute__((l1_data));
24 25
25void kgdb_l1_test(void) __attribute__((l1_text)); 26void kgdb_l1_test(void) __attribute__((l1_text));
@@ -32,6 +33,8 @@ void kgdb_l1_test(void)
32 printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); 33 printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
33 return ; 34 return ;
34} 35}
36#endif
37
35#if L2_LENGTH 38#if L2_LENGTH
36 39
37static int num2 __attribute__((l2)); 40static int num2 __attribute__((l2));
@@ -59,10 +62,12 @@ int kgdb_test(char *name, int len, int count, int z)
59static int test_proc_output(char *buf) 62static int test_proc_output(char *buf)
60{ 63{
61 kgdb_test("hello world!", 12, 0x55, 0x10); 64 kgdb_test("hello world!", 12, 0x55, 0x10);
65#ifndef CONFIG_SMP
62 kgdb_l1_test(); 66 kgdb_l1_test();
63 #if L2_LENGTH 67#endif
68#if L2_LENGTH
64 kgdb_l2_test(); 69 kgdb_l2_test();
65 #endif 70#endif
66 71
67 return 0; 72 return 0;
68} 73}
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 594e325b40e4..d76618db50df 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -45,6 +45,7 @@
45#include <asm/asm-offsets.h> 45#include <asm/asm-offsets.h>
46#include <asm/dma.h> 46#include <asm/dma.h>
47#include <asm/fixed_code.h> 47#include <asm/fixed_code.h>
48#include <asm/cacheflush.h>
48#include <asm/mem_map.h> 49#include <asm/mem_map.h>
49 50
50#define TEXT_OFFSET 0 51#define TEXT_OFFSET 0
@@ -240,7 +241,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
240 241
241 } else if (addr >= FIXED_CODE_START 242 } else if (addr >= FIXED_CODE_START
242 && addr + sizeof(tmp) <= FIXED_CODE_END) { 243 && addr + sizeof(tmp) <= FIXED_CODE_END) {
243 memcpy(&tmp, (const void *)(addr), sizeof(tmp)); 244 copy_from_user_page(0, 0, 0, &tmp, (const void *)(addr), sizeof(tmp));
244 copied = sizeof(tmp); 245 copied = sizeof(tmp);
245 246
246 } else 247 } else
@@ -320,7 +321,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
320 321
321 } else if (addr >= FIXED_CODE_START 322 } else if (addr >= FIXED_CODE_START
322 && addr + sizeof(data) <= FIXED_CODE_END) { 323 && addr + sizeof(data) <= FIXED_CODE_END) {
323 memcpy((void *)(addr), &data, sizeof(data)); 324 copy_to_user_page(0, 0, 0, (void *)(addr), &data, sizeof(data));
324 copied = sizeof(data); 325 copied = sizeof(data);
325 326
326 } else 327 } else
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index e5c116230800..a58687bdee6a 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -889,6 +889,10 @@ void __init setup_arch(char **cmdline_p)
889 CPU, bfin_revid()); 889 CPU, bfin_revid());
890 } 890 }
891 891
892 /* We can't run on BF548-0.1 due to ANOMALY 05000448 */
893 if (bfin_cpuid() == 0x27de && bfin_revid() == 1)
894 panic("You can't run on this processor due to 05000448\n");
895
892 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); 896 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
893 897
894 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", 898 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
@@ -1141,12 +1145,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1141 icache_size = 0; 1145 icache_size = 0;
1142 1146
1143 seq_printf(m, "cache size\t: %d KB(L1 icache) " 1147 seq_printf(m, "cache size\t: %d KB(L1 icache) "
1144 "%d KB(L1 dcache-%s) %d KB(L2 cache)\n", 1148 "%d KB(L1 dcache%s) %d KB(L2 cache)\n",
1145 icache_size, dcache_size, 1149 icache_size, dcache_size,
1146#if defined CONFIG_BFIN_WB 1150#if defined CONFIG_BFIN_WB
1147 "wb" 1151 "-wb"
1148#elif defined CONFIG_BFIN_WT 1152#elif defined CONFIG_BFIN_WT
1149 "wt" 1153 "-wt"
1150#endif 1154#endif
1151 "", 0); 1155 "", 0);
1152 1156
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index 172b4c588467..1bbacfbd4c5d 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -134,7 +134,10 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
134 134
135 write_seqlock(&xtime_lock); 135 write_seqlock(&xtime_lock);
136#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) 136#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
137/* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */ 137 /*
138 * TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is
139 * enabled.
140 */
138 if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { 141 if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) {
139#endif 142#endif
140 do_timer(1); 143 do_timer(1);
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index 0e175342112e..41f2eacfef20 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -113,7 +113,6 @@ static struct platform_device bfin_mac_device = {
113 .name = "bfin_mac", 113 .name = "bfin_mac",
114 .dev.platform_data = &bfin_mii_bus, 114 .dev.platform_data = &bfin_mii_bus,
115}; 115};
116#endif
117 116
118#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 117#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
119static struct dsa_platform_data ksz8893m_switch_data = { 118static struct dsa_platform_data ksz8893m_switch_data = {
@@ -132,6 +131,7 @@ static struct platform_device ksz8893m_switch_device = {
132 .dev.platform_data = &ksz8893m_switch_data, 131 .dev.platform_data = &ksz8893m_switch_data,
133}; 132};
134#endif 133#endif
134#endif
135 135
136#if defined(CONFIG_MTD_M25P80) \ 136#if defined(CONFIG_MTD_M25P80) \
137 || defined(CONFIG_MTD_M25P80_MODULE) 137 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -171,6 +171,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
171}; 171};
172#endif 172#endif
173 173
174#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
174#if defined(CONFIG_NET_DSA_KSZ8893M) \ 175#if defined(CONFIG_NET_DSA_KSZ8893M) \
175 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 176 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
176/* SPI SWITCH CHIP */ 177/* SPI SWITCH CHIP */
@@ -179,10 +180,11 @@ static struct bfin5xx_spi_chip spi_switch_info = {
179 .bits_per_word = 8, 180 .bits_per_word = 8,
180}; 181};
181#endif 182#endif
183#endif
182 184
183#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 185#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
184static struct bfin5xx_spi_chip spi_mmc_chip_info = { 186static struct bfin5xx_spi_chip mmc_spi_chip_info = {
185 .enable_dma = 1, 187 .enable_dma = 0,
186 .bits_per_word = 8, 188 .bits_per_word = 8,
187}; 189};
188#endif 190#endif
@@ -259,6 +261,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
259 }, 261 },
260#endif 262#endif
261 263
264#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
262#if defined(CONFIG_NET_DSA_KSZ8893M) \ 265#if defined(CONFIG_NET_DSA_KSZ8893M) \
263 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 266 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
264 { 267 {
@@ -271,24 +274,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
271 .mode = SPI_MODE_3, 274 .mode = SPI_MODE_3,
272 }, 275 },
273#endif 276#endif
277#endif
274 278
275#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 279#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
276 { 280 {
277 .modalias = "spi_mmc_dummy", 281 .modalias = "mmc_spi",
278 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 282 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
279 .bus_num = 0, 283 .bus_num = 0,
280 .chip_select = 0, 284 .chip_select = 5,
281 .platform_data = NULL, 285 .controller_data = &mmc_spi_chip_info,
282 .controller_data = &spi_mmc_chip_info,
283 .mode = SPI_MODE_3,
284 },
285 {
286 .modalias = "spi_mmc",
287 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
288 .bus_num = 0,
289 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
290 .platform_data = NULL,
291 .controller_data = &spi_mmc_chip_info,
292 .mode = SPI_MODE_3, 286 .mode = SPI_MODE_3,
293 }, 287 },
294#endif 288#endif
@@ -630,11 +624,10 @@ static struct platform_device *stamp_devices[] __initdata = {
630#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 624#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
631 &bfin_mii_bus, 625 &bfin_mii_bus,
632 &bfin_mac_device, 626 &bfin_mac_device,
633#endif
634
635#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 627#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
636 &ksz8893m_switch_device, 628 &ksz8893m_switch_device,
637#endif 629#endif
630#endif
638 631
639#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 632#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
640 &bfin_spi0_device, 633 &bfin_spi0_device,
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index e5b4bef0edae..c847bb101076 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf518/anomaly.h 2 * File: include/asm-blackfin/mach-bf518/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - ???? 10 * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -19,6 +19,8 @@
19#define ANOMALY_05000122 (1) 19#define ANOMALY_05000122 (1)
20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
21#define ANOMALY_05000245 (1) 21#define ANOMALY_05000245 (1)
22/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
23#define ANOMALY_05000254 (1)
22/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
23#define ANOMALY_05000265 (1) 25#define ANOMALY_05000265 (1)
24/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 26/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
@@ -53,6 +55,12 @@
53#define ANOMALY_05000443 (1) 55#define ANOMALY_05000443 (1)
54/* Incorrect L1 Instruction Bank B Memory Map Location */ 56/* Incorrect L1 Instruction Bank B Memory Map Location */
55#define ANOMALY_05000444 (1) 57#define ANOMALY_05000444 (1)
58/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
59#define ANOMALY_05000452 (1)
60/* PWM_TRIPB Signal Not Available on PG10 */
61#define ANOMALY_05000453 (1)
62/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
63#define ANOMALY_05000455 (1)
56 64
57/* Anomalies that don't exist on this proc */ 65/* Anomalies that don't exist on this proc */
58#define ANOMALY_05000125 (0) 66#define ANOMALY_05000125 (0)
@@ -65,15 +73,20 @@
65#define ANOMALY_05000263 (0) 73#define ANOMALY_05000263 (0)
66#define ANOMALY_05000266 (0) 74#define ANOMALY_05000266 (0)
67#define ANOMALY_05000273 (0) 75#define ANOMALY_05000273 (0)
76#define ANOMALY_05000278 (0)
68#define ANOMALY_05000285 (0) 77#define ANOMALY_05000285 (0)
78#define ANOMALY_05000305 (0)
69#define ANOMALY_05000307 (0) 79#define ANOMALY_05000307 (0)
70#define ANOMALY_05000311 (0) 80#define ANOMALY_05000311 (0)
71#define ANOMALY_05000312 (0) 81#define ANOMALY_05000312 (0)
72#define ANOMALY_05000323 (0) 82#define ANOMALY_05000323 (0)
73#define ANOMALY_05000353 (0) 83#define ANOMALY_05000353 (0)
74#define ANOMALY_05000363 (0) 84#define ANOMALY_05000363 (0)
85#define ANOMALY_05000380 (0)
75#define ANOMALY_05000386 (0) 86#define ANOMALY_05000386 (0)
76#define ANOMALY_05000412 (0) 87#define ANOMALY_05000412 (0)
77#define ANOMALY_05000432 (0) 88#define ANOMALY_05000432 (0)
89#define ANOMALY_05000447 (0)
90#define ANOMALY_05000448 (0)
78 91
79#endif 92#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index b50a63b975a2..e21c1c3e4ec7 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 856c097b5317..48e69eecdba4 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -487,9 +487,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
487}; 487};
488#endif 488#endif
489 489
490#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 490#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
491static struct bfin5xx_spi_chip spi_mmc_chip_info = { 491static struct bfin5xx_spi_chip mmc_spi_chip_info = {
492 .enable_dma = 1, 492 .enable_dma = 0,
493 .bits_per_word = 8, 493 .bits_per_word = 8,
494}; 494};
495#endif 495#endif
@@ -585,23 +585,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
585 .controller_data = &ad9960_spi_chip_info, 585 .controller_data = &ad9960_spi_chip_info,
586 }, 586 },
587#endif 587#endif
588#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 588#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
589 { 589 {
590 .modalias = "spi_mmc_dummy", 590 .modalias = "mmc_spi",
591 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 591 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
592 .bus_num = 0,
593 .chip_select = 0,
594 .platform_data = NULL,
595 .controller_data = &spi_mmc_chip_info,
596 .mode = SPI_MODE_3,
597 },
598 {
599 .modalias = "spi_mmc",
600 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
601 .bus_num = 0, 592 .bus_num = 0,
602 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 593 .chip_select = 5,
603 .platform_data = NULL, 594 .controller_data = &mmc_spi_chip_info,
604 .controller_data = &spi_mmc_chip_info,
605 .mode = SPI_MODE_3, 595 .mode = SPI_MODE_3,
606 }, 596 },
607#endif 597#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 83606fcdde27..7fe480e4ebe8 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -256,9 +256,9 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
256}; 256};
257#endif 257#endif
258 258
259#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 259#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
260static struct bfin5xx_spi_chip spi_mmc_chip_info = { 260static struct bfin5xx_spi_chip mmc_spi_chip_info = {
261 .enable_dma = 1, 261 .enable_dma = 0,
262 .bits_per_word = 8, 262 .bits_per_word = 8,
263}; 263};
264#endif 264#endif
@@ -366,23 +366,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
366 }, 366 },
367#endif 367#endif
368 368
369#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 369#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
370 { 370 {
371 .modalias = "spi_mmc_dummy", 371 .modalias = "mmc_spi",
372 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 372 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
373 .bus_num = 0, 373 .bus_num = 0,
374 .chip_select = 0, 374 .chip_select = 5,
375 .platform_data = NULL, 375 .controller_data = &mmc_spi_chip_info,
376 .controller_data = &spi_mmc_chip_info,
377 .mode = SPI_MODE_3,
378 },
379 {
380 .modalias = "spi_mmc",
381 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
382 .bus_num = 0,
383 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
384 .platform_data = NULL,
385 .controller_data = &spi_mmc_chip_info,
386 .mode = SPI_MODE_3, 376 .mode = SPI_MODE_3,
387 }, 377 },
388#endif 378#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 035e8d835058..df6808d8a6ef 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf527/anomaly.h 2 * File: include/asm-blackfin/mach-bf527/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -167,12 +167,16 @@
167#define ANOMALY_05000263 (0) 167#define ANOMALY_05000263 (0)
168#define ANOMALY_05000266 (0) 168#define ANOMALY_05000266 (0)
169#define ANOMALY_05000273 (0) 169#define ANOMALY_05000273 (0)
170#define ANOMALY_05000278 (0)
170#define ANOMALY_05000285 (0) 171#define ANOMALY_05000285 (0)
172#define ANOMALY_05000305 (0)
171#define ANOMALY_05000307 (0) 173#define ANOMALY_05000307 (0)
172#define ANOMALY_05000311 (0) 174#define ANOMALY_05000311 (0)
173#define ANOMALY_05000312 (0) 175#define ANOMALY_05000312 (0)
174#define ANOMALY_05000323 (0) 176#define ANOMALY_05000323 (0)
175#define ANOMALY_05000363 (0) 177#define ANOMALY_05000363 (0)
176#define ANOMALY_05000412 (0) 178#define ANOMALY_05000412 (0)
179#define ANOMALY_05000447 (0)
180#define ANOMALY_05000448 (0)
177 181
178#endif 182#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
index 75722d6008b0..e8c41fd842b5 100644
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig
index 308c98dc5aba..8d8b3e7321e6 100644
--- a/arch/blackfin/mach-bf533/boards/Kconfig
+++ b/arch/blackfin/mach-bf533/boards/Kconfig
@@ -38,9 +38,4 @@ config BFIN532_IP0X
38 help 38 help
39 Core support for IP04/IP04 open hardware IP-PBX. 39 Core support for IP04/IP04 open hardware IP-PBX.
40 40
41config GENERIC_BF533_BOARD
42 bool "Generic"
43 help
44 Generic or Custom board support.
45
46endchoice 41endchoice
diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile
index 9afbe72b484f..ff1e832f80d2 100644
--- a/arch/blackfin/mach-bf533/boards/Makefile
+++ b/arch/blackfin/mach-bf533/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf533/boards/Makefile 2# arch/blackfin/mach-bf533/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF533_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN533_STAMP) += stamp.o 5obj-$(CONFIG_BFIN533_STAMP) += stamp.o
7obj-$(CONFIG_BFIN532_IP0X) += ip0x.o 6obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
8obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o 7obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 015c18f85e7f..0765872a8ada 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -101,9 +101,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
101}; 101};
102#endif 102#endif
103 103
104#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 104#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
105static struct bfin5xx_spi_chip spi_mmc_chip_info = { 105static struct bfin5xx_spi_chip mmc_spi_chip_info = {
106 .enable_dma = 1, 106 .enable_dma = 0,
107 .bits_per_word = 8, 107 .bits_per_word = 8,
108}; 108};
109#endif 109#endif
@@ -129,23 +129,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
129 }, 129 },
130#endif 130#endif
131 131
132#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 132#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
133 {
134 .modalias = "spi_mmc_dummy",
135 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
136 .bus_num = 0,
137 .chip_select = 0,
138 .platform_data = NULL,
139 .controller_data = &spi_mmc_chip_info,
140 .mode = SPI_MODE_3,
141 },
142 { 133 {
143 .modalias = "spi_mmc", 134 .modalias = "mmc_spi",
144 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 135 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
145 .bus_num = 0, 136 .bus_num = 0,
146 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 137 .chip_select = 5,
147 .platform_data = NULL, 138 .controller_data = &mmc_spi_chip_info,
148 .controller_data = &spi_mmc_chip_info,
149 .mode = SPI_MODE_3, 139 .mode = SPI_MODE_3,
150 }, 140 },
151#endif 141#endif
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index e7061c7e8c42..e8974878d8c2 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -96,9 +96,9 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
96}; 96};
97#endif 97#endif
98 98
99#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 99#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
100static struct bfin5xx_spi_chip spi_mmc_chip_info = { 100static struct bfin5xx_spi_chip mmc_spi_chip_info = {
101 .enable_dma = 1, 101 .enable_dma = 0,
102 .bits_per_word = 8, 102 .bits_per_word = 8,
103}; 103};
104#endif 104#endif
@@ -138,23 +138,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
138 }, 138 },
139#endif 139#endif
140 140
141#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 141#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
142 {
143 .modalias = "spi_mmc_dummy",
144 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
145 .bus_num = 0,
146 .chip_select = 0,
147 .platform_data = NULL,
148 .controller_data = &spi_mmc_chip_info,
149 .mode = SPI_MODE_3,
150 },
151 { 142 {
152 .modalias = "spi_mmc", 143 .modalias = "mmc_spi",
153 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 144 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
154 .bus_num = 0, 145 .bus_num = 0,
155 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 146 .chip_select = 5,
156 .platform_data = NULL, 147 .controller_data = &mmc_spi_chip_info,
157 .controller_data = &spi_mmc_chip_info,
158 .mode = SPI_MODE_3, 148 .mode = SPI_MODE_3,
159 }, 149 },
160#endif 150#endif
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c
deleted file mode 100644
index 986eeec53b1f..000000000000
--- a/arch/blackfin/mach-bf533/boards/generic_board.c
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf533/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created: 2005
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/irq.h>
34
35/*
36 * Name the Board for the /proc/cpuinfo
37 */
38const char bfin_board_name[] = "UNKNOWN BOARD";
39
40#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
41static struct platform_device rtc_device = {
42 .name = "rtc-bfin",
43 .id = -1,
44};
45#endif
46
47/*
48 * Driver needs to know address, irq and flag pin.
49 */
50#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
51static struct resource smc91x_resources[] = {
52 {
53 .start = 0x20300300,
54 .end = 0x20300300 + 16,
55 .flags = IORESOURCE_MEM,
56 }, {
57 .start = IRQ_PROG_INTB,
58 .end = IRQ_PROG_INTB,
59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
60 }, {
61 .start = IRQ_PF7,
62 .end = IRQ_PF7,
63 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
64 },
65};
66
67static struct platform_device smc91x_device = {
68 .name = "smc91x",
69 .id = 0,
70 .num_resources = ARRAY_SIZE(smc91x_resources),
71 .resource = smc91x_resources,
72};
73#endif
74
75#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
76#ifdef CONFIG_BFIN_SIR0
77static struct resource bfin_sir0_resources[] = {
78 {
79 .start = 0xFFC00400,
80 .end = 0xFFC004FF,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .start = IRQ_UART0_RX,
85 .end = IRQ_UART0_RX+1,
86 .flags = IORESOURCE_IRQ,
87 },
88 {
89 .start = CH_UART0_RX,
90 .end = CH_UART0_RX+1,
91 .flags = IORESOURCE_DMA,
92 },
93};
94
95static struct platform_device bfin_sir0_device = {
96 .name = "bfin_sir",
97 .id = 0,
98 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
99 .resource = bfin_sir0_resources,
100};
101#endif
102#endif
103
104static struct platform_device *generic_board_devices[] __initdata = {
105#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
106 &rtc_device,
107#endif
108
109#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
110 &smc91x_device,
111#endif
112
113#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
114#ifdef CONFIG_BFIN_SIR0
115 &bfin_sir0_device,
116#endif
117#endif
118};
119
120static int __init generic_board_init(void)
121{
122 printk(KERN_INFO "%s(): registering device resources\n", __func__);
123 return platform_add_devices(generic_board_devices, ARRAY_SIZE(generic_board_devices));
124}
125
126arch_initcall(generic_board_init);
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index e30b1b7d1442..f19b63378b12 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -127,8 +127,8 @@ static struct platform_device dm9000_device2 = {
127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
128/* all SPI peripherals info goes here */ 128/* all SPI peripherals info goes here */
129 129
130#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 130#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
131static struct bfin5xx_spi_chip spi_mmc_chip_info = { 131static struct bfin5xx_spi_chip mmc_spi_chip_info = {
132/* 132/*
133 * CPOL (Clock Polarity) 133 * CPOL (Clock Polarity)
134 * 0 - Active high SCK 134 * 0 - Active high SCK
@@ -152,14 +152,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
152/* Notice: for blackfin, the speed_hz is the value of register 152/* Notice: for blackfin, the speed_hz is the value of register
153 * SPI_BAUD, not the real baudrate */ 153 * SPI_BAUD, not the real baudrate */
154static struct spi_board_info bfin_spi_board_info[] __initdata = { 154static struct spi_board_info bfin_spi_board_info[] __initdata = {
155#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 155#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
156 { 156 {
157 .modalias = "spi_mmc", 157 .modalias = "mmc_spi",
158 .max_speed_hz = 2, 158 .max_speed_hz = 2,
159 .bus_num = 1, 159 .bus_num = 1,
160 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 160 .chip_select = 5,
161 .platform_data = NULL, 161 .controller_data = &mmc_spi_chip_info,
162 .controller_data = &spi_mmc_chip_info,
163 }, 162 },
164#endif 163#endif
165}; 164};
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 0d3a03429fb9..1cf893e2e55b 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf533/anomaly.h 2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -160,7 +160,7 @@
160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) 160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 163/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ 165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
@@ -278,9 +278,12 @@
278#define ANOMALY_05000266 (0) 278#define ANOMALY_05000266 (0)
279#define ANOMALY_05000323 (0) 279#define ANOMALY_05000323 (0)
280#define ANOMALY_05000353 (1) 280#define ANOMALY_05000353 (1)
281#define ANOMALY_05000380 (0)
281#define ANOMALY_05000386 (1) 282#define ANOMALY_05000386 (1)
282#define ANOMALY_05000412 (0) 283#define ANOMALY_05000412 (0)
283#define ANOMALY_05000432 (0) 284#define ANOMALY_05000432 (0)
284#define ANOMALY_05000435 (0) 285#define ANOMALY_05000435 (0)
286#define ANOMALY_05000447 (0)
287#define ANOMALY_05000448 (0)
285 288
286#endif 289#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index f3d9e495230c..5f517f53b0fd 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
134 CH_UART_TX, 134 CH_UART_TX,
135 CH_UART_RX, 135 CH_UART_RX,
136#endif 136#endif
137#ifdef CONFIG_BFIN_UART0_CTSRTS 137#ifdef CONFIG_SERIAL_BFIN_CTSRTS
138 CONFIG_UART0_CTS_PIN, 138 CONFIG_UART0_CTS_PIN,
139 CONFIG_UART0_RTS_PIN, 139 CONFIG_UART0_RTS_PIN,
140#endif 140#endif
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 42a57b0acb29..77c59da87e85 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -33,9 +33,4 @@ config CAMSIG_MINOTAUR
33 help 33 help
34 Board supply package for CSP Minotaur 34 Board supply package for CSP Minotaur
35 35
36config GENERIC_BF537_BOARD
37 bool "Generic"
38 help
39 Generic or Custom board support.
40
41endchoice 36endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7168cc14afd8..68b98a7af6a6 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf537/boards/Makefile 2# arch/blackfin/mach-bf537/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF537_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN537_STAMP) += stamp.o 5obj-$(CONFIG_BFIN537_STAMP) += stamp.o
7obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o 6obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o
8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o 7obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index 9cd8fb2a30d3..41c75b9bfac0 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
108}; 108};
109#endif 109#endif
110 110
111#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 111#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
112static struct bfin5xx_spi_chip spi_mmc_chip_info = { 112static struct bfin5xx_spi_chip mmc_spi_chip_info = {
113 .enable_dma = 1, 113 .enable_dma = 0,
114 .bits_per_word = 8, 114 .bits_per_word = 8,
115}; 115};
116#endif 116#endif
@@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
160 }, 160 },
161#endif 161#endif
162 162
163#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 163#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
164 {
165 .modalias = "spi_mmc_dummy",
166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
167 .bus_num = 0,
168 .chip_select = 7,
169 .platform_data = NULL,
170 .controller_data = &spi_mmc_chip_info,
171 .mode = SPI_MODE_3,
172 },
173 { 164 {
174 .modalias = "spi_mmc", 165 .modalias = "mmc_spi",
175 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 166 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
176 .bus_num = 0, 167 .bus_num = 0,
177 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 168 .chip_select = 1,
178 .platform_data = NULL, 169 .controller_data = &mmc_spi_chip_info,
179 .controller_data = &spi_mmc_chip_info,
180 .mode = SPI_MODE_3, 170 .mode = SPI_MODE_3,
181 }, 171 },
182#endif 172#endif
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
deleted file mode 100644
index da710fdc4569..000000000000
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ /dev/null
@@ -1,745 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf537/boards/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2008 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/etherdevice.h>
33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
35#include <linux/mtd/partitions.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
39#include <linux/usb/isp1362.h>
40#endif
41#include <linux/irq.h>
42#include <linux/interrupt.h>
43#include <linux/usb/sl811.h>
44#include <asm/dma.h>
45#include <asm/bfin5xx_spi.h>
46#include <asm/reboot.h>
47#include <asm/portmux.h>
48#include <linux/spi/ad7877.h>
49
50/*
51 * Name the Board for the /proc/cpuinfo
52 */
53const char bfin_board_name[] = "UNKNOWN BOARD";
54
55/*
56 * Driver needs to know address, irq and flag pin.
57 */
58
59#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
60#include <linux/usb/isp1760.h>
61static struct resource bfin_isp1760_resources[] = {
62 [0] = {
63 .start = 0x203C0000,
64 .end = 0x203C0000 + 0x000fffff,
65 .flags = IORESOURCE_MEM,
66 },
67 [1] = {
68 .start = IRQ_PF7,
69 .end = IRQ_PF7,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct isp1760_platform_data isp1760_priv = {
75 .is_isp1761 = 0,
76 .port1_disable = 0,
77 .bus_width_16 = 1,
78 .port1_otg = 0,
79 .analog_oc = 0,
80 .dack_polarity_high = 0,
81 .dreq_polarity_high = 0,
82};
83
84static struct platform_device bfin_isp1760_device = {
85 .name = "isp1760-hcd",
86 .id = 0,
87 .dev = {
88 .platform_data = &isp1760_priv,
89 },
90 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
91 .resource = bfin_isp1760_resources,
92};
93#endif
94
95#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
96static struct resource bfin_pcmcia_cf_resources[] = {
97 {
98 .start = 0x20310000, /* IO PORT */
99 .end = 0x20312000,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = 0x20311000, /* Attribute Memory */
103 .end = 0x20311FFF,
104 .flags = IORESOURCE_MEM,
105 }, {
106 .start = IRQ_PF4,
107 .end = IRQ_PF4,
108 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
109 }, {
110 .start = 6, /* Card Detect PF6 */
111 .end = 6,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116static struct platform_device bfin_pcmcia_cf_device = {
117 .name = "bfin_cf_pcmcia",
118 .id = -1,
119 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
120 .resource = bfin_pcmcia_cf_resources,
121};
122#endif
123
124#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
125static struct platform_device rtc_device = {
126 .name = "rtc-bfin",
127 .id = -1,
128};
129#endif
130
131#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
132static struct resource smc91x_resources[] = {
133 {
134 .name = "smc91x-regs",
135 .start = 0x20300300,
136 .end = 0x20300300 + 16,
137 .flags = IORESOURCE_MEM,
138 }, {
139
140 .start = IRQ_PF7,
141 .end = IRQ_PF7,
142 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
143 },
144};
145static struct platform_device smc91x_device = {
146 .name = "smc91x",
147 .id = 0,
148 .num_resources = ARRAY_SIZE(smc91x_resources),
149 .resource = smc91x_resources,
150};
151#endif
152
153#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
154static struct resource dm9000_resources[] = {
155 [0] = {
156 .start = 0x203FB800,
157 .end = 0x203FB800 + 1,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = 0x203FB800 + 4,
162 .end = 0x203FB800 + 5,
163 .flags = IORESOURCE_MEM,
164 },
165 [2] = {
166 .start = IRQ_PF9,
167 .end = IRQ_PF9,
168 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
169 },
170};
171
172static struct platform_device dm9000_device = {
173 .name = "dm9000",
174 .id = -1,
175 .num_resources = ARRAY_SIZE(dm9000_resources),
176 .resource = dm9000_resources,
177};
178#endif
179
180#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
181static struct resource sl811_hcd_resources[] = {
182 {
183 .start = 0x20340000,
184 .end = 0x20340000,
185 .flags = IORESOURCE_MEM,
186 }, {
187 .start = 0x20340004,
188 .end = 0x20340004,
189 .flags = IORESOURCE_MEM,
190 }, {
191 .start = CONFIG_USB_SL811_BFIN_IRQ,
192 .end = CONFIG_USB_SL811_BFIN_IRQ,
193 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
194 },
195};
196
197#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
198void sl811_port_power(struct device *dev, int is_on)
199{
200 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
201 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
202
203}
204#endif
205
206static struct sl811_platform_data sl811_priv = {
207 .potpg = 10,
208 .power = 250, /* == 500mA */
209#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
210 .port_power = &sl811_port_power,
211#endif
212};
213
214static struct platform_device sl811_hcd_device = {
215 .name = "sl811-hcd",
216 .id = 0,
217 .dev = {
218 .platform_data = &sl811_priv,
219 },
220 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
221 .resource = sl811_hcd_resources,
222};
223#endif
224
225#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
226static struct resource isp1362_hcd_resources[] = {
227 {
228 .start = 0x20360000,
229 .end = 0x20360000,
230 .flags = IORESOURCE_MEM,
231 }, {
232 .start = 0x20360004,
233 .end = 0x20360004,
234 .flags = IORESOURCE_MEM,
235 }, {
236 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
237 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
238 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
239 },
240};
241
242static struct isp1362_platform_data isp1362_priv = {
243 .sel15Kres = 1,
244 .clknotstop = 0,
245 .oc_enable = 0,
246 .int_act_high = 0,
247 .int_edge_triggered = 0,
248 .remote_wakeup_connected = 0,
249 .no_power_switching = 1,
250 .power_switching_mode = 0,
251};
252
253static struct platform_device isp1362_hcd_device = {
254 .name = "isp1362-hcd",
255 .id = 0,
256 .dev = {
257 .platform_data = &isp1362_priv,
258 },
259 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
260 .resource = isp1362_hcd_resources,
261};
262#endif
263
264#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
265static struct platform_device bfin_mii_bus = {
266 .name = "bfin_mii_bus",
267};
268
269static struct platform_device bfin_mac_device = {
270 .name = "bfin_mac",
271 .dev.platform_data = &bfin_mii_bus,
272};
273#endif
274
275#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
276static struct resource net2272_bfin_resources[] = {
277 {
278 .start = 0x20300000,
279 .end = 0x20300000 + 0x100,
280 .flags = IORESOURCE_MEM,
281 }, {
282 .start = IRQ_PF7,
283 .end = IRQ_PF7,
284 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
285 },
286};
287
288static struct platform_device net2272_bfin_device = {
289 .name = "net2272",
290 .id = -1,
291 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
292 .resource = net2272_bfin_resources,
293};
294#endif
295
296#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
297/* all SPI peripherals info goes here */
298
299#if defined(CONFIG_MTD_M25P80) \
300 || defined(CONFIG_MTD_M25P80_MODULE)
301static struct mtd_partition bfin_spi_flash_partitions[] = {
302 {
303 .name = "bootloader(spi)",
304 .size = 0x00020000,
305 .offset = 0,
306 .mask_flags = MTD_CAP_ROM
307 }, {
308 .name = "linux kernel(spi)",
309 .size = 0xe0000,
310 .offset = 0x20000
311 }, {
312 .name = "file system(spi)",
313 .size = 0x700000,
314 .offset = 0x00100000,
315 }
316};
317
318static struct flash_platform_data bfin_spi_flash_data = {
319 .name = "m25p80",
320 .parts = bfin_spi_flash_partitions,
321 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
322 .type = "m25p64",
323};
324
325/* SPI flash chip (m25p64) */
326static struct bfin5xx_spi_chip spi_flash_chip_info = {
327 .enable_dma = 0, /* use dma transfer with this chip*/
328 .bits_per_word = 8,
329};
330#endif
331
332#if defined(CONFIG_SPI_ADC_BF533) \
333 || defined(CONFIG_SPI_ADC_BF533_MODULE)
334/* SPI ADC chip */
335static struct bfin5xx_spi_chip spi_adc_chip_info = {
336 .enable_dma = 1, /* use dma transfer with this chip*/
337 .bits_per_word = 16,
338};
339#endif
340
341#if defined(CONFIG_SND_BLACKFIN_AD1836) \
342 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
343static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
344 .enable_dma = 0,
345 .bits_per_word = 16,
346};
347#endif
348
349#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
350static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
351 .enable_dma = 0,
352 .bits_per_word = 16,
353};
354#endif
355
356#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
357static struct bfin5xx_spi_chip spi_mmc_chip_info = {
358 .enable_dma = 1,
359 .bits_per_word = 8,
360};
361#endif
362
363#if defined(CONFIG_PBX)
364static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
365 .ctl_reg = 0x4, /* send zero */
366 .enable_dma = 0,
367 .bits_per_word = 8,
368 .cs_change_per_word = 1,
369};
370#endif
371
372#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
373static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
374 .enable_dma = 0,
375 .bits_per_word = 16,
376};
377
378static const struct ad7877_platform_data bfin_ad7877_ts_info = {
379 .model = 7877,
380 .vref_delay_usecs = 50, /* internal, no capacitor */
381 .x_plate_ohms = 419,
382 .y_plate_ohms = 486,
383 .pressure_max = 1000,
384 .pressure_min = 0,
385 .stopacq_polarity = 1,
386 .first_conversion_delay = 3,
387 .acquisition_time = 1,
388 .averaging = 1,
389 .pen_down_acc_interval = 1,
390};
391#endif
392
393static struct spi_board_info bfin_spi_board_info[] __initdata = {
394#if defined(CONFIG_MTD_M25P80) \
395 || defined(CONFIG_MTD_M25P80_MODULE)
396 {
397 /* the modalias must be the same as spi device driver name */
398 .modalias = "m25p80", /* Name of spi_driver for this device */
399 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
400 .bus_num = 0, /* Framework bus number */
401 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
402 .platform_data = &bfin_spi_flash_data,
403 .controller_data = &spi_flash_chip_info,
404 .mode = SPI_MODE_3,
405 },
406#endif
407
408#if defined(CONFIG_SPI_ADC_BF533) \
409 || defined(CONFIG_SPI_ADC_BF533_MODULE)
410 {
411 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
412 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
413 .bus_num = 0, /* Framework bus number */
414 .chip_select = 1, /* Framework chip select. */
415 .platform_data = NULL, /* No spi_driver specific config */
416 .controller_data = &spi_adc_chip_info,
417 },
418#endif
419
420#if defined(CONFIG_SND_BLACKFIN_AD1836) \
421 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
422 {
423 .modalias = "ad1836-spi",
424 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
425 .bus_num = 0,
426 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
427 .controller_data = &ad1836_spi_chip_info,
428 },
429#endif
430#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
431 {
432 .modalias = "ad9960-spi",
433 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
434 .bus_num = 0,
435 .chip_select = 1,
436 .controller_data = &ad9960_spi_chip_info,
437 },
438#endif
439#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
440 {
441 .modalias = "spi_mmc_dummy",
442 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
443 .bus_num = 0,
444 .chip_select = 0,
445 .platform_data = NULL,
446 .controller_data = &spi_mmc_chip_info,
447 .mode = SPI_MODE_3,
448 },
449 {
450 .modalias = "spi_mmc",
451 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
452 .bus_num = 0,
453 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
454 .platform_data = NULL,
455 .controller_data = &spi_mmc_chip_info,
456 .mode = SPI_MODE_3,
457 },
458#endif
459#if defined(CONFIG_PBX)
460 {
461 .modalias = "fxs-spi",
462 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
463 .bus_num = 0,
464 .chip_select = 8 - CONFIG_J11_JUMPER,
465 .controller_data = &spi_si3xxx_chip_info,
466 .mode = SPI_MODE_3,
467 },
468 {
469 .modalias = "fxo-spi",
470 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
471 .bus_num = 0,
472 .chip_select = 8 - CONFIG_J19_JUMPER,
473 .controller_data = &spi_si3xxx_chip_info,
474 .mode = SPI_MODE_3,
475 },
476#endif
477#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
478 {
479 .modalias = "ad7877",
480 .platform_data = &bfin_ad7877_ts_info,
481 .irq = IRQ_PF6,
482 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
483 .bus_num = 0,
484 .chip_select = 1,
485 .controller_data = &spi_ad7877_chip_info,
486 },
487#endif
488};
489
490/* SPI controller data */
491static struct bfin5xx_spi_master bfin_spi0_info = {
492 .num_chipselect = 8,
493 .enable_dma = 1, /* master has the ability to do dma transfer */
494 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
495};
496
497/* SPI (0) */
498static struct resource bfin_spi0_resource[] = {
499 [0] = {
500 .start = SPI0_REGBASE,
501 .end = SPI0_REGBASE + 0xFF,
502 .flags = IORESOURCE_MEM,
503 },
504 [1] = {
505 .start = CH_SPI,
506 .end = CH_SPI,
507 .flags = IORESOURCE_IRQ,
508 },
509};
510
511static struct platform_device bfin_spi0_device = {
512 .name = "bfin-spi",
513 .id = 0, /* Bus number */
514 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
515 .resource = bfin_spi0_resource,
516 .dev = {
517 .platform_data = &bfin_spi0_info, /* Passed to driver */
518 },
519};
520#endif /* spi master and devices */
521
522#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
523static struct platform_device bfin_fb_device = {
524 .name = "bf537-lq035",
525};
526#endif
527
528#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
529static struct platform_device bfin_fb_adv7393_device = {
530 .name = "bfin-adv7393",
531};
532#endif
533
534#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
535static struct resource bfin_uart_resources[] = {
536 {
537 .start = 0xFFC00400,
538 .end = 0xFFC004FF,
539 .flags = IORESOURCE_MEM,
540 }, {
541 .start = 0xFFC02000,
542 .end = 0xFFC020FF,
543 .flags = IORESOURCE_MEM,
544 },
545};
546
547static struct platform_device bfin_uart_device = {
548 .name = "bfin-uart",
549 .id = 1,
550 .num_resources = ARRAY_SIZE(bfin_uart_resources),
551 .resource = bfin_uart_resources,
552};
553#endif
554
555#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
556#ifdef CONFIG_BFIN_SIR0
557static struct resource bfin_sir0_resources[] = {
558 {
559 .start = 0xFFC00400,
560 .end = 0xFFC004FF,
561 .flags = IORESOURCE_MEM,
562 },
563 {
564 .start = IRQ_UART0_RX,
565 .end = IRQ_UART0_RX+1,
566 .flags = IORESOURCE_IRQ,
567 },
568 {
569 .start = CH_UART0_RX,
570 .end = CH_UART0_RX+1,
571 .flags = IORESOURCE_DMA,
572 },
573};
574
575static struct platform_device bfin_sir0_device = {
576 .name = "bfin_sir",
577 .id = 0,
578 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
579 .resource = bfin_sir0_resources,
580};
581#endif
582#ifdef CONFIG_BFIN_SIR1
583static struct resource bfin_sir1_resources[] = {
584 {
585 .start = 0xFFC02000,
586 .end = 0xFFC020FF,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .start = IRQ_UART1_RX,
591 .end = IRQ_UART1_RX+1,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = CH_UART1_RX,
596 .end = CH_UART1_RX+1,
597 .flags = IORESOURCE_DMA,
598 },
599};
600
601static struct platform_device bfin_sir1_device = {
602 .name = "bfin_sir",
603 .id = 1,
604 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
605 .resource = bfin_sir1_resources,
606};
607#endif
608#endif
609
610#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
611static struct resource bfin_twi0_resource[] = {
612 [0] = {
613 .start = TWI0_REGBASE,
614 .end = TWI0_REGBASE + 0xFF,
615 .flags = IORESOURCE_MEM,
616 },
617 [1] = {
618 .start = IRQ_TWI,
619 .end = IRQ_TWI,
620 .flags = IORESOURCE_IRQ,
621 },
622};
623
624static struct platform_device i2c_bfin_twi_device = {
625 .name = "i2c-bfin-twi",
626 .id = 0,
627 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
628 .resource = bfin_twi0_resource,
629};
630#endif
631
632#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
633static struct platform_device bfin_sport0_uart_device = {
634 .name = "bfin-sport-uart",
635 .id = 0,
636};
637
638static struct platform_device bfin_sport1_uart_device = {
639 .name = "bfin-sport-uart",
640 .id = 1,
641};
642#endif
643
644static struct platform_device *stamp_devices[] __initdata = {
645#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
646 &bfin_pcmcia_cf_device,
647#endif
648
649#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
650 &rtc_device,
651#endif
652
653#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
654 &sl811_hcd_device,
655#endif
656
657#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
658 &isp1362_hcd_device,
659#endif
660
661#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
662 &smc91x_device,
663#endif
664
665#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
666 &dm9000_device,
667#endif
668
669#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
670 &bfin_mii_bus,
671 &bfin_mac_device,
672#endif
673
674#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
675 &net2272_bfin_device,
676#endif
677
678#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
679 &bfin_isp1760_device,
680#endif
681
682#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
683 &bfin_spi0_device,
684#endif
685
686#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
687 &bfin_fb_device,
688#endif
689
690#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
691 &bfin_fb_adv7393_device,
692#endif
693
694#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
695 &bfin_uart_device,
696#endif
697
698#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
699#ifdef CONFIG_BFIN_SIR0
700 &bfin_sir0_device,
701#endif
702#ifdef CONFIG_BFIN_SIR1
703 &bfin_sir1_device,
704#endif
705#endif
706
707#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
708 &i2c_bfin_twi_device,
709#endif
710
711#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
712 &bfin_sport0_uart_device,
713 &bfin_sport1_uart_device,
714#endif
715};
716
717static int __init generic_init(void)
718{
719 printk(KERN_INFO "%s(): registering device resources\n", __func__);
720 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
721#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
722 spi_register_board_info(bfin_spi_board_info,
723 ARRAY_SIZE(bfin_spi_board_info));
724#endif
725
726 return 0;
727}
728
729arch_initcall(generic_init);
730
731void native_machine_restart(char *cmd)
732{
733 /* workaround reboot hang when booting from SPI */
734 if ((bfin_read_SYSCR() & 0x7) == 0x3)
735 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
736}
737
738#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
739void bfin_get_ether_addr(char *addr)
740{
741 random_ether_addr(addr);
742 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
743}
744EXPORT_SYMBOL(bfin_get_ether_addr);
745#endif
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index db7d3a385e4b..3c159819e555 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -134,9 +134,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
134}; 134};
135#endif 135#endif
136 136
137#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 137#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
138static struct bfin5xx_spi_chip spi_mmc_chip_info = { 138static struct bfin5xx_spi_chip mmc_spi_chip_info = {
139 .enable_dma = 1, 139 .enable_dma = 0,
140 .bits_per_word = 8, 140 .bits_per_word = 8,
141}; 141};
142#endif 142#endif
@@ -156,23 +156,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
156 }, 156 },
157#endif 157#endif
158 158
159#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 159#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
160 { 160 {
161 .modalias = "spi_mmc_dummy", 161 .modalias = "mmc_spi",
162 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 162 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
163 .bus_num = 0, 163 .bus_num = 0,
164 .chip_select = 0, 164 .chip_select = 5,
165 .platform_data = NULL, 165 .controller_data = &mmc_spi_chip_info,
166 .controller_data = &spi_mmc_chip_info,
167 .mode = SPI_MODE_3,
168 },
169 {
170 .modalias = "spi_mmc",
171 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
172 .bus_num = 0,
173 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
174 .platform_data = NULL,
175 .controller_data = &spi_mmc_chip_info,
176 .mode = SPI_MODE_3, 166 .mode = SPI_MODE_3,
177 }, 167 },
178#endif 168#endif
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 590eb3a139b7..4e1de1e53f89 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -289,9 +289,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
289}; 289};
290#endif 290#endif
291 291
292#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 292#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
293static struct bfin5xx_spi_chip spi_mmc_chip_info = { 293static struct bfin5xx_spi_chip mmc_spi_chip_info = {
294 .enable_dma = 1, 294 .enable_dma = 0,
295 .bits_per_word = 8, 295 .bits_per_word = 8,
296}; 296};
297#endif 297#endif
@@ -364,23 +364,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
364 .controller_data = &ad9960_spi_chip_info, 364 .controller_data = &ad9960_spi_chip_info,
365 }, 365 },
366#endif 366#endif
367#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 367#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
368 {
369 .modalias = "spi_mmc_dummy",
370 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
371 .bus_num = 0,
372 .chip_select = 7,
373 .platform_data = NULL,
374 .controller_data = &spi_mmc_chip_info,
375 .mode = SPI_MODE_3,
376 },
377 { 368 {
378 .modalias = "spi_mmc", 369 .modalias = "mmc_spi",
379 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 370 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
380 .bus_num = 0, 371 .bus_num = 0,
381 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 372 .chip_select = 5,
382 .platform_data = NULL, 373 .controller_data = &mmc_spi_chip_info,
383 .controller_data = &spi_mmc_chip_info,
384 .mode = SPI_MODE_3, 374 .mode = SPI_MODE_3,
385 }, 375 },
386#endif 376#endif
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 3f4f203a06ec..53ad10f3cd76 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
108}; 108};
109#endif 109#endif
110 110
111#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 111#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
112static struct bfin5xx_spi_chip spi_mmc_chip_info = { 112static struct bfin5xx_spi_chip mmc_spi_chip_info = {
113 .enable_dma = 1, 113 .enable_dma = 0,
114 .bits_per_word = 8, 114 .bits_per_word = 8,
115}; 115};
116#endif 116#endif
@@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
160 }, 160 },
161#endif 161#endif
162 162
163#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 163#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
164 {
165 .modalias = "spi_mmc_dummy",
166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
167 .bus_num = 0,
168 .chip_select = 7,
169 .platform_data = NULL,
170 .controller_data = &spi_mmc_chip_info,
171 .mode = SPI_MODE_3,
172 },
173 { 164 {
174 .modalias = "spi_mmc", 165 .modalias = "mmc_spi",
175 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
176 .bus_num = 0, 167 .bus_num = 0,
177 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 168 .chip_select = 5,
178 .platform_data = NULL, 169 .controller_data = &mmc_spi_chip_info,
179 .controller_data = &spi_mmc_chip_info,
180 .mode = SPI_MODE_3, 170 .mode = SPI_MODE_3,
181 }, 171 },
182#endif 172#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 9cb39121d1cb..1bfd80c26c90 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf537/anomaly.h 2 * File: include/asm-blackfin/mach-bf537/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -110,7 +110,7 @@
110#define ANOMALY_05000301 (1) 110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) 112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 113/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) 114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) 116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
@@ -168,9 +168,12 @@
168#define ANOMALY_05000323 (0) 168#define ANOMALY_05000323 (0)
169#define ANOMALY_05000353 (1) 169#define ANOMALY_05000353 (1)
170#define ANOMALY_05000363 (0) 170#define ANOMALY_05000363 (0)
171#define ANOMALY_05000380 (0)
171#define ANOMALY_05000386 (1) 172#define ANOMALY_05000386 (1)
172#define ANOMALY_05000412 (0) 173#define ANOMALY_05000412 (0)
173#define ANOMALY_05000432 (0) 174#define ANOMALY_05000432 (0)
174#define ANOMALY_05000435 (0) 175#define ANOMALY_05000435 (0)
176#define ANOMALY_05000447 (0)
177#define ANOMALY_05000448 (0)
175 178
176#endif 179#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index b3f87e1d16a2..9e34700844a2 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index e130b4f8a05d..3a5699827363 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf538/anomaly.h 2 * File: include/asm-blackfin/mach-bf538/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -120,13 +120,17 @@
120#define ANOMALY_05000198 (0) 120#define ANOMALY_05000198 (0)
121#define ANOMALY_05000230 (0) 121#define ANOMALY_05000230 (0)
122#define ANOMALY_05000263 (0) 122#define ANOMALY_05000263 (0)
123#define ANOMALY_05000305 (0)
123#define ANOMALY_05000311 (0) 124#define ANOMALY_05000311 (0)
124#define ANOMALY_05000323 (0) 125#define ANOMALY_05000323 (0)
125#define ANOMALY_05000353 (1) 126#define ANOMALY_05000353 (1)
126#define ANOMALY_05000363 (0) 127#define ANOMALY_05000363 (0)
128#define ANOMALY_05000380 (0)
127#define ANOMALY_05000386 (1) 129#define ANOMALY_05000386 (1)
128#define ANOMALY_05000412 (0) 130#define ANOMALY_05000412 (0)
129#define ANOMALY_05000432 (0) 131#define ANOMALY_05000432 (0)
130#define ANOMALY_05000435 (0) 132#define ANOMALY_05000435 (0)
133#define ANOMALY_05000447 (0)
134#define ANOMALY_05000448 (0)
131 135
132#endif 136#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 40503b6b89a3..3c2811ebecdd 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 23d03c52f4b4..882e40ccf0d1 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf548/anomaly.h 2 * File: include/asm-blackfin/mach-bf548/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 10 * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -91,8 +91,6 @@
91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) 91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ 92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) 93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
94/* Mobile DDR Operation Not Functional */
95#define ANOMALY_05000377 (1)
96/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ 94/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
97#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) 95#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
98/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ 96/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
@@ -157,8 +155,22 @@
157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) 155#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
158/* Software System Reset Corrupts PLL_LOCKCNT Register */ 156/* Software System Reset Corrupts PLL_LOCKCNT Register */
159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) 157#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
158/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
159#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
160/* OTP Write Accesses Not Supported */
161#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
160/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 162/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
161#define ANOMALY_05000443 (1) 163#define ANOMALY_05000443 (1)
164/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
165#define ANOMALY_05000446 (1)
166/* UART IrDA Receiver Fails on Extended Bit Pulses */
167#define ANOMALY_05000447 (1)
168/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
169#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
170/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
171#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
172/* USB DMA Mode 1 Short Packet Data Corruption */
173#define ANOMALY_05000450 (1
162 174
163/* Anomalies that don't exist on this proc */ 175/* Anomalies that don't exist on this proc */
164#define ANOMALY_05000125 (0) 176#define ANOMALY_05000125 (0)
@@ -171,6 +183,8 @@
171#define ANOMALY_05000263 (0) 183#define ANOMALY_05000263 (0)
172#define ANOMALY_05000266 (0) 184#define ANOMALY_05000266 (0)
173#define ANOMALY_05000273 (0) 185#define ANOMALY_05000273 (0)
186#define ANOMALY_05000278 (0)
187#define ANOMALY_05000305 (0)
174#define ANOMALY_05000307 (0) 188#define ANOMALY_05000307 (0)
175#define ANOMALY_05000311 (0) 189#define ANOMALY_05000311 (0)
176#define ANOMALY_05000323 (0) 190#define ANOMALY_05000323 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index e4cf35e7ab9f..c05e79cba257 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -63,7 +63,7 @@
63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) 63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) 64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
65 65
66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART2_CTSRTS)
67# define CONFIG_SERIAL_BFIN_CTSRTS 67# define CONFIG_SERIAL_BFIN_CTSRTS
68 68
69# ifndef CONFIG_UART0_CTS_PIN 69# ifndef CONFIG_UART0_CTS_PIN
@@ -74,12 +74,12 @@
74# define CONFIG_UART0_RTS_PIN -1 74# define CONFIG_UART0_RTS_PIN -1
75# endif 75# endif
76 76
77# ifndef CONFIG_UART1_CTS_PIN 77# ifndef CONFIG_UART2_CTS_PIN
78# define CONFIG_UART1_CTS_PIN -1 78# define CONFIG_UART2_CTS_PIN -1
79# endif 79# endif
80 80
81# ifndef CONFIG_UART1_RTS_PIN 81# ifndef CONFIG_UART2_RTS_PIN
82# define CONFIG_UART1_RTS_PIN -1 82# define CONFIG_UART2_RTS_PIN -1
83# endif 83# endif
84#endif 84#endif
85 85
@@ -130,7 +130,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
130 CH_UART0_TX, 130 CH_UART0_TX,
131 CH_UART0_RX, 131 CH_UART0_RX,
132#endif 132#endif
133#ifdef CONFIG_BFIN_UART0_CTSRTS 133#ifdef CONFIG_SERIAL_BFIN_CTSRTS
134 CONFIG_UART0_CTS_PIN, 134 CONFIG_UART0_CTS_PIN,
135 CONFIG_UART0_RTS_PIN, 135 CONFIG_UART0_RTS_PIN,
136#endif 136#endif
@@ -144,6 +144,10 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART1_TX, 144 CH_UART1_TX,
145 CH_UART1_RX, 145 CH_UART1_RX,
146#endif 146#endif
147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 0,
149 0,
150#endif
147 }, 151 },
148#endif 152#endif
149#ifdef CONFIG_SERIAL_BFIN_UART2 153#ifdef CONFIG_SERIAL_BFIN_UART2
@@ -154,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
154 CH_UART2_TX, 158 CH_UART2_TX,
155 CH_UART2_RX, 159 CH_UART2_RX,
156#endif 160#endif
157#ifdef CONFIG_BFIN_UART2_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
158 CONFIG_UART2_CTS_PIN, 162 CONFIG_UART2_CTS_PIN,
159 CONFIG_UART2_RTS_PIN, 163 CONFIG_UART2_RTS_PIN,
160#endif 164#endif
@@ -168,6 +172,10 @@ struct bfin_serial_res bfin_serial_resource[] = {
168 CH_UART3_TX, 172 CH_UART3_TX,
169 CH_UART3_RX, 173 CH_UART3_RX,
170#endif 174#endif
175#ifdef CONFIG_SERIAL_BFIN_CTSRTS
176 0,
177 0,
178#endif
171 }, 179 },
172#endif 180#endif
173}; 181};
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 60299a71e090..f194625f6821 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -123,8 +123,8 @@ Events (highest priority) EMU 0
123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ 123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ 124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ 125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
126#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ 126#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
127#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ 127#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ 128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ 129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ 130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
@@ -361,8 +361,8 @@ Events (highest priority) EMU 0
361#define IRQ_UART2_ERR IRQ_UART2_ERROR 361#define IRQ_UART2_ERR IRQ_UART2_ERROR
362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR 362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR 363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
364#define IRQ_EPP1_ERR IRQ_EPP1_ERROR 364#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
365#define IRQ_EPP2_ERR IRQ_EPP2_ERROR 365#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
366#define IRQ_UART3_ERR IRQ_UART3_ERROR 366#define IRQ_UART3_ERR IRQ_UART3_ERROR
367#define IRQ_HOST_ERR IRQ_HOST_ERROR 367#define IRQ_HOST_ERR IRQ_HOST_ERROR
368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR 368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig
index e41a67b1fb53..e4bc6d7c5a6a 100644
--- a/arch/blackfin/mach-bf561/boards/Kconfig
+++ b/arch/blackfin/mach-bf561/boards/Kconfig
@@ -19,9 +19,4 @@ config BFIN561_BLUETECHNIX_CM
19 help 19 help
20 CM-BF561 support for EVAL- and DEV-Board. 20 CM-BF561 support for EVAL- and DEV-Board.
21 21
22config GENERIC_BF561_BOARD
23 bool "Generic"
24 help
25 Generic or Custom board support.
26
27endchoice 22endchoice
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
index 04add010b568..3a152559e957 100644
--- a/arch/blackfin/mach-bf561/boards/Makefile
+++ b/arch/blackfin/mach-bf561/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf561/boards/Makefile 2# arch/blackfin/mach-bf561/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF561_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o 5obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
7obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o 6obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
8obj-$(CONFIG_BFIN561_TEPLA) += tepla.o 7obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 6880d1ebfe60..f623c6b0719f 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -105,9 +105,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
105}; 105};
106#endif 106#endif
107 107
108#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
109static struct bfin5xx_spi_chip spi_mmc_chip_info = { 109static struct bfin5xx_spi_chip mmc_spi_chip_info = {
110 .enable_dma = 1, 110 .enable_dma = 0,
111 .bits_per_word = 8, 111 .bits_per_word = 8,
112}; 112};
113#endif 113#endif
@@ -155,14 +155,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
155 .controller_data = &ad9960_spi_chip_info, 155 .controller_data = &ad9960_spi_chip_info,
156 }, 156 },
157#endif 157#endif
158#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 158#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
159 { 159 {
160 .modalias = "spi_mmc", 160 .modalias = "mmc_spi",
161 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 161 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
162 .bus_num = 0, 162 .bus_num = 0,
163 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 163 .chip_select = 5,
164 .platform_data = NULL, 164 .controller_data = &mmc_spi_chip_info,
165 .controller_data = &spi_mmc_chip_info,
166 .mode = SPI_MODE_3, 165 .mode = SPI_MODE_3,
167 }, 166 },
168#endif 167#endif
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
deleted file mode 100644
index 0ba366a0e696..000000000000
--- a/arch/blackfin/mach-bf561/boards/generic_board.c
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf561/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/irq.h>
34
35const char bfin_board_name[] = "UNKNOWN BOARD";
36
37/*
38 * Driver needs to know address, irq and flag pin.
39 */
40#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
41static struct resource smc91x_resources[] = {
42 {
43 .start = 0x2C010300,
44 .end = 0x2C010300 + 16,
45 .flags = IORESOURCE_MEM,
46 }, {
47 .start = IRQ_PROG_INTB,
48 .end = IRQ_PROG_INTB,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 }, {
51 .start = IRQ_PF9,
52 .end = IRQ_PF9,
53 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
54 },
55};
56
57static struct platform_device smc91x_device = {
58 .name = "smc91x",
59 .id = 0,
60 .num_resources = ARRAY_SIZE(smc91x_resources),
61 .resource = smc91x_resources,
62};
63#endif
64
65#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
66#ifdef CONFIG_BFIN_SIR0
67static struct resource bfin_sir0_resources[] = {
68 {
69 .start = 0xFFC00400,
70 .end = 0xFFC004FF,
71 .flags = IORESOURCE_MEM,
72 },
73 {
74 .start = IRQ_UART0_RX,
75 .end = IRQ_UART0_RX+1,
76 .flags = IORESOURCE_IRQ,
77 },
78 {
79 .start = CH_UART0_RX,
80 .end = CH_UART0_RX+1,
81 .flags = IORESOURCE_DMA,
82 },
83};
84
85static struct platform_device bfin_sir0_device = {
86 .name = "bfin_sir",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
89 .resource = bfin_sir0_resources,
90};
91#endif
92#endif
93
94static struct platform_device *generic_board_devices[] __initdata = {
95#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
96 &smc91x_device,
97#endif
98
99#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
100#ifdef CONFIG_BFIN_SIR0
101 &bfin_sir0_device,
102#endif
103#endif
104};
105
106static int __init generic_board_init(void)
107{
108 printk(KERN_INFO "%s(): registering device resources\n", __func__);
109 return platform_add_devices(generic_board_devices,
110 ARRAY_SIZE(generic_board_devices));
111}
112
113arch_initcall(generic_board_init);
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 1a9e17562821..d0b0b3506440 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf561/anomaly.h 2 * File: include/asm-blackfin/mach-bf561/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -224,7 +224,7 @@
224#define ANOMALY_05000301 (1) 224#define ANOMALY_05000301 (1)
225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
226#define ANOMALY_05000302 (1) 226#define ANOMALY_05000302 (1)
227/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
229/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 229/* SCKELOW Bit Does Not Maintain State Through Hibernate */
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) 230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
@@ -283,8 +283,11 @@
283#define ANOMALY_05000273 (0) 283#define ANOMALY_05000273 (0)
284#define ANOMALY_05000311 (0) 284#define ANOMALY_05000311 (0)
285#define ANOMALY_05000353 (1) 285#define ANOMALY_05000353 (1)
286#define ANOMALY_05000380 (0)
286#define ANOMALY_05000386 (1) 287#define ANOMALY_05000386 (1)
287#define ANOMALY_05000432 (0) 288#define ANOMALY_05000432 (0)
288#define ANOMALY_05000435 (0) 289#define ANOMALY_05000435 (0)
290#define ANOMALY_05000447 (0)
291#define ANOMALY_05000448 (0)
289 292
290#endif 293#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index 043bfcf26c52..ca8c5f645209 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
134 CH_UART_TX, 134 CH_UART_TX,
135 CH_UART_RX, 135 CH_UART_RX,
136#endif 136#endif
137#ifdef CONFIG_BFIN_UART0_CTSRTS 137#ifdef CONFIG_SERIAL_BFIN_CTSRTS
138 CONFIG_UART0_CTS_PIN, 138 CONFIG_UART0_CTS_PIN,
139 CONFIG_UART0_RTS_PIN, 139 CONFIG_UART0_RTS_PIN,
140#endif 140#endif
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index 98133b968f7b..80d39b2f9db2 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -62,3 +62,12 @@
62#if (CONFIG_BOOT_LOAD & 0x3) 62#if (CONFIG_BOOT_LOAD & 0x3)
63# error "The kernel load address must be 4 byte aligned" 63# error "The kernel load address must be 4 byte aligned"
64#endif 64#endif
65
66/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
67#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
68# error "The kernel load address is too high; keep it below 10meg for safety"
69#endif
70
71#if ANOMALY_05000448
72# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
73#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 3c98dacbf289..aa0648c6a9fe 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -66,11 +66,33 @@
66 66
67/* Invalidate all instruction cache lines assocoiated with this memory area */ 67/* Invalidate all instruction cache lines assocoiated with this memory area */
68ENTRY(_blackfin_icache_flush_range) 68ENTRY(_blackfin_icache_flush_range)
69/*
70 * Walkaround to avoid loading wrong instruction after invalidating icache
71 * and following sequence is met.
72 *
73 * 1) One instruction address is cached in the instruction cache.
74 * 2) This instruction in SDRAM is changed.
75 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
76 * 4) This instruction is executed again, but the old one is loaded.
77 */
78 P0 = R0;
79 IFLUSH[P0];
69 do_flush IFLUSH, , nop 80 do_flush IFLUSH, , nop
70ENDPROC(_blackfin_icache_flush_range) 81ENDPROC(_blackfin_icache_flush_range)
71 82
72/* Flush all cache lines assocoiated with this area of memory. */ 83/* Flush all cache lines assocoiated with this area of memory. */
73ENTRY(_blackfin_icache_dcache_flush_range) 84ENTRY(_blackfin_icache_dcache_flush_range)
85/*
86 * Walkaround to avoid loading wrong instruction after invalidating icache
87 * and following sequence is met.
88 *
89 * 1) One instruction address is cached in the instruction cache.
90 * 2) This instruction in SDRAM is changed.
91 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
92 * 4) This instruction is executed again, but the old one is loaded.
93 */
94 P0 = R0;
95 IFLUSH[P0];
74 do_flush FLUSH, IFLUSH 96 do_flush FLUSH, IFLUSH
75ENDPROC(_blackfin_icache_dcache_flush_range) 97ENDPROC(_blackfin_icache_dcache_flush_range)
76 98
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index 9dddb6f8cc85..35393651359b 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -17,7 +17,7 @@
17#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ 17#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
18#define PLL_CTL_VAL \ 18#define PLL_CTL_VAL \
19 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ 19 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
20 (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) 20 (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
21 21
22__attribute__((l1_text)) 22__attribute__((l1_text))
23static void do_sync(void) 23static void do_sync(void)
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 4da50bcd9300..8009a512fb11 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -376,10 +376,22 @@ ENTRY(_do_hibernate)
376#endif 376#endif
377 377
378#ifdef PINT0_ASSIGN 378#ifdef PINT0_ASSIGN
379 PM_SYS_PUSH(PINT0_MASK_SET)
380 PM_SYS_PUSH(PINT1_MASK_SET)
381 PM_SYS_PUSH(PINT2_MASK_SET)
382 PM_SYS_PUSH(PINT3_MASK_SET)
379 PM_SYS_PUSH(PINT0_ASSIGN) 383 PM_SYS_PUSH(PINT0_ASSIGN)
380 PM_SYS_PUSH(PINT1_ASSIGN) 384 PM_SYS_PUSH(PINT1_ASSIGN)
381 PM_SYS_PUSH(PINT2_ASSIGN) 385 PM_SYS_PUSH(PINT2_ASSIGN)
382 PM_SYS_PUSH(PINT3_ASSIGN) 386 PM_SYS_PUSH(PINT3_ASSIGN)
387 PM_SYS_PUSH(PINT0_INVERT_SET)
388 PM_SYS_PUSH(PINT1_INVERT_SET)
389 PM_SYS_PUSH(PINT2_INVERT_SET)
390 PM_SYS_PUSH(PINT3_INVERT_SET)
391 PM_SYS_PUSH(PINT0_EDGE_SET)
392 PM_SYS_PUSH(PINT1_EDGE_SET)
393 PM_SYS_PUSH(PINT2_EDGE_SET)
394 PM_SYS_PUSH(PINT3_EDGE_SET)
383#endif 395#endif
384 396
385 PM_SYS_PUSH(EBIU_AMBCTL0) 397 PM_SYS_PUSH(EBIU_AMBCTL0)
@@ -714,10 +726,22 @@ ENTRY(_do_hibernate)
714 PM_SYS_POP(EBIU_AMBCTL0) 726 PM_SYS_POP(EBIU_AMBCTL0)
715 727
716#ifdef PINT0_ASSIGN 728#ifdef PINT0_ASSIGN
729 PM_SYS_POP(PINT3_EDGE_SET)
730 PM_SYS_POP(PINT2_EDGE_SET)
731 PM_SYS_POP(PINT1_EDGE_SET)
732 PM_SYS_POP(PINT0_EDGE_SET)
733 PM_SYS_POP(PINT3_INVERT_SET)
734 PM_SYS_POP(PINT2_INVERT_SET)
735 PM_SYS_POP(PINT1_INVERT_SET)
736 PM_SYS_POP(PINT0_INVERT_SET)
717 PM_SYS_POP(PINT3_ASSIGN) 737 PM_SYS_POP(PINT3_ASSIGN)
718 PM_SYS_POP(PINT2_ASSIGN) 738 PM_SYS_POP(PINT2_ASSIGN)
719 PM_SYS_POP(PINT1_ASSIGN) 739 PM_SYS_POP(PINT1_ASSIGN)
720 PM_SYS_POP(PINT0_ASSIGN) 740 PM_SYS_POP(PINT0_ASSIGN)
741 PM_SYS_POP(PINT3_MASK_SET)
742 PM_SYS_POP(PINT2_MASK_SET)
743 PM_SYS_POP(PINT1_MASK_SET)
744 PM_SYS_POP(PINT0_MASK_SET)
721#endif 745#endif
722 746
723#ifdef SICA_IWR1 747#ifdef SICA_IWR1
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 88de053bbe8e..21e65a339a22 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -600,6 +600,19 @@ ENTRY(_system_call)
600 p2 = [p2]; 600 p2 = [p2];
601 601
602 [p2+(TASK_THREAD+THREAD_KSP)] = sp; 602 [p2+(TASK_THREAD+THREAD_KSP)] = sp;
603#ifdef CONFIG_IPIPE
604 r0 = sp;
605 SP += -12;
606 call ___ipipe_syscall_root;
607 SP += 12;
608 cc = r0 == 1;
609 if cc jump .Lsyscall_really_exit;
610 cc = r0 == -1;
611 if cc jump .Lresume_userspace;
612 r3 = [sp + PT_R3];
613 r4 = [sp + PT_R4];
614 p0 = [sp + PT_ORIG_P0];
615#endif /* CONFIG_IPIPE */
603 616
604 /* Check the System Call */ 617 /* Check the System Call */
605 r7 = __NR_syscall; 618 r7 = __NR_syscall;
@@ -654,6 +667,17 @@ ENTRY(_system_call)
654 r7 = r7 & r4; 667 r7 = r7 & r4;
655 668
656.Lsyscall_resched: 669.Lsyscall_resched:
670#ifdef CONFIG_IPIPE
671 cc = BITTST(r7, TIF_IRQ_SYNC);
672 if !cc jump .Lsyscall_no_irqsync;
673 [--sp] = reti;
674 r0 = [sp++];
675 SP += -12;
676 call ___ipipe_sync_root;
677 SP += 12;
678 jump .Lresume_userspace_1;
679.Lsyscall_no_irqsync:
680#endif
657 cc = BITTST(r7, TIF_NEED_RESCHED); 681 cc = BITTST(r7, TIF_NEED_RESCHED);
658 if !cc jump .Lsyscall_sigpending; 682 if !cc jump .Lsyscall_sigpending;
659 683
@@ -685,6 +709,10 @@ ENTRY(_system_call)
685.Lsyscall_really_exit: 709.Lsyscall_really_exit:
686 r5 = [sp + PT_RESERVED]; 710 r5 = [sp + PT_RESERVED];
687 rets = r5; 711 rets = r5;
712#ifdef CONFIG_IPIPE
713 [--sp] = reti;
714 r5 = [sp++];
715#endif /* CONFIG_IPIPE */
688 rts; 716 rts;
689ENDPROC(_system_call) 717ENDPROC(_system_call)
690 718
@@ -771,6 +799,15 @@ _new_old_task:
771ENDPROC(_resume) 799ENDPROC(_resume)
772 800
773ENTRY(_ret_from_exception) 801ENTRY(_ret_from_exception)
802#ifdef CONFIG_IPIPE
803 [--sp] = rets;
804 SP += -12;
805 call ___ipipe_check_root
806 SP += 12
807 rets = [sp++];
808 cc = r0 == 0;
809 if cc jump 4f; /* not on behalf of Linux, get out */
810#endif /* CONFIG_IPIPE */
774 p2.l = lo(IPEND); 811 p2.l = lo(IPEND);
775 p2.h = hi(IPEND); 812 p2.h = hi(IPEND);
776 813
@@ -827,6 +864,28 @@ ENTRY(_ret_from_exception)
827 rts; 864 rts;
828ENDPROC(_ret_from_exception) 865ENDPROC(_ret_from_exception)
829 866
867#ifdef CONFIG_IPIPE
868
869_sync_root_irqs:
870 [--sp] = reti; /* Reenable interrupts */
871 r0 = [sp++];
872 jump.l ___ipipe_sync_root
873
874_resume_kernel_from_int:
875 r0.l = _sync_root_irqs
876 r0.h = _sync_root_irqs
877 [--sp] = rets;
878 [--sp] = ( r7:4, p5:3 );
879 SP += -12;
880 call ___ipipe_call_irqtail
881 SP += 12;
882 ( r7:4, p5:3 ) = [sp++];
883 rets = [sp++];
884 rts
885#else
886#define _resume_kernel_from_int 2f
887#endif
888
830ENTRY(_return_from_int) 889ENTRY(_return_from_int)
831 /* If someone else already raised IRQ 15, do nothing. */ 890 /* If someone else already raised IRQ 15, do nothing. */
832 csync; 891 csync;
@@ -848,7 +907,7 @@ ENTRY(_return_from_int)
848 r1 = r0 - r1; 907 r1 = r0 - r1;
849 r2 = r0 & r1; 908 r2 = r0 & r1;
850 cc = r2 == 0; 909 cc = r2 == 0;
851 if !cc jump 2f; 910 if !cc jump _resume_kernel_from_int;
852 911
853 /* Lower the interrupt level to 15. */ 912 /* Lower the interrupt level to 15. */
854 p0.l = lo(EVT15); 913 p0.l = lo(EVT15);
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 43c4eb9acb65..0069c2dd4625 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -235,6 +235,7 @@ ENDPROC(_evt_system_call)
235 235
236#ifdef CONFIG_IPIPE 236#ifdef CONFIG_IPIPE
237ENTRY(___ipipe_call_irqtail) 237ENTRY(___ipipe_call_irqtail)
238 p0 = r0;
238 r0.l = 1f; 239 r0.l = 1f;
239 r0.h = 1f; 240 r0.h = 1f;
240 reti = r0; 241 reti = r0;
@@ -242,9 +243,6 @@ ENTRY(___ipipe_call_irqtail)
2421: 2431:
243 [--sp] = rets; 244 [--sp] = rets;
244 [--sp] = ( r7:4, p5:3 ); 245 [--sp] = ( r7:4, p5:3 );
245 p0.l = ___ipipe_irq_tail_hook;
246 p0.h = ___ipipe_irq_tail_hook;
247 p0 = [p0];
248 sp += -12; 246 sp += -12;
249 call (p0); 247 call (p0);
250 sp += 12; 248 sp += 12;
@@ -259,7 +257,7 @@ ENTRY(___ipipe_call_irqtail)
259 p0.h = hi(EVT14); 257 p0.h = hi(EVT14);
260 [p0] = r0; 258 [p0] = r0;
261 csync; 259 csync;
262 r0 = 0x401f; 260 r0 = 0x401f (z);
263 sti r0; 261 sti r0;
264 raise 14; 262 raise 14;
265 [--sp] = reti; /* IRQs on. */ 263 [--sp] = reti; /* IRQs on. */
@@ -277,11 +275,7 @@ ENTRY(___ipipe_call_irqtail)
277 p0.h = _bfin_irq_flags; 275 p0.h = _bfin_irq_flags;
278 r0 = [p0]; 276 r0 = [p0];
279 sti r0; 277 sti r0;
280#if 0 /* FIXME: this actually raises scheduling latencies */
281 /* Reenable interrupts */
282 [--sp] = reti;
283 r0 = [sp++];
284#endif
285 rts; 278 rts;
286ENDPROC(___ipipe_call_irqtail) 279ENDPROC(___ipipe_call_irqtail)
280
287#endif /* CONFIG_IPIPE */ 281#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 202494568c6c..a7d7b2dd4059 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -161,11 +161,15 @@ static void bfin_core_unmask_irq(unsigned int irq)
161 161
162static void bfin_internal_mask_irq(unsigned int irq) 162static void bfin_internal_mask_irq(unsigned int irq)
163{ 163{
164 unsigned long flags;
165
164#ifdef CONFIG_BF53x 166#ifdef CONFIG_BF53x
167 local_irq_save_hw(flags);
165 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 168 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
166 ~(1 << SIC_SYSIRQ(irq))); 169 ~(1 << SIC_SYSIRQ(irq)));
167#else 170#else
168 unsigned mask_bank, mask_bit; 171 unsigned mask_bank, mask_bit;
172 local_irq_save_hw(flags);
169 mask_bank = SIC_SYSIRQ(irq) / 32; 173 mask_bank = SIC_SYSIRQ(irq) / 32;
170 mask_bit = SIC_SYSIRQ(irq) % 32; 174 mask_bit = SIC_SYSIRQ(irq) % 32;
171 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 175 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
@@ -175,15 +179,20 @@ static void bfin_internal_mask_irq(unsigned int irq)
175 ~(1 << mask_bit)); 179 ~(1 << mask_bit));
176#endif 180#endif
177#endif 181#endif
182 local_irq_restore_hw(flags);
178} 183}
179 184
180static void bfin_internal_unmask_irq(unsigned int irq) 185static void bfin_internal_unmask_irq(unsigned int irq)
181{ 186{
187 unsigned long flags;
188
182#ifdef CONFIG_BF53x 189#ifdef CONFIG_BF53x
190 local_irq_save_hw(flags);
183 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 191 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
184 (1 << SIC_SYSIRQ(irq))); 192 (1 << SIC_SYSIRQ(irq)));
185#else 193#else
186 unsigned mask_bank, mask_bit; 194 unsigned mask_bank, mask_bit;
195 local_irq_save_hw(flags);
187 mask_bank = SIC_SYSIRQ(irq) / 32; 196 mask_bank = SIC_SYSIRQ(irq) / 32;
188 mask_bit = SIC_SYSIRQ(irq) % 32; 197 mask_bit = SIC_SYSIRQ(irq) % 32;
189 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | 198 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
@@ -193,6 +202,7 @@ static void bfin_internal_unmask_irq(unsigned int irq)
193 (1 << mask_bit)); 202 (1 << mask_bit));
194#endif 203#endif
195#endif 204#endif
205 local_irq_restore_hw(flags);
196} 206}
197 207
198#ifdef CONFIG_PM 208#ifdef CONFIG_PM
@@ -390,7 +400,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
390static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) 400static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
391{ 401{
392#ifdef CONFIG_IPIPE 402#ifdef CONFIG_IPIPE
393 _set_irq_handler(irq, handle_edge_irq); 403 _set_irq_handler(irq, handle_level_irq);
394#else 404#else
395 struct irq_desc *desc = irq_desc + irq; 405 struct irq_desc *desc = irq_desc + irq;
396 /* May not call generic set_irq_handler() due to spinlock 406 /* May not call generic set_irq_handler() due to spinlock
@@ -1055,13 +1065,18 @@ int __init init_arch_irq(void)
1055#endif 1065#endif
1056 default: 1066 default:
1057#ifdef CONFIG_IPIPE 1067#ifdef CONFIG_IPIPE
1058 /* 1068 /*
1059 * We want internal interrupt sources to be masked, because 1069 * We want internal interrupt sources to be
1060 * ISRs may trigger interrupts recursively (e.g. DMA), but 1070 * masked, because ISRs may trigger interrupts
1061 * interrupts are _not_ masked at CPU level. So let's handle 1071 * recursively (e.g. DMA), but interrupts are
1062 * them as level interrupts. 1072 * _not_ masked at CPU level. So let's handle
1063 */ 1073 * most of them as level interrupts, except
1064 set_irq_handler(irq, handle_level_irq); 1074 * the timer interrupt which is special.
1075 */
1076 if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR)
1077 set_irq_handler(irq, handle_simple_irq);
1078 else
1079 set_irq_handler(irq, handle_level_irq);
1065#else /* !CONFIG_IPIPE */ 1080#else /* !CONFIG_IPIPE */
1066 set_irq_handler(irq, handle_simple_irq); 1081 set_irq_handler(irq, handle_simple_irq);
1067#endif /* !CONFIG_IPIPE */ 1082#endif /* !CONFIG_IPIPE */
@@ -1123,9 +1138,8 @@ int __init init_arch_irq(void)
1123 1138
1124#ifdef CONFIG_IPIPE 1139#ifdef CONFIG_IPIPE
1125 for (irq = 0; irq < NR_IRQS; irq++) { 1140 for (irq = 0; irq < NR_IRQS; irq++) {
1126 struct irq_desc *desc = irq_desc + irq; 1141 struct irq_desc *desc = irq_to_desc(irq);
1127 desc->ic_prio = __ipipe_get_irq_priority(irq); 1142 desc->ic_prio = __ipipe_get_irq_priority(irq);
1128 desc->thr_prio = __ipipe_get_irqthread_priority(irq);
1129 } 1143 }
1130#endif /* CONFIG_IPIPE */ 1144#endif /* CONFIG_IPIPE */
1131 1145
@@ -1208,76 +1222,21 @@ int __ipipe_get_irq_priority(unsigned irq)
1208 return IVG15; 1222 return IVG15;
1209} 1223}
1210 1224
1211int __ipipe_get_irqthread_priority(unsigned irq)
1212{
1213 int ient, prio;
1214 int demux_irq;
1215
1216 /* The returned priority value is rescaled to [0..IVG13+1]
1217 * with 0 being the lowest effective priority level. */
1218
1219 if (irq <= IRQ_CORETMR)
1220 return IVG13 - irq + 1;
1221
1222 /* GPIO IRQs are given the priority of the demux
1223 * interrupt. */
1224 if (IS_GPIOIRQ(irq)) {
1225#if defined(CONFIG_BF54x)
1226 u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]);
1227 demux_irq = (bank == 0 ? IRQ_PINT0 :
1228 bank == 1 ? IRQ_PINT1 :
1229 bank == 2 ? IRQ_PINT2 :
1230 IRQ_PINT3);
1231#elif defined(CONFIG_BF561)
1232 demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA :
1233 irq >= IRQ_PF16 ? IRQ_PROG1_INTA :
1234 IRQ_PROG0_INTA);
1235#elif defined(CONFIG_BF52x)
1236 demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA :
1237 irq >= IRQ_PG0 ? IRQ_PORTG_INTA :
1238 IRQ_PORTF_INTA);
1239#else
1240 demux_irq = irq;
1241#endif
1242 return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1;
1243 }
1244
1245 /* The GPIO demux interrupt is given a lower priority
1246 * than the GPIO IRQs, so that its threaded handler
1247 * unmasks the interrupt line after the decoded IRQs
1248 * have been processed. */
1249 prio = PRIO_GPIODEMUX(irq);
1250 /* demux irq? */
1251 if (prio != -1)
1252 return IVG13 - prio;
1253
1254 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1255 struct ivgx *ivg = ivg_table + ient;
1256 if (ivg->irqno == irq) {
1257 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1258 if (ivg7_13[prio].ifirst <= ivg &&
1259 ivg7_13[prio].istop > ivg)
1260 return IVG7 - prio;
1261 }
1262 }
1263 }
1264
1265 return 0;
1266}
1267
1268/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ 1225/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1269#ifdef CONFIG_DO_IRQ_L1 1226#ifdef CONFIG_DO_IRQ_L1
1270__attribute__((l1_text)) 1227__attribute__((l1_text))
1271#endif 1228#endif
1272asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) 1229asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1273{ 1230{
1231 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1232 struct ipipe_domain *this_domain = ipipe_current_domain;
1274 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; 1233 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1275 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; 1234 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1276 int irq; 1235 int irq, s;
1277 1236
1278 if (likely(vec == EVT_IVTMR_P)) { 1237 if (likely(vec == EVT_IVTMR_P)) {
1279 irq = IRQ_CORETMR; 1238 irq = IRQ_CORETMR;
1280 goto handle_irq; 1239 goto core_tick;
1281 } 1240 }
1282 1241
1283 SSYNC(); 1242 SSYNC();
@@ -1319,24 +1278,39 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1319 irq = ivg->irqno; 1278 irq = ivg->irqno;
1320 1279
1321 if (irq == IRQ_SYSTMR) { 1280 if (irq == IRQ_SYSTMR) {
1281#ifdef CONFIG_GENERIC_CLOCKEVENTS
1282core_tick:
1283#else
1322 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ 1284 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1285#endif
1323 /* This is basically what we need from the register frame. */ 1286 /* This is basically what we need from the register frame. */
1324 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; 1287 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1325 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; 1288 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1326 if (!ipipe_root_domain_p) 1289 if (this_domain != ipipe_root_domain)
1327 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1328 else
1329 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; 1290 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1291 else
1292 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1330 } 1293 }
1331 1294
1332handle_irq: 1295#ifndef CONFIG_GENERIC_CLOCKEVENTS
1296core_tick:
1297#endif
1298 if (this_domain == ipipe_root_domain) {
1299 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1300 barrier();
1301 }
1333 1302
1334 ipipe_trace_irq_entry(irq); 1303 ipipe_trace_irq_entry(irq);
1335 __ipipe_handle_irq(irq, regs); 1304 __ipipe_handle_irq(irq, regs);
1336 ipipe_trace_irq_exit(irq); 1305 ipipe_trace_irq_exit(irq);
1337 1306
1338 if (ipipe_root_domain_p) 1307 if (this_domain == ipipe_root_domain) {
1339 return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); 1308 set_thread_flag(TIF_IRQ_SYNC);
1309 if (!s) {
1310 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1311 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1312 }
1313 }
1340 1314
1341 return 0; 1315 return 0;
1342} 1316}
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 77c992847094..93eab6146079 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -158,10 +158,14 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance)
158 kfree(msg); 158 kfree(msg);
159 break; 159 break;
160 case BFIN_IPI_CALL_FUNC: 160 case BFIN_IPI_CALL_FUNC:
161 spin_unlock(&msg_queue->lock);
161 ipi_call_function(cpu, msg); 162 ipi_call_function(cpu, msg);
163 spin_lock(&msg_queue->lock);
162 break; 164 break;
163 case BFIN_IPI_CPU_STOP: 165 case BFIN_IPI_CPU_STOP:
166 spin_unlock(&msg_queue->lock);
164 ipi_cpu_stop(cpu); 167 ipi_cpu_stop(cpu);
168 spin_lock(&msg_queue->lock);
165 kfree(msg); 169 kfree(msg);
166 break; 170 break;
167 default: 171 default:
@@ -457,7 +461,7 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end)
457 smp_flush_data.start = start; 461 smp_flush_data.start = start;
458 smp_flush_data.end = end; 462 smp_flush_data.end = end;
459 463
460 if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1)) 464 if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
461 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); 465 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
462} 466}
463EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); 467EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index d0532b72bba5..9c3629b9a689 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -104,7 +104,7 @@ void __init paging_init(void)
104 } 104 }
105} 105}
106 106
107asmlinkage void init_pda(void) 107asmlinkage void __init init_pda(void)
108{ 108{
109 unsigned int cpu = raw_smp_processor_id(); 109 unsigned int cpu = raw_smp_processor_id();
110 110
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 08:33:07 -0400