diff options
Diffstat (limited to 'arch/blackfin/mach-common/pm.c')
| -rw-r--r-- | arch/blackfin/mach-common/pm.c | 64 |
1 files changed, 8 insertions, 56 deletions
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index 9e7e27b7fc8d..0e3d4ff9d8b6 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c | |||
| @@ -38,6 +38,7 @@ | |||
| 38 | #include <linux/io.h> | 38 | #include <linux/io.h> |
| 39 | #include <linux/irq.h> | 39 | #include <linux/irq.h> |
| 40 | 40 | ||
| 41 | #include <asm/cplb.h> | ||
| 41 | #include <asm/gpio.h> | 42 | #include <asm/gpio.h> |
| 42 | #include <asm/dma.h> | 43 | #include <asm/dma.h> |
| 43 | #include <asm/dpmc.h> | 44 | #include <asm/dpmc.h> |
| @@ -170,58 +171,6 @@ static void flushinv_all_dcache(void) | |||
| 170 | } | 171 | } |
| 171 | #endif | 172 | #endif |
| 172 | 173 | ||
| 173 | static inline void dcache_disable(void) | ||
| 174 | { | ||
| 175 | #ifdef CONFIG_BFIN_DCACHE | ||
| 176 | unsigned long ctrl; | ||
| 177 | |||
| 178 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) | ||
| 179 | flushinv_all_dcache(); | ||
| 180 | #endif | ||
| 181 | SSYNC(); | ||
| 182 | ctrl = bfin_read_DMEM_CONTROL(); | ||
| 183 | ctrl &= ~ENDCPLB; | ||
| 184 | bfin_write_DMEM_CONTROL(ctrl); | ||
| 185 | SSYNC(); | ||
| 186 | #endif | ||
| 187 | } | ||
| 188 | |||
| 189 | static inline void dcache_enable(void) | ||
| 190 | { | ||
| 191 | #ifdef CONFIG_BFIN_DCACHE | ||
| 192 | unsigned long ctrl; | ||
| 193 | SSYNC(); | ||
| 194 | ctrl = bfin_read_DMEM_CONTROL(); | ||
| 195 | ctrl |= ENDCPLB; | ||
| 196 | bfin_write_DMEM_CONTROL(ctrl); | ||
| 197 | SSYNC(); | ||
| 198 | #endif | ||
| 199 | } | ||
| 200 | |||
| 201 | static inline void icache_disable(void) | ||
| 202 | { | ||
| 203 | #ifdef CONFIG_BFIN_ICACHE | ||
| 204 | unsigned long ctrl; | ||
| 205 | SSYNC(); | ||
| 206 | ctrl = bfin_read_IMEM_CONTROL(); | ||
| 207 | ctrl &= ~ENICPLB; | ||
| 208 | bfin_write_IMEM_CONTROL(ctrl); | ||
| 209 | SSYNC(); | ||
| 210 | #endif | ||
| 211 | } | ||
| 212 | |||
| 213 | static inline void icache_enable(void) | ||
| 214 | { | ||
| 215 | #ifdef CONFIG_BFIN_ICACHE | ||
| 216 | unsigned long ctrl; | ||
| 217 | SSYNC(); | ||
| 218 | ctrl = bfin_read_IMEM_CONTROL(); | ||
| 219 | ctrl |= ENICPLB; | ||
| 220 | bfin_write_IMEM_CONTROL(ctrl); | ||
| 221 | SSYNC(); | ||
| 222 | #endif | ||
| 223 | } | ||
| 224 | |||
| 225 | int bfin_pm_suspend_mem_enter(void) | 174 | int bfin_pm_suspend_mem_enter(void) |
| 226 | { | 175 | { |
| 227 | unsigned long flags; | 176 | unsigned long flags; |
| @@ -258,16 +207,19 @@ int bfin_pm_suspend_mem_enter(void) | |||
| 258 | 207 | ||
| 259 | bfin_gpio_pm_hibernate_suspend(); | 208 | bfin_gpio_pm_hibernate_suspend(); |
| 260 | 209 | ||
| 261 | dcache_disable(); | 210 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
| 262 | icache_disable(); | 211 | flushinv_all_dcache(); |
| 212 | #endif | ||
| 213 | _disable_dcplb(); | ||
| 214 | _disable_icplb(); | ||
| 263 | bf53x_suspend_l1_mem(memptr); | 215 | bf53x_suspend_l1_mem(memptr); |
| 264 | 216 | ||
| 265 | do_hibernate(wakeup | vr_wakeup); /* Goodbye */ | 217 | do_hibernate(wakeup | vr_wakeup); /* Goodbye */ |
| 266 | 218 | ||
| 267 | bf53x_resume_l1_mem(memptr); | 219 | bf53x_resume_l1_mem(memptr); |
| 268 | 220 | ||
| 269 | icache_enable(); | 221 | _enable_icplb(); |
| 270 | dcache_enable(); | 222 | _enable_dcplb(); |
| 271 | 223 | ||
| 272 | bfin_gpio_pm_hibernate_restore(); | 224 | bfin_gpio_pm_hibernate_restore(); |
| 273 | blackfin_dma_resume(); | 225 | blackfin_dma_resume(); |
