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-rw-r--r--arch/blackfin/mach-common/ints-priority.c743
1 files changed, 289 insertions, 454 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 1c8c4c7245c3..1177369f9922 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -15,35 +15,18 @@
15#include <linux/kernel_stat.h> 15#include <linux/kernel_stat.h>
16#include <linux/seq_file.h> 16#include <linux/seq_file.h>
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/sched.h>
18#ifdef CONFIG_IPIPE 19#ifdef CONFIG_IPIPE
19#include <linux/ipipe.h> 20#include <linux/ipipe.h>
20#endif 21#endif
21#ifdef CONFIG_KGDB
22#include <linux/kgdb.h>
23#endif
24#include <asm/traps.h> 22#include <asm/traps.h>
25#include <asm/blackfin.h> 23#include <asm/blackfin.h>
26#include <asm/gpio.h> 24#include <asm/gpio.h>
27#include <asm/irq_handler.h> 25#include <asm/irq_handler.h>
28#include <asm/dpmc.h> 26#include <asm/dpmc.h>
29#include <asm/bfin5xx_spi.h>
30#include <asm/bfin_sport.h>
31#include <asm/bfin_can.h>
32 27
33#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) 28#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
34 29
35#ifdef BF537_FAMILY
36# define BF537_GENERIC_ERROR_INT_DEMUX
37# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
38# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
39# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41# define UART_ERR_MASK (0x6) /* UART_IIR */
42# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
43#else
44# undef BF537_GENERIC_ERROR_INT_DEMUX
45#endif
46
47/* 30/*
48 * NOTES: 31 * NOTES:
49 * - we have separated the physical Hardware interrupt from the 32 * - we have separated the physical Hardware interrupt from the
@@ -62,22 +45,19 @@ unsigned long bfin_irq_flags = 0x1f;
62EXPORT_SYMBOL(bfin_irq_flags); 45EXPORT_SYMBOL(bfin_irq_flags);
63#endif 46#endif
64 47
65/* The number of spurious interrupts */
66atomic_t num_spurious;
67
68#ifdef CONFIG_PM 48#ifdef CONFIG_PM
69unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ 49unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
70unsigned vr_wakeup; 50unsigned vr_wakeup;
71#endif 51#endif
72 52
73struct ivgx { 53static struct ivgx {
74 /* irq number for request_irq, available in mach-bf5xx/irq.h */ 54 /* irq number for request_irq, available in mach-bf5xx/irq.h */
75 unsigned int irqno; 55 unsigned int irqno;
76 /* corresponding bit in the SIC_ISR register */ 56 /* corresponding bit in the SIC_ISR register */
77 unsigned int isrflag; 57 unsigned int isrflag;
78} ivg_table[NR_PERI_INTS]; 58} ivg_table[NR_PERI_INTS];
79 59
80struct ivg_slice { 60static struct ivg_slice {
81 /* position of first irq in ivg_table for given ivg */ 61 /* position of first irq in ivg_table for given ivg */
82 struct ivgx *ifirst; 62 struct ivgx *ifirst;
83 struct ivgx *istop; 63 struct ivgx *istop;
@@ -124,21 +104,21 @@ static void __init search_IAR(void)
124 * This is for core internal IRQs 104 * This is for core internal IRQs
125 */ 105 */
126 106
127static void bfin_ack_noop(unsigned int irq) 107void bfin_ack_noop(struct irq_data *d)
128{ 108{
129 /* Dummy function. */ 109 /* Dummy function. */
130} 110}
131 111
132static void bfin_core_mask_irq(unsigned int irq) 112static void bfin_core_mask_irq(struct irq_data *d)
133{ 113{
134 bfin_irq_flags &= ~(1 << irq); 114 bfin_irq_flags &= ~(1 << d->irq);
135 if (!irqs_disabled_hw()) 115 if (!hard_irqs_disabled())
136 local_irq_enable_hw(); 116 hard_local_irq_enable();
137} 117}
138 118
139static void bfin_core_unmask_irq(unsigned int irq) 119static void bfin_core_unmask_irq(struct irq_data *d)
140{ 120{
141 bfin_irq_flags |= 1 << irq; 121 bfin_irq_flags |= 1 << d->irq;
142 /* 122 /*
143 * If interrupts are enabled, IMASK must contain the same value 123 * If interrupts are enabled, IMASK must contain the same value
144 * as bfin_irq_flags. Make sure that invariant holds. If interrupts 124 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
@@ -148,82 +128,88 @@ static void bfin_core_unmask_irq(unsigned int irq)
148 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly 128 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
149 * what we need. 129 * what we need.
150 */ 130 */
151 if (!irqs_disabled_hw()) 131 if (!hard_irqs_disabled())
152 local_irq_enable_hw(); 132 hard_local_irq_enable();
153 return; 133 return;
154} 134}
155 135
156static void bfin_internal_mask_irq(unsigned int irq) 136void bfin_internal_mask_irq(unsigned int irq)
157{ 137{
158 unsigned long flags; 138 unsigned long flags = hard_local_irq_save();
159 139
160#ifdef CONFIG_BF53x 140#ifdef SIC_IMASK0
161 local_irq_save_hw(flags); 141 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
162 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 142 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
163 ~(1 << SIC_SYSIRQ(irq)));
164#else
165 unsigned mask_bank, mask_bit;
166 local_irq_save_hw(flags);
167 mask_bank = SIC_SYSIRQ(irq) / 32;
168 mask_bit = SIC_SYSIRQ(irq) % 32;
169 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 143 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
170 ~(1 << mask_bit)); 144 ~(1 << mask_bit));
171#ifdef CONFIG_SMP 145# ifdef CONFIG_SMP
172 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & 146 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
173 ~(1 << mask_bit)); 147 ~(1 << mask_bit));
148# endif
149#else
150 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
151 ~(1 << SIC_SYSIRQ(irq)));
174#endif 152#endif
175#endif 153
176 local_irq_restore_hw(flags); 154 hard_local_irq_restore(flags);
155}
156
157static void bfin_internal_mask_irq_chip(struct irq_data *d)
158{
159 bfin_internal_mask_irq(d->irq);
177} 160}
178 161
179#ifdef CONFIG_SMP 162#ifdef CONFIG_SMP
180static void bfin_internal_unmask_irq_affinity(unsigned int irq, 163static void bfin_internal_unmask_irq_affinity(unsigned int irq,
181 const struct cpumask *affinity) 164 const struct cpumask *affinity)
182#else 165#else
183static void bfin_internal_unmask_irq(unsigned int irq) 166void bfin_internal_unmask_irq(unsigned int irq)
184#endif 167#endif
185{ 168{
186 unsigned long flags; 169 unsigned long flags = hard_local_irq_save();
187 170
188#ifdef CONFIG_BF53x 171#ifdef SIC_IMASK0
189 local_irq_save_hw(flags); 172 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
190 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 173 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
191 (1 << SIC_SYSIRQ(irq))); 174# ifdef CONFIG_SMP
192#else
193 unsigned mask_bank, mask_bit;
194 local_irq_save_hw(flags);
195 mask_bank = SIC_SYSIRQ(irq) / 32;
196 mask_bit = SIC_SYSIRQ(irq) % 32;
197#ifdef CONFIG_SMP
198 if (cpumask_test_cpu(0, affinity)) 175 if (cpumask_test_cpu(0, affinity))
199#endif 176# endif
200 bfin_write_SIC_IMASK(mask_bank, 177 bfin_write_SIC_IMASK(mask_bank,
201 bfin_read_SIC_IMASK(mask_bank) | 178 bfin_read_SIC_IMASK(mask_bank) |
202 (1 << mask_bit)); 179 (1 << mask_bit));
203#ifdef CONFIG_SMP 180# ifdef CONFIG_SMP
204 if (cpumask_test_cpu(1, affinity)) 181 if (cpumask_test_cpu(1, affinity))
205 bfin_write_SICB_IMASK(mask_bank, 182 bfin_write_SICB_IMASK(mask_bank,
206 bfin_read_SICB_IMASK(mask_bank) | 183 bfin_read_SICB_IMASK(mask_bank) |
207 (1 << mask_bit)); 184 (1 << mask_bit));
185# endif
186#else
187 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
188 (1 << SIC_SYSIRQ(irq)));
208#endif 189#endif
209#endif 190
210 local_irq_restore_hw(flags); 191 hard_local_irq_restore(flags);
211} 192}
212 193
213#ifdef CONFIG_SMP 194#ifdef CONFIG_SMP
214static void bfin_internal_unmask_irq(unsigned int irq) 195static void bfin_internal_unmask_irq_chip(struct irq_data *d)
215{ 196{
216 struct irq_desc *desc = irq_to_desc(irq); 197 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
217 bfin_internal_unmask_irq_affinity(irq, desc->affinity);
218} 198}
219 199
220static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask) 200static int bfin_internal_set_affinity(struct irq_data *d,
201 const struct cpumask *mask, bool force)
221{ 202{
222 bfin_internal_mask_irq(irq); 203 bfin_internal_mask_irq(d->irq);
223 bfin_internal_unmask_irq_affinity(irq, mask); 204 bfin_internal_unmask_irq_affinity(d->irq, mask);
224 205
225 return 0; 206 return 0;
226} 207}
208#else
209static void bfin_internal_unmask_irq_chip(struct irq_data *d)
210{
211 bfin_internal_unmask_irq(d->irq);
212}
227#endif 213#endif
228 214
229#ifdef CONFIG_PM 215#ifdef CONFIG_PM
@@ -264,7 +250,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
264 break; 250 break;
265 } 251 }
266 252
267 local_irq_save_hw(flags); 253 flags = hard_local_irq_save();
268 254
269 if (state) { 255 if (state) {
270 bfin_sic_iwr[bank] |= (1 << bit); 256 bfin_sic_iwr[bank] |= (1 << bit);
@@ -275,36 +261,41 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
275 vr_wakeup &= ~wakeup; 261 vr_wakeup &= ~wakeup;
276 } 262 }
277 263
278 local_irq_restore_hw(flags); 264 hard_local_irq_restore(flags);
279 265
280 return 0; 266 return 0;
281} 267}
268
269static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
270{
271 return bfin_internal_set_wake(d->irq, state);
272}
273#else
274# define bfin_internal_set_wake_chip NULL
282#endif 275#endif
283 276
284static struct irq_chip bfin_core_irqchip = { 277static struct irq_chip bfin_core_irqchip = {
285 .name = "CORE", 278 .name = "CORE",
286 .ack = bfin_ack_noop, 279 .irq_ack = bfin_ack_noop,
287 .mask = bfin_core_mask_irq, 280 .irq_mask = bfin_core_mask_irq,
288 .unmask = bfin_core_unmask_irq, 281 .irq_unmask = bfin_core_unmask_irq,
289}; 282};
290 283
291static struct irq_chip bfin_internal_irqchip = { 284static struct irq_chip bfin_internal_irqchip = {
292 .name = "INTN", 285 .name = "INTN",
293 .ack = bfin_ack_noop, 286 .irq_ack = bfin_ack_noop,
294 .mask = bfin_internal_mask_irq, 287 .irq_mask = bfin_internal_mask_irq_chip,
295 .unmask = bfin_internal_unmask_irq, 288 .irq_unmask = bfin_internal_unmask_irq_chip,
296 .mask_ack = bfin_internal_mask_irq, 289 .irq_mask_ack = bfin_internal_mask_irq_chip,
297 .disable = bfin_internal_mask_irq, 290 .irq_disable = bfin_internal_mask_irq_chip,
298 .enable = bfin_internal_unmask_irq, 291 .irq_enable = bfin_internal_unmask_irq_chip,
299#ifdef CONFIG_SMP 292#ifdef CONFIG_SMP
300 .set_affinity = bfin_internal_set_affinity, 293 .irq_set_affinity = bfin_internal_set_affinity,
301#endif
302#ifdef CONFIG_PM
303 .set_wake = bfin_internal_set_wake,
304#endif 294#endif
295 .irq_set_wake = bfin_internal_set_wake_chip,
305}; 296};
306 297
307static void bfin_handle_irq(unsigned irq) 298void bfin_handle_irq(unsigned irq)
308{ 299{
309#ifdef CONFIG_IPIPE 300#ifdef CONFIG_IPIPE
310 struct pt_regs regs; /* Contents not used. */ 301 struct pt_regs regs; /* Contents not used. */
@@ -312,107 +303,10 @@ static void bfin_handle_irq(unsigned irq)
312 __ipipe_handle_irq(irq, &regs); 303 __ipipe_handle_irq(irq, &regs);
313 ipipe_trace_irq_exit(irq); 304 ipipe_trace_irq_exit(irq);
314#else /* !CONFIG_IPIPE */ 305#else /* !CONFIG_IPIPE */
315 struct irq_desc *desc = irq_desc + irq; 306 generic_handle_irq(irq);
316 desc->handle_irq(irq, desc);
317#endif /* !CONFIG_IPIPE */ 307#endif /* !CONFIG_IPIPE */
318} 308}
319 309
320#ifdef BF537_GENERIC_ERROR_INT_DEMUX
321static int error_int_mask;
322
323static void bfin_generic_error_mask_irq(unsigned int irq)
324{
325 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
326 if (!error_int_mask)
327 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
328}
329
330static void bfin_generic_error_unmask_irq(unsigned int irq)
331{
332 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
333 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
334}
335
336static struct irq_chip bfin_generic_error_irqchip = {
337 .name = "ERROR",
338 .ack = bfin_ack_noop,
339 .mask_ack = bfin_generic_error_mask_irq,
340 .mask = bfin_generic_error_mask_irq,
341 .unmask = bfin_generic_error_unmask_irq,
342};
343
344static void bfin_demux_error_irq(unsigned int int_err_irq,
345 struct irq_desc *inta_desc)
346{
347 int irq = 0;
348
349#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
350 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
351 irq = IRQ_MAC_ERROR;
352 else
353#endif
354 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
355 irq = IRQ_SPORT0_ERROR;
356 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
357 irq = IRQ_SPORT1_ERROR;
358 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
359 irq = IRQ_PPI_ERROR;
360 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
361 irq = IRQ_CAN_ERROR;
362 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
363 irq = IRQ_SPI_ERROR;
364 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
365 irq = IRQ_UART0_ERROR;
366 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
367 irq = IRQ_UART1_ERROR;
368
369 if (irq) {
370 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
371 bfin_handle_irq(irq);
372 else {
373
374 switch (irq) {
375 case IRQ_PPI_ERROR:
376 bfin_write_PPI_STATUS(PPI_ERR_MASK);
377 break;
378#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
379 case IRQ_MAC_ERROR:
380 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
381 break;
382#endif
383 case IRQ_SPORT0_ERROR:
384 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
385 break;
386
387 case IRQ_SPORT1_ERROR:
388 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
389 break;
390
391 case IRQ_CAN_ERROR:
392 bfin_write_CAN_GIS(CAN_ERR_MASK);
393 break;
394
395 case IRQ_SPI_ERROR:
396 bfin_write_SPI_STAT(SPI_ERR_MASK);
397 break;
398
399 default:
400 break;
401 }
402
403 pr_debug("IRQ %d:"
404 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
405 irq);
406 }
407 } else
408 printk(KERN_ERR
409 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
410 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
411 __func__, __FILE__, __LINE__);
412
413}
414#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
415
416#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 310#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
417static int mac_stat_int_mask; 311static int mac_stat_int_mask;
418 312
@@ -448,10 +342,12 @@ static void bfin_mac_status_ack_irq(unsigned int irq)
448 } 342 }
449} 343}
450 344
451static void bfin_mac_status_mask_irq(unsigned int irq) 345static void bfin_mac_status_mask_irq(struct irq_data *d)
452{ 346{
347 unsigned int irq = d->irq;
348
453 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); 349 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
454#ifdef BF537_GENERIC_ERROR_INT_DEMUX 350#ifdef BF537_FAMILY
455 switch (irq) { 351 switch (irq) {
456 case IRQ_MAC_PHYINT: 352 case IRQ_MAC_PHYINT:
457 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE); 353 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
@@ -466,9 +362,11 @@ static void bfin_mac_status_mask_irq(unsigned int irq)
466 bfin_mac_status_ack_irq(irq); 362 bfin_mac_status_ack_irq(irq);
467} 363}
468 364
469static void bfin_mac_status_unmask_irq(unsigned int irq) 365static void bfin_mac_status_unmask_irq(struct irq_data *d)
470{ 366{
471#ifdef BF537_GENERIC_ERROR_INT_DEMUX 367 unsigned int irq = d->irq;
368
369#ifdef BF537_FAMILY
472 switch (irq) { 370 switch (irq) {
473 case IRQ_MAC_PHYINT: 371 case IRQ_MAC_PHYINT:
474 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE); 372 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
@@ -484,34 +382,34 @@ static void bfin_mac_status_unmask_irq(unsigned int irq)
484} 382}
485 383
486#ifdef CONFIG_PM 384#ifdef CONFIG_PM
487int bfin_mac_status_set_wake(unsigned int irq, unsigned int state) 385int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
488{ 386{
489#ifdef BF537_GENERIC_ERROR_INT_DEMUX 387#ifdef BF537_FAMILY
490 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); 388 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
491#else 389#else
492 return bfin_internal_set_wake(IRQ_MAC_ERROR, state); 390 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
493#endif 391#endif
494} 392}
393#else
394# define bfin_mac_status_set_wake NULL
495#endif 395#endif
496 396
497static struct irq_chip bfin_mac_status_irqchip = { 397static struct irq_chip bfin_mac_status_irqchip = {
498 .name = "MACST", 398 .name = "MACST",
499 .ack = bfin_ack_noop, 399 .irq_ack = bfin_ack_noop,
500 .mask_ack = bfin_mac_status_mask_irq, 400 .irq_mask_ack = bfin_mac_status_mask_irq,
501 .mask = bfin_mac_status_mask_irq, 401 .irq_mask = bfin_mac_status_mask_irq,
502 .unmask = bfin_mac_status_unmask_irq, 402 .irq_unmask = bfin_mac_status_unmask_irq,
503#ifdef CONFIG_PM 403 .irq_set_wake = bfin_mac_status_set_wake,
504 .set_wake = bfin_mac_status_set_wake,
505#endif
506}; 404};
507 405
508static void bfin_demux_mac_status_irq(unsigned int int_err_irq, 406void bfin_demux_mac_status_irq(unsigned int int_err_irq,
509 struct irq_desc *inta_desc) 407 struct irq_desc *inta_desc)
510{ 408{
511 int i, irq = 0; 409 int i, irq = 0;
512 u32 status = bfin_read_EMAC_SYSTAT(); 410 u32 status = bfin_read_EMAC_SYSTAT();
513 411
514 for (i = 0; i < (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) 412 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
515 if (status & (1L << i)) { 413 if (status & (1L << i)) {
516 irq = IRQ_MAC_PHYINT + i; 414 irq = IRQ_MAC_PHYINT + i;
517 break; 415 break;
@@ -529,21 +427,18 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
529 } else 427 } else
530 printk(KERN_ERR 428 printk(KERN_ERR
531 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" 429 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
532 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", 430 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
533 __func__, __FILE__, __LINE__); 431 "(EMAC_SYSTAT=0x%X)\n",
432 __func__, __FILE__, __LINE__, status);
534} 433}
535#endif 434#endif
536 435
537static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) 436static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
538{ 437{
539#ifdef CONFIG_IPIPE 438#ifdef CONFIG_IPIPE
540 _set_irq_handler(irq, handle_level_irq); 439 handle = handle_level_irq;
541#else
542 struct irq_desc *desc = irq_desc + irq;
543 /* May not call generic set_irq_handler() due to spinlock
544 recursion. */
545 desc->handle_irq = handle;
546#endif 440#endif
441 __irq_set_handler_locked(irq, handle);
547} 442}
548 443
549static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); 444static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
@@ -551,58 +446,59 @@ extern void bfin_gpio_irq_prepare(unsigned gpio);
551 446
552#if !defined(CONFIG_BF54x) 447#if !defined(CONFIG_BF54x)
553 448
554static void bfin_gpio_ack_irq(unsigned int irq) 449static void bfin_gpio_ack_irq(struct irq_data *d)
555{ 450{
556 /* AFAIK ack_irq in case mask_ack is provided 451 /* AFAIK ack_irq in case mask_ack is provided
557 * get's only called for edge sense irqs 452 * get's only called for edge sense irqs
558 */ 453 */
559 set_gpio_data(irq_to_gpio(irq), 0); 454 set_gpio_data(irq_to_gpio(d->irq), 0);
560} 455}
561 456
562static void bfin_gpio_mask_ack_irq(unsigned int irq) 457static void bfin_gpio_mask_ack_irq(struct irq_data *d)
563{ 458{
564 struct irq_desc *desc = irq_desc + irq; 459 unsigned int irq = d->irq;
565 u32 gpionr = irq_to_gpio(irq); 460 u32 gpionr = irq_to_gpio(irq);
566 461
567 if (desc->handle_irq == handle_edge_irq) 462 if (!irqd_is_level_type(d))
568 set_gpio_data(gpionr, 0); 463 set_gpio_data(gpionr, 0);
569 464
570 set_gpio_maska(gpionr, 0); 465 set_gpio_maska(gpionr, 0);
571} 466}
572 467
573static void bfin_gpio_mask_irq(unsigned int irq) 468static void bfin_gpio_mask_irq(struct irq_data *d)
574{ 469{
575 set_gpio_maska(irq_to_gpio(irq), 0); 470 set_gpio_maska(irq_to_gpio(d->irq), 0);
576} 471}
577 472
578static void bfin_gpio_unmask_irq(unsigned int irq) 473static void bfin_gpio_unmask_irq(struct irq_data *d)
579{ 474{
580 set_gpio_maska(irq_to_gpio(irq), 1); 475 set_gpio_maska(irq_to_gpio(d->irq), 1);
581} 476}
582 477
583static unsigned int bfin_gpio_irq_startup(unsigned int irq) 478static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
584{ 479{
585 u32 gpionr = irq_to_gpio(irq); 480 u32 gpionr = irq_to_gpio(d->irq);
586 481
587 if (__test_and_set_bit(gpionr, gpio_enabled)) 482 if (__test_and_set_bit(gpionr, gpio_enabled))
588 bfin_gpio_irq_prepare(gpionr); 483 bfin_gpio_irq_prepare(gpionr);
589 484
590 bfin_gpio_unmask_irq(irq); 485 bfin_gpio_unmask_irq(d);
591 486
592 return 0; 487 return 0;
593} 488}
594 489
595static void bfin_gpio_irq_shutdown(unsigned int irq) 490static void bfin_gpio_irq_shutdown(struct irq_data *d)
596{ 491{
597 u32 gpionr = irq_to_gpio(irq); 492 u32 gpionr = irq_to_gpio(d->irq);
598 493
599 bfin_gpio_mask_irq(irq); 494 bfin_gpio_mask_irq(d);
600 __clear_bit(gpionr, gpio_enabled); 495 __clear_bit(gpionr, gpio_enabled);
601 bfin_gpio_irq_free(gpionr); 496 bfin_gpio_irq_free(gpionr);
602} 497}
603 498
604static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) 499static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
605{ 500{
501 unsigned int irq = d->irq;
606 int ret; 502 int ret;
607 char buf[16]; 503 char buf[16];
608 u32 gpionr = irq_to_gpio(irq); 504 u32 gpionr = irq_to_gpio(irq);
@@ -663,29 +559,48 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
663} 559}
664 560
665#ifdef CONFIG_PM 561#ifdef CONFIG_PM
666int bfin_gpio_set_wake(unsigned int irq, unsigned int state) 562static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
667{ 563{
668 return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state); 564 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
669} 565}
566#else
567# define bfin_gpio_set_wake NULL
670#endif 568#endif
671 569
672static void bfin_demux_gpio_irq(unsigned int inta_irq, 570static void bfin_demux_gpio_block(unsigned int irq)
673 struct irq_desc *desc)
674{ 571{
675 unsigned int i, gpio, mask, irq, search = 0; 572 unsigned int gpio, mask;
573
574 gpio = irq_to_gpio(irq);
575 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
576
577 while (mask) {
578 if (mask & 1)
579 bfin_handle_irq(irq);
580 irq++;
581 mask >>= 1;
582 }
583}
584
585void bfin_demux_gpio_irq(unsigned int inta_irq,
586 struct irq_desc *desc)
587{
588 unsigned int irq;
676 589
677 switch (inta_irq) { 590 switch (inta_irq) {
678#if defined(CONFIG_BF53x) 591#if defined(BF537_FAMILY)
679 case IRQ_PROG_INTA: 592 case IRQ_PF_INTA_PG_INTA:
680 irq = IRQ_PF0; 593 bfin_demux_gpio_block(IRQ_PF0);
681 search = 1; 594 irq = IRQ_PG0;
682 break; 595 break;
683# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 596 case IRQ_PH_INTA_MAC_RX:
684 case IRQ_MAC_RX:
685 irq = IRQ_PH0; 597 irq = IRQ_PH0;
686 break; 598 break;
687# endif 599#elif defined(BF533_FAMILY)
688#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) 600 case IRQ_PROG_INTA:
601 irq = IRQ_PF0;
602 break;
603#elif defined(BF538_FAMILY)
689 case IRQ_PORTF_INTA: 604 case IRQ_PORTF_INTA:
690 irq = IRQ_PF0; 605 irq = IRQ_PF0;
691 break; 606 break;
@@ -715,31 +630,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
715 return; 630 return;
716 } 631 }
717 632
718 if (search) { 633 bfin_demux_gpio_block(irq);
719 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
720 irq += i;
721
722 mask = get_gpiop_data(i) & get_gpiop_maska(i);
723
724 while (mask) {
725 if (mask & 1)
726 bfin_handle_irq(irq);
727 irq++;
728 mask >>= 1;
729 }
730 }
731 } else {
732 gpio = irq_to_gpio(irq);
733 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
734
735 do {
736 if (mask & 1)
737 bfin_handle_irq(irq);
738 irq++;
739 mask >>= 1;
740 } while (mask);
741 }
742
743} 634}
744 635
745#else /* CONFIG_BF54x */ 636#else /* CONFIG_BF54x */
@@ -817,14 +708,13 @@ void init_pint_lut(void)
817 } 708 }
818} 709}
819 710
820static void bfin_gpio_ack_irq(unsigned int irq) 711static void bfin_gpio_ack_irq(struct irq_data *d)
821{ 712{
822 struct irq_desc *desc = irq_desc + irq; 713 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
823 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
824 u32 pintbit = PINT_BIT(pint_val); 714 u32 pintbit = PINT_BIT(pint_val);
825 u32 bank = PINT_2_BANK(pint_val); 715 u32 bank = PINT_2_BANK(pint_val);
826 716
827 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 717 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
828 if (pint[bank]->invert_set & pintbit) 718 if (pint[bank]->invert_set & pintbit)
829 pint[bank]->invert_clear = pintbit; 719 pint[bank]->invert_clear = pintbit;
830 else 720 else
@@ -834,14 +724,13 @@ static void bfin_gpio_ack_irq(unsigned int irq)
834 724
835} 725}
836 726
837static void bfin_gpio_mask_ack_irq(unsigned int irq) 727static void bfin_gpio_mask_ack_irq(struct irq_data *d)
838{ 728{
839 struct irq_desc *desc = irq_desc + irq; 729 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
840 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
841 u32 pintbit = PINT_BIT(pint_val); 730 u32 pintbit = PINT_BIT(pint_val);
842 u32 bank = PINT_2_BANK(pint_val); 731 u32 bank = PINT_2_BANK(pint_val);
843 732
844 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 733 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
845 if (pint[bank]->invert_set & pintbit) 734 if (pint[bank]->invert_set & pintbit)
846 pint[bank]->invert_clear = pintbit; 735 pint[bank]->invert_clear = pintbit;
847 else 736 else
@@ -852,25 +741,25 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq)
852 pint[bank]->mask_clear = pintbit; 741 pint[bank]->mask_clear = pintbit;
853} 742}
854 743
855static void bfin_gpio_mask_irq(unsigned int irq) 744static void bfin_gpio_mask_irq(struct irq_data *d)
856{ 745{
857 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 746 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
858 747
859 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); 748 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
860} 749}
861 750
862static void bfin_gpio_unmask_irq(unsigned int irq) 751static void bfin_gpio_unmask_irq(struct irq_data *d)
863{ 752{
864 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 753 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
865 u32 pintbit = PINT_BIT(pint_val); 754 u32 pintbit = PINT_BIT(pint_val);
866 u32 bank = PINT_2_BANK(pint_val); 755 u32 bank = PINT_2_BANK(pint_val);
867 756
868 pint[bank]->request = pintbit;
869 pint[bank]->mask_set = pintbit; 757 pint[bank]->mask_set = pintbit;
870} 758}
871 759
872static unsigned int bfin_gpio_irq_startup(unsigned int irq) 760static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
873{ 761{
762 unsigned int irq = d->irq;
874 u32 gpionr = irq_to_gpio(irq); 763 u32 gpionr = irq_to_gpio(irq);
875 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 764 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
876 765
@@ -884,22 +773,23 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
884 if (__test_and_set_bit(gpionr, gpio_enabled)) 773 if (__test_and_set_bit(gpionr, gpio_enabled))
885 bfin_gpio_irq_prepare(gpionr); 774 bfin_gpio_irq_prepare(gpionr);
886 775
887 bfin_gpio_unmask_irq(irq); 776 bfin_gpio_unmask_irq(d);
888 777
889 return 0; 778 return 0;
890} 779}
891 780
892static void bfin_gpio_irq_shutdown(unsigned int irq) 781static void bfin_gpio_irq_shutdown(struct irq_data *d)
893{ 782{
894 u32 gpionr = irq_to_gpio(irq); 783 u32 gpionr = irq_to_gpio(d->irq);
895 784
896 bfin_gpio_mask_irq(irq); 785 bfin_gpio_mask_irq(d);
897 __clear_bit(gpionr, gpio_enabled); 786 __clear_bit(gpionr, gpio_enabled);
898 bfin_gpio_irq_free(gpionr); 787 bfin_gpio_irq_free(gpionr);
899} 788}
900 789
901static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) 790static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
902{ 791{
792 unsigned int irq = d->irq;
903 int ret; 793 int ret;
904 char buf[16]; 794 char buf[16];
905 u32 gpionr = irq_to_gpio(irq); 795 u32 gpionr = irq_to_gpio(irq);
@@ -958,15 +848,11 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
958} 848}
959 849
960#ifdef CONFIG_PM 850#ifdef CONFIG_PM
961u32 pint_saved_masks[NR_PINT_SYS_IRQS]; 851static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
962u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
963
964int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
965{ 852{
966 u32 pint_irq; 853 u32 pint_irq;
967 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 854 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
968 u32 bank = PINT_2_BANK(pint_val); 855 u32 bank = PINT_2_BANK(pint_val);
969 u32 pintbit = PINT_BIT(pint_val);
970 856
971 switch (bank) { 857 switch (bank) {
972 case 0: 858 case 0:
@@ -987,46 +873,14 @@ int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
987 873
988 bfin_internal_set_wake(pint_irq, state); 874 bfin_internal_set_wake(pint_irq, state);
989 875
990 if (state)
991 pint_wakeup_masks[bank] |= pintbit;
992 else
993 pint_wakeup_masks[bank] &= ~pintbit;
994
995 return 0;
996}
997
998u32 bfin_pm_setup(void)
999{
1000 u32 val, i;
1001
1002 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1003 val = pint[i]->mask_clear;
1004 pint_saved_masks[i] = val;
1005 if (val ^ pint_wakeup_masks[i]) {
1006 pint[i]->mask_clear = val;
1007 pint[i]->mask_set = pint_wakeup_masks[i];
1008 }
1009 }
1010
1011 return 0; 876 return 0;
1012} 877}
1013 878#else
1014void bfin_pm_restore(void) 879# define bfin_gpio_set_wake NULL
1015{
1016 u32 i, val;
1017
1018 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1019 val = pint_saved_masks[i];
1020 if (val ^ pint_wakeup_masks[i]) {
1021 pint[i]->mask_clear = pint[i]->mask_clear;
1022 pint[i]->mask_set = val;
1023 }
1024 }
1025}
1026#endif 880#endif
1027 881
1028static void bfin_demux_gpio_irq(unsigned int inta_irq, 882void bfin_demux_gpio_irq(unsigned int inta_irq,
1029 struct irq_desc *desc) 883 struct irq_desc *desc)
1030{ 884{
1031 u32 bank, pint_val; 885 u32 bank, pint_val;
1032 u32 request, irq; 886 u32 request, irq;
@@ -1066,18 +920,16 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
1066 920
1067static struct irq_chip bfin_gpio_irqchip = { 921static struct irq_chip bfin_gpio_irqchip = {
1068 .name = "GPIO", 922 .name = "GPIO",
1069 .ack = bfin_gpio_ack_irq, 923 .irq_ack = bfin_gpio_ack_irq,
1070 .mask = bfin_gpio_mask_irq, 924 .irq_mask = bfin_gpio_mask_irq,
1071 .mask_ack = bfin_gpio_mask_ack_irq, 925 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1072 .unmask = bfin_gpio_unmask_irq, 926 .irq_unmask = bfin_gpio_unmask_irq,
1073 .disable = bfin_gpio_mask_irq, 927 .irq_disable = bfin_gpio_mask_irq,
1074 .enable = bfin_gpio_unmask_irq, 928 .irq_enable = bfin_gpio_unmask_irq,
1075 .set_type = bfin_gpio_irq_type, 929 .irq_set_type = bfin_gpio_irq_type,
1076 .startup = bfin_gpio_irq_startup, 930 .irq_startup = bfin_gpio_irq_startup,
1077 .shutdown = bfin_gpio_irq_shutdown, 931 .irq_shutdown = bfin_gpio_irq_shutdown,
1078#ifdef CONFIG_PM 932 .irq_set_wake = bfin_gpio_set_wake,
1079 .set_wake = bfin_gpio_set_wake,
1080#endif
1081}; 933};
1082 934
1083void __cpuinit init_exception_vectors(void) 935void __cpuinit init_exception_vectors(void)
@@ -1111,12 +963,12 @@ int __init init_arch_irq(void)
1111{ 963{
1112 int irq; 964 int irq;
1113 unsigned long ilat = 0; 965 unsigned long ilat = 0;
966
1114 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 967 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1115#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ 968#ifdef SIC_IMASK0
1116 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1117 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 969 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1118 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 970 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1119# ifdef CONFIG_BF54x 971# ifdef SIC_IMASK2
1120 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); 972 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1121# endif 973# endif
1122# ifdef CONFIG_SMP 974# ifdef CONFIG_SMP
@@ -1129,11 +981,6 @@ int __init init_arch_irq(void)
1129 981
1130 local_irq_disable(); 982 local_irq_disable();
1131 983
1132#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1133 /* Clear EMAC Interrupt Status bits so we can demux it later */
1134 bfin_write_EMAC_SYSTAT(-1);
1135#endif
1136
1137#ifdef CONFIG_BF54x 984#ifdef CONFIG_BF54x
1138# ifdef CONFIG_PINTx_REASSIGN 985# ifdef CONFIG_PINTx_REASSIGN
1139 pint[0]->assign = CONFIG_PINT0_ASSIGN; 986 pint[0]->assign = CONFIG_PINT0_ASSIGN;
@@ -1147,16 +994,16 @@ int __init init_arch_irq(void)
1147 994
1148 for (irq = 0; irq <= SYS_IRQS; irq++) { 995 for (irq = 0; irq <= SYS_IRQS; irq++) {
1149 if (irq <= IRQ_CORETMR) 996 if (irq <= IRQ_CORETMR)
1150 set_irq_chip(irq, &bfin_core_irqchip); 997 irq_set_chip(irq, &bfin_core_irqchip);
1151 else 998 else
1152 set_irq_chip(irq, &bfin_internal_irqchip); 999 irq_set_chip(irq, &bfin_internal_irqchip);
1153 1000
1154 switch (irq) { 1001 switch (irq) {
1155#if defined(CONFIG_BF53x) 1002#if defined(BF537_FAMILY)
1003 case IRQ_PH_INTA_MAC_RX:
1004 case IRQ_PF_INTA_PG_INTA:
1005#elif defined(BF533_FAMILY)
1156 case IRQ_PROG_INTA: 1006 case IRQ_PROG_INTA:
1157# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1158 case IRQ_MAC_RX:
1159# endif
1160#elif defined(CONFIG_BF54x) 1007#elif defined(CONFIG_BF54x)
1161 case IRQ_PINT0: 1008 case IRQ_PINT0:
1162 case IRQ_PINT1: 1009 case IRQ_PINT1:
@@ -1170,76 +1017,61 @@ int __init init_arch_irq(void)
1170 case IRQ_PROG0_INTA: 1017 case IRQ_PROG0_INTA:
1171 case IRQ_PROG1_INTA: 1018 case IRQ_PROG1_INTA:
1172 case IRQ_PROG2_INTA: 1019 case IRQ_PROG2_INTA:
1173#elif defined(CONFIG_BF538) || defined(CONFIG_BF539) 1020#elif defined(BF538_FAMILY)
1174 case IRQ_PORTF_INTA: 1021 case IRQ_PORTF_INTA:
1175#endif 1022#endif
1176 set_irq_chained_handler(irq, 1023 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1177 bfin_demux_gpio_irq);
1178 break; 1024 break;
1179#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1180 case IRQ_GENERIC_ERROR:
1181 set_irq_chained_handler(irq, bfin_demux_error_irq);
1182 break;
1183#endif
1184#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1025#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1185 case IRQ_MAC_ERROR: 1026 case IRQ_MAC_ERROR:
1186 set_irq_chained_handler(irq, bfin_demux_mac_status_irq); 1027 irq_set_chained_handler(irq,
1028 bfin_demux_mac_status_irq);
1187 break; 1029 break;
1188#endif 1030#endif
1189#ifdef CONFIG_SMP 1031#ifdef CONFIG_SMP
1190 case IRQ_SUPPLE_0: 1032 case IRQ_SUPPLE_0:
1191 case IRQ_SUPPLE_1: 1033 case IRQ_SUPPLE_1:
1192 set_irq_handler(irq, handle_percpu_irq); 1034 irq_set_handler(irq, handle_percpu_irq);
1193 break; 1035 break;
1194#endif 1036#endif
1195 1037
1196#ifdef CONFIG_TICKSOURCE_CORETMR 1038#ifdef CONFIG_TICKSOURCE_CORETMR
1197 case IRQ_CORETMR: 1039 case IRQ_CORETMR:
1198# ifdef CONFIG_SMP 1040# ifdef CONFIG_SMP
1199 set_irq_handler(irq, handle_percpu_irq); 1041 irq_set_handler(irq, handle_percpu_irq);
1200 break;
1201# else 1042# else
1202 set_irq_handler(irq, handle_simple_irq); 1043 irq_set_handler(irq, handle_simple_irq);
1203 break;
1204# endif 1044# endif
1045 break;
1205#endif 1046#endif
1206 1047
1207#ifdef CONFIG_TICKSOURCE_GPTMR0 1048#ifdef CONFIG_TICKSOURCE_GPTMR0
1208 case IRQ_TIMER0: 1049 case IRQ_TIMER0:
1209 set_irq_handler(irq, handle_simple_irq); 1050 irq_set_handler(irq, handle_simple_irq);
1210 break; 1051 break;
1211#endif 1052#endif
1212 1053
1213#ifdef CONFIG_IPIPE
1214 default: 1054 default:
1215 set_irq_handler(irq, handle_level_irq); 1055#ifdef CONFIG_IPIPE
1216 break; 1056 irq_set_handler(irq, handle_level_irq);
1217#else /* !CONFIG_IPIPE */ 1057#else
1218 default: 1058 irq_set_handler(irq, handle_simple_irq);
1219 set_irq_handler(irq, handle_simple_irq); 1059#endif
1220 break; 1060 break;
1221#endif /* !CONFIG_IPIPE */
1222 } 1061 }
1223 } 1062 }
1224 1063
1225#ifdef BF537_GENERIC_ERROR_INT_DEMUX 1064 init_mach_irq();
1226 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1227 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1228 handle_level_irq);
1229#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1230 set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1231#endif
1232#endif
1233 1065
1234#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1066#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1235 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) 1067 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1236 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip, 1068 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1237 handle_level_irq); 1069 handle_level_irq);
1238#endif 1070#endif
1239 /* if configured as edge, then will be changed to do_edge_IRQ */ 1071 /* if configured as edge, then will be changed to do_edge_IRQ */
1240 for (irq = GPIO_IRQ_BASE; 1072 for (irq = GPIO_IRQ_BASE;
1241 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) 1073 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1242 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, 1074 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1243 handle_level_irq); 1075 handle_level_irq);
1244 1076
1245 bfin_write_IMASK(0); 1077 bfin_write_IMASK(0);
@@ -1291,53 +1123,54 @@ int __init init_arch_irq(void)
1291#ifdef CONFIG_DO_IRQ_L1 1123#ifdef CONFIG_DO_IRQ_L1
1292__attribute__((l1_text)) 1124__attribute__((l1_text))
1293#endif 1125#endif
1294void do_irq(int vec, struct pt_regs *fp) 1126static int vec_to_irq(int vec)
1295{ 1127{
1296 if (vec == EVT_IVTMR_P) { 1128 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1297 vec = IRQ_CORETMR; 1129 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1298 } else { 1130 unsigned long sic_status[3];
1299 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1300 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1301#if defined(SIC_ISR0) || defined(SICA_ISR0)
1302 unsigned long sic_status[3];
1303 1131
1304 if (smp_processor_id()) { 1132 if (likely(vec == EVT_IVTMR_P))
1133 return IRQ_CORETMR;
1134
1135#ifdef SIC_ISR
1136 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1137#else
1138 if (smp_processor_id()) {
1305# ifdef SICB_ISR0 1139# ifdef SICB_ISR0
1306 /* This will be optimized out in UP mode. */ 1140 /* This will be optimized out in UP mode. */
1307 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); 1141 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1308 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); 1142 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1309# endif
1310 } else {
1311 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1312 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1313 }
1314# ifdef SIC_ISR2
1315 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1316# endif 1143# endif
1317 for (;; ivg++) { 1144 } else {
1318 if (ivg >= ivg_stop) { 1145 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1319 atomic_inc(&num_spurious); 1146 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1320 return; 1147 }
1321 } 1148#endif
1322 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) 1149#ifdef SIC_ISR2
1323 break; 1150 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1324 } 1151#endif
1325#else
1326 unsigned long sic_status;
1327
1328 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1329 1152
1330 for (;; ivg++) { 1153 for (;; ivg++) {
1331 if (ivg >= ivg_stop) { 1154 if (ivg >= ivg_stop)
1332 atomic_inc(&num_spurious); 1155 return -1;
1333 return; 1156#ifdef SIC_ISR
1334 } else if (sic_status & ivg->isrflag) 1157 if (sic_status[0] & ivg->isrflag)
1335 break; 1158#else
1336 } 1159 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1337#endif 1160#endif
1338 vec = ivg->irqno; 1161 return ivg->irqno;
1339 } 1162 }
1340 asm_do_IRQ(vec, fp); 1163}
1164
1165#ifdef CONFIG_DO_IRQ_L1
1166__attribute__((l1_text))
1167#endif
1168void do_irq(int vec, struct pt_regs *fp)
1169{
1170 int irq = vec_to_irq(vec);
1171 if (irq == -1)
1172 return;
1173 asm_do_IRQ(irq, fp);
1341} 1174}
1342 1175
1343#ifdef CONFIG_IPIPE 1176#ifdef CONFIG_IPIPE
@@ -1373,42 +1206,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1373 struct ipipe_domain *this_domain = __ipipe_current_domain; 1206 struct ipipe_domain *this_domain = __ipipe_current_domain;
1374 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; 1207 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1375 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; 1208 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1376 int irq, s; 1209 int irq, s = 0;
1377 1210
1378 if (likely(vec == EVT_IVTMR_P)) 1211 irq = vec_to_irq(vec);
1379 irq = IRQ_CORETMR; 1212 if (irq == -1)
1380 else { 1213 return 0;
1381#if defined(SIC_ISR0) || defined(SICA_ISR0)
1382 unsigned long sic_status[3];
1383
1384 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1385 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1386# ifdef SIC_ISR2
1387 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1388# endif
1389 for (;; ivg++) {
1390 if (ivg >= ivg_stop) {
1391 atomic_inc(&num_spurious);
1392 return 0;
1393 }
1394 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1395 break;
1396 }
1397#else
1398 unsigned long sic_status;
1399
1400 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1401
1402 for (;; ivg++) {
1403 if (ivg >= ivg_stop) {
1404 atomic_inc(&num_spurious);
1405 return 0;
1406 } else if (sic_status & ivg->isrflag)
1407 break;
1408 }
1409#endif
1410 irq = ivg->irqno;
1411 }
1412 1214
1413 if (irq == IRQ_SYSTMR) { 1215 if (irq == IRQ_SYSTMR) {
1414#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) 1216#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
@@ -1423,6 +1225,21 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1423 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; 1225 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1424 } 1226 }
1425 1227
1228 /*
1229 * We don't want Linux interrupt handlers to run at the
1230 * current core priority level (i.e. < EVT15), since this
1231 * might delay other interrupts handled by a high priority
1232 * domain. Here is what we do instead:
1233 *
1234 * - we raise the SYNCDEFER bit to prevent
1235 * __ipipe_handle_irq() to sync the pipeline for the root
1236 * stage for the incoming interrupt. Upon return, that IRQ is
1237 * pending in the interrupt log.
1238 *
1239 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1240 * that _schedule_and_signal_from_int will eventually sync the
1241 * pipeline from EVT15.
1242 */
1426 if (this_domain == ipipe_root_domain) { 1243 if (this_domain == ipipe_root_domain) {
1427 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); 1244 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1428 barrier(); 1245 barrier();
@@ -1432,6 +1249,24 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1432 __ipipe_handle_irq(irq, regs); 1249 __ipipe_handle_irq(irq, regs);
1433 ipipe_trace_irq_exit(irq); 1250 ipipe_trace_irq_exit(irq);
1434 1251
1252 if (user_mode(regs) &&
1253 !ipipe_test_foreign_stack() &&
1254 (current->ipipe_flags & PF_EVTRET) != 0) {
1255 /*
1256 * Testing for user_regs() does NOT fully eliminate
1257 * foreign stack contexts, because of the forged
1258 * interrupt returns we do through
1259 * __ipipe_call_irqtail. In that case, we might have
1260 * preempted a foreign stack context in a high
1261 * priority domain, with a single interrupt level now
1262 * pending after the irqtail unwinding is done. In
1263 * which case user_mode() is now true, and the event
1264 * gets dispatched spuriously.
1265 */
1266 current->ipipe_flags &= ~PF_EVTRET;
1267 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1268 }
1269
1435 if (this_domain == ipipe_root_domain) { 1270 if (this_domain == ipipe_root_domain) {
1436 set_thread_flag(TIF_IRQ_SYNC); 1271 set_thread_flag(TIF_IRQ_SYNC);
1437 if (!s) { 1272 if (!s) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 11:44:18 -0500