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Diffstat (limited to 'arch/blackfin/mach-common/ints-priority-sc.c')
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c41
1 files changed, 31 insertions, 10 deletions
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index d3b7672b2b94..e06fe96b6fc3 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -92,10 +92,15 @@ static void __init search_IAR(void)
92 92
93 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { 93 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
94 int iar_shift = (irqn & 7) * 4; 94 int iar_shift = (irqn & 7) * 4;
95 if (ivg == 95 if (ivg ==
96 (0xf & 96 (0xf &
97#ifndef CONFIG_BF52x
97 bfin_read32((unsigned long *)SIC_IAR0 + 98 bfin_read32((unsigned long *)SIC_IAR0 +
98 (irqn >> 3)) >> iar_shift)) { 99 (irqn >> 3)) >> iar_shift)) {
100#else
101 bfin_read32((unsigned long *)SIC_IAR0 +
102 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
103#endif
99 ivg_table[irq_pos].irqno = IVG7 + irqn; 104 ivg_table[irq_pos].irqno = IVG7 + irqn;
100 ivg_table[irq_pos].isrflag = 1 << (irqn % 32); 105 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
101 ivg7_13[ivg].istop++; 106 ivg7_13[ivg].istop++;
@@ -140,7 +145,7 @@ static void bfin_core_unmask_irq(unsigned int irq)
140 145
141static void bfin_internal_mask_irq(unsigned int irq) 146static void bfin_internal_mask_irq(unsigned int irq)
142{ 147{
143#ifndef CONFIG_BF54x 148#ifdef CONFIG_BF53x
144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 149 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
145 ~(1 << (irq - (IRQ_CORETMR + 1)))); 150 ~(1 << (irq - (IRQ_CORETMR + 1))));
146#else 151#else
@@ -155,7 +160,7 @@ static void bfin_internal_mask_irq(unsigned int irq)
155 160
156static void bfin_internal_unmask_irq(unsigned int irq) 161static void bfin_internal_unmask_irq(unsigned int irq)
157{ 162{
158#ifndef CONFIG_BF54x 163#ifdef CONFIG_BF53x
159 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 164 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
160 (1 << (irq - (IRQ_CORETMR + 1)))); 165 (1 << (irq - (IRQ_CORETMR + 1))));
161#else 166#else
@@ -750,13 +755,15 @@ int __init init_arch_irq(void)
750 int irq; 755 int irq;
751 unsigned long ilat = 0; 756 unsigned long ilat = 0;
752 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 757 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
753#ifdef CONFIG_BF54x 758#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
754 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 759 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
755 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); 760 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
756 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
757 bfin_write_SIC_IWR0(IWR_ENABLE_ALL); 761 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
758 bfin_write_SIC_IWR1(IWR_ENABLE_ALL); 762 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
763#ifdef CONFIG_BF54x
764 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
759 bfin_write_SIC_IWR2(IWR_ENABLE_ALL); 765 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
766#endif
760#else 767#else
761 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 768 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
762 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 769 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
@@ -787,7 +794,7 @@ int __init init_arch_irq(void)
787 794
788 switch (irq) { 795 switch (irq) {
789#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 796#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
790#ifndef CONFIG_BF54x 797#if defined(CONFIG_BF53x)
791 case IRQ_PROG_INTA: 798 case IRQ_PROG_INTA:
792 set_irq_chained_handler(irq, 799 set_irq_chained_handler(irq,
793 bfin_demux_gpio_irq); 800 bfin_demux_gpio_irq);
@@ -798,7 +805,7 @@ int __init init_arch_irq(void)
798 bfin_demux_gpio_irq); 805 bfin_demux_gpio_irq);
799 break; 806 break;
800#endif 807#endif
801#else 808#elif defined(CONFIG_BF54x)
802 case IRQ_PINT0: 809 case IRQ_PINT0:
803 set_irq_chained_handler(irq, 810 set_irq_chained_handler(irq,
804 bfin_demux_gpio_irq); 811 bfin_demux_gpio_irq);
@@ -815,7 +822,20 @@ int __init init_arch_irq(void)
815 set_irq_chained_handler(irq, 822 set_irq_chained_handler(irq,
816 bfin_demux_gpio_irq); 823 bfin_demux_gpio_irq);
817 break; 824 break;
818#endif /*CONFIG_BF54x */ 825#elif defined(CONFIG_BF52x)
826 case IRQ_PORTF_INTA:
827 set_irq_chained_handler(irq,
828 bfin_demux_gpio_irq);
829 break;
830 case IRQ_PORTG_INTA:
831 set_irq_chained_handler(irq,
832 bfin_demux_gpio_irq);
833 break;
834 case IRQ_PORTH_INTA:
835 set_irq_chained_handler(irq,
836 bfin_demux_gpio_irq);
837 break;
838#endif
819#endif 839#endif
820 default: 840 default:
821 set_irq_handler(irq, handle_simple_irq); 841 set_irq_handler(irq, handle_simple_irq);
@@ -880,14 +900,15 @@ void do_irq(int vec, struct pt_regs *fp)
880 } else { 900 } else {
881 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 901 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
882 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 902 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
883#ifdef CONFIG_BF54x 903#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
884 unsigned long sic_status[3]; 904 unsigned long sic_status[3];
885 905
886 SSYNC(); 906 SSYNC();
887 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); 907 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
888 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); 908 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
909#ifdef CONFIG_BF54x
889 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); 910 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
890 911#endif
891 for (;; ivg++) { 912 for (;; ivg++) {
892 if (ivg >= ivg_stop) { 913 if (ivg >= ivg_stop) {
893 atomic_inc(&num_spurious); 914 atomic_inc(&num_spurious);