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Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/blackfin.h')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h15
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 6c7dc58c018c..891cb599aa63 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -35,19 +35,4 @@
35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) 35#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) 36#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
37 37
38#define BFIN_UART_NR_PORTS 1
39
40#define OFFSET_THR 0x00 /* Transmit Holding register */
41#define OFFSET_RBR 0x00 /* Receive Buffer register */
42#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
43#define OFFSET_IER 0x04 /* Interrupt Enable Register */
44#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
45#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
46#define OFFSET_LCR 0x0C /* Line Control Register */
47#define OFFSET_MCR 0x10 /* Modem Control Register */
48#define OFFSET_LSR 0x14 /* Line Status Register */
49#define OFFSET_MSR 0x18 /* Modem Status Register */
50#define OFFSET_SCR 0x1C /* SCR Scratch Register */
51#define OFFSET_GCTL 0x24 /* Global Control Register */
52
53#endif /* _MACH_BLACKFIN_H_ */ 38#endif /* _MACH_BLACKFIN_H_ */