diff options
Diffstat (limited to 'arch/blackfin/mach-bf538/include/mach/defBF539.h')
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/defBF539.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index d7061d9f2a83..b674a1c4aef1 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h | |||
| @@ -442,15 +442,15 @@ | |||
| 442 | /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ | 442 | /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ |
| 443 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | 443 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ |
| 444 | #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ | 444 | #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ |
| 445 | #define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ | 445 | #define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ |
| 446 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | 446 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ |
| 447 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | 447 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ |
| 448 | #define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */ | 448 | #define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ |
| 449 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | 449 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ |
| 450 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | 450 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ |
| 451 | #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ | 451 | #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ |
| 452 | #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ | 452 | #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ |
| 453 | #define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */ | 453 | #define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ |
| 454 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | 454 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ |
| 455 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | 455 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ |
| 456 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | 456 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ |
| @@ -761,15 +761,15 @@ | |||
| 761 | /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ | 761 | /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ |
| 762 | #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ | 762 | #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ |
| 763 | #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ | 763 | #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ |
| 764 | #define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ | 764 | #define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ |
| 765 | #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ | 765 | #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ |
| 766 | #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ | 766 | #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ |
| 767 | #define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */ | 767 | #define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ |
| 768 | #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ | 768 | #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ |
| 769 | #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ | 769 | #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ |
| 770 | #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ | 770 | #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ |
| 771 | #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ | 771 | #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ |
| 772 | #define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */ | 772 | #define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ |
| 773 | #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ | 773 | #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ |
| 774 | #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ | 774 | #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ |
| 775 | #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ | 775 | #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ |
| @@ -2401,7 +2401,7 @@ | |||
| 2401 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | 2401 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ |
| 2402 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | 2402 | #define RCVSERV 0x0080 /* Receive FIFO Service */ |
| 2403 | 2403 | ||
| 2404 | /* TWIx_FIFO_CTRL Masks */ | 2404 | /* TWIx_FIFO_CTL Masks */ |
| 2405 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | 2405 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ |
| 2406 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | 2406 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ |
| 2407 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | 2407 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ |