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-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c27
-rw-r--r--arch/blackfin/mach-bf537/head.S4
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h163
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bf537.h141
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h195
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_sir.h142
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h165
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF534.h1819
-rw-r--r--arch/blackfin/mach-bf537/include/mach/cdefBF537.h206
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h2527
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF537.h405
-rw-r--r--arch/blackfin/mach-bf537/include/mach/dma.h55
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h214
-rw-r--r--arch/blackfin/mach-bf537/include/mach/mem_init.h303
-rw-r--r--arch/blackfin/mach-bf537/include/mach/mem_map.h179
-rw-r--r--arch/blackfin/mach-bf537/include/mach/portmux.h144
16 files changed, 6686 insertions, 3 deletions
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index e93964fdb432..8482d22321f3 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -584,6 +584,30 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
584 584
585#if defined(CONFIG_MTD_DATAFLASH) \ 585#if defined(CONFIG_MTD_DATAFLASH) \
586 || defined(CONFIG_MTD_DATAFLASH_MODULE) 586 || defined(CONFIG_MTD_DATAFLASH_MODULE)
587
588static struct mtd_partition bfin_spi_dataflash_partitions[] = {
589 {
590 .name = "bootloader(spi)",
591 .size = 0x00040000,
592 .offset = 0,
593 .mask_flags = MTD_CAP_ROM
594 }, {
595 .name = "linux kernel(spi)",
596 .size = 0xe0000,
597 .offset = MTDPART_OFS_APPEND,
598 }, {
599 .name = "file system(spi)",
600 .size = MTDPART_SIZ_FULL,
601 .offset = MTDPART_OFS_APPEND,
602 }
603};
604
605static struct flash_platform_data bfin_spi_dataflash_data = {
606 .name = "SPI Dataflash",
607 .parts = bfin_spi_dataflash_partitions,
608 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
609};
610
587/* DataFlash chip */ 611/* DataFlash chip */
588static struct bfin5xx_spi_chip data_flash_chip_info = { 612static struct bfin5xx_spi_chip data_flash_chip_info = {
589 .enable_dma = 0, /* use dma transfer with this chip*/ 613 .enable_dma = 0, /* use dma transfer with this chip*/
@@ -609,9 +633,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
609 || defined(CONFIG_MTD_DATAFLASH_MODULE) 633 || defined(CONFIG_MTD_DATAFLASH_MODULE)
610 { /* DataFlash chip */ 634 { /* DataFlash chip */
611 .modalias = "mtd_dataflash", 635 .modalias = "mtd_dataflash",
612 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 636 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
613 .bus_num = 0, /* Framework bus number */ 637 .bus_num = 0, /* Framework bus number */
614 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ 638 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
639 .platform_data = &bfin_spi_dataflash_data,
615 .controller_data = &data_flash_chip_info, 640 .controller_data = &data_flash_chip_info,
616 .mode = SPI_MODE_3, 641 .mode = SPI_MODE_3,
617 }, 642 },
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 64e0287ab266..12eb5cc571d0 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -31,8 +31,8 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach-common/clocks.h> 34#include <asm/clocks.h>
35#include <asm/mach/mem_init.h> 35#include <mach/mem_init.h>
36#endif 36#endif
37 37
38.section .l1.text 38.section .l1.text
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
new file mode 100644
index 000000000000..8460ab9c324f
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -0,0 +1,163 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.1 silicon - sorry */
17#if __SILICON_REVISION__ < 2
18# error will not work on BF537 silicon version 0.0 or 0.1
19#endif
20
21#if defined(__ADSPBF534__)
22# define ANOMALY_BF534 1
23#else
24# define ANOMALY_BF534 0
25#endif
26#if defined(__ADSPBF536__)
27# define ANOMALY_BF536 1
28#else
29# define ANOMALY_BF536 0
30#endif
31#if defined(__ADSPBF537__)
32# define ANOMALY_BF537 1
33#else
34# define ANOMALY_BF537 0
35#endif
36
37/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
38#define ANOMALY_05000074 (1)
39/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
40#define ANOMALY_05000119 (1)
41/* Rx.H cannot be used to access 16-bit System MMR registers */
42#define ANOMALY_05000122 (1)
43/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
45/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
46#define ANOMALY_05000167 (1)
47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
48#define ANOMALY_05000180 (1)
49/* Instruction Cache Is Not Functional */
50#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
51/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
52#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
53/* Spurious Hardware Error from an access in the shadow of a conditional branch */
54#define ANOMALY_05000245 (1)
55/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
56#define ANOMALY_05000247 (1)
57/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
58#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
59/* EMAC Tx DMA error after an early frame abort */
60#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
61/* Maximum external clock speed for Timers */
62#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
63/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
64#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
65/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
66#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
67/* EMAC MDIO input latched on wrong MDC edge */
68#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
69/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
70#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
71/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
72#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
73/* ICPLB_STATUS MMR register may be corrupted */
74#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
75/* DCPLB_FAULT_ADDR MMR register may be corrupted */
76#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
77/* Stores to data cache may be lost */
78#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
79/* Hardware loop corrupted when taking an ICPLB exception */
80#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
81/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
82#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
83/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
84#define ANOMALY_05000265 (1)
85/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
86#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
87/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
88#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
89/* Certain data cache write through modes fail for VDDint <=0.9V */
90#define ANOMALY_05000272 (1)
91/* Writes to Synchronous SDRAM memory may be lost */
92#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
93/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
94#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
95/* Disabling Peripherals with DMA running may cause DMA system instability */
96#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
97/* SPI Master boot mode does not work well with Atmel Data flash devices */
98#define ANOMALY_05000280 (1)
99/* False Hardware Error Exception when ISR context is not restored */
100#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
101/* Memory DMA corruption with 32-bit data and traffic control */
102#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
103/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
104#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
105/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
106#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
107/* SPORTs may receive bad data if FIFOs fill up */
108#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
109/* Memory to memory DMA source/destination descriptors must be in same memory space */
110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
117/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
118#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
119/* False hardware errors caused by fetches at the boundary of reserved memory */
120#define ANOMALY_05000310 (1)
121/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
122#define ANOMALY_05000312 (1)
123/* PPI is level sensitive on first transfer */
124#define ANOMALY_05000313 (1)
125/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
126#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
127/* EMAC RMII mode: collisions occur in Full Duplex mode */
128#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
132#define ANOMALY_05000322 (1)
133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
135/* New Feature: UART Remains Enabled after UART Boot */
136#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
137/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
138#define ANOMALY_05000355 (1)
139/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
140#define ANOMALY_05000357 (1)
141/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
142#define ANOMALY_05000359 (1)
143/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
144#define ANOMALY_05000366 (1)
145/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
146#define ANOMALY_05000371 (1)
147/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
148#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
149/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
150#define ANOMALY_05000403 (1)
151
152/* Anomalies that don't exist on this proc */
153#define ANOMALY_05000125 (0)
154#define ANOMALY_05000158 (0)
155#define ANOMALY_05000183 (0)
156#define ANOMALY_05000198 (0)
157#define ANOMALY_05000230 (0)
158#define ANOMALY_05000266 (0)
159#define ANOMALY_05000311 (0)
160#define ANOMALY_05000323 (0)
161#define ANOMALY_05000363 (0)
162
163#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
new file mode 100644
index 000000000000..cfe2a221112e
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bf537.h
@@ -0,0 +1,141 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/bf537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF537_H__
31#define __MACH_BF537_H__
32
33#define SUPPORTED_REVID 2
34
35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
36
37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
38#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
39#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
42#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
43#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44
45#define OFFSET_(x) ((x) & 0x0000FFFF)
46
47/*some misc defines*/
48#define IMASK_IVG15 0x8000
49#define IMASK_IVG14 0x4000
50#define IMASK_IVG13 0x2000
51#define IMASK_IVG12 0x1000
52
53#define IMASK_IVG11 0x0800
54#define IMASK_IVG10 0x0400
55#define IMASK_IVG9 0x0200
56#define IMASK_IVG8 0x0100
57
58#define IMASK_IVG7 0x0080
59#define IMASK_IVGTMR 0x0040
60#define IMASK_IVGHW 0x0020
61
62/***************************/
63
64
65#define BFIN_DSUBBANKS 4
66#define BFIN_DWAYS 2
67#define BFIN_DLINES 64
68#define BFIN_ISUBBANKS 4
69#define BFIN_IWAYS 4
70#define BFIN_ILINES 32
71
72#define WAY0_L 0x1
73#define WAY1_L 0x2
74#define WAY01_L 0x3
75#define WAY2_L 0x4
76#define WAY02_L 0x5
77#define WAY12_L 0x6
78#define WAY012_L 0x7
79
80#define WAY3_L 0x8
81#define WAY03_L 0x9
82#define WAY13_L 0xA
83#define WAY013_L 0xB
84
85#define WAY32_L 0xC
86#define WAY320_L 0xD
87#define WAY321_L 0xE
88#define WAYALL_L 0xF
89
90#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
91
92/********************************* EBIU Settings ************************************/
93#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
94#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
95
96#ifdef CONFIG_C_AMBEN_ALL
97#define V_AMBEN AMBEN_ALL
98#endif
99#ifdef CONFIG_C_AMBEN
100#define V_AMBEN 0x0
101#endif
102#ifdef CONFIG_C_AMBEN_B0
103#define V_AMBEN AMBEN_B0
104#endif
105#ifdef CONFIG_C_AMBEN_B0_B1
106#define V_AMBEN AMBEN_B0_B1
107#endif
108#ifdef CONFIG_C_AMBEN_B0_B1_B2
109#define V_AMBEN AMBEN_B0_B1_B2
110#endif
111#ifdef CONFIG_C_AMCKEN
112#define V_AMCKEN AMCKEN
113#else
114#define V_AMCKEN 0x0
115#endif
116#ifdef CONFIG_C_CDPRIO
117#define V_CDPRIO 0x100
118#else
119#define V_CDPRIO 0x0
120#endif
121
122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
123
124#ifdef CONFIG_BF537
125#define CPU "BF537"
126#define CPUID 0x027c8000
127#endif
128#ifdef CONFIG_BF536
129#define CPU "BF536"
130#define CPUID 0x027c8000
131#endif
132#ifdef CONFIG_BF534
133#define CPU "BF534"
134#define CPUID 0x027c6000
135#endif
136#ifndef CPU
137#define CPU "UNKNOWN"
138#define CPUID 0x0
139#endif
140
141#endif /* __MACH_BF537_H__ */
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..1bf56ffa22f9
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,195 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver header files
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61
62#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
63# define CONFIG_SERIAL_BFIN_CTSRTS
64
65# ifndef CONFIG_UART0_CTS_PIN
66# define CONFIG_UART0_CTS_PIN -1
67# endif
68
69# ifndef CONFIG_UART0_RTS_PIN
70# define CONFIG_UART0_RTS_PIN -1
71# endif
72
73# ifndef CONFIG_UART1_CTS_PIN
74# define CONFIG_UART1_CTS_PIN -1
75# endif
76
77# ifndef CONFIG_UART1_RTS_PIN
78# define CONFIG_UART1_RTS_PIN -1
79# endif
80#endif
81/*
82 * The pin configuration is different from schematic
83 */
84struct bfin_serial_port {
85 struct uart_port port;
86 unsigned int old_status;
87 unsigned int lsr;
88#ifdef CONFIG_SERIAL_BFIN_DMA
89 int tx_done;
90 int tx_count;
91 struct circ_buf rx_dma_buf;
92 struct timer_list rx_dma_timer;
93 int rx_dma_nrows;
94 unsigned int tx_dma_channel;
95 unsigned int rx_dma_channel;
96 struct work_struct tx_dma_workqueue;
97#endif
98#ifdef CONFIG_SERIAL_BFIN_CTSRTS
99 struct timer_list cts_timer;
100 int cts_pin;
101 int rts_pin;
102#endif
103};
104
105/* The hardware clears the LSR bits upon read, so we need to cache
106 * some of the more fun bits in software so they don't get lost
107 * when checking the LSR in other code paths (TX).
108 */
109static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
110{
111 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
112 uart->lsr |= (lsr & (BI|FE|PE|OE));
113 return lsr | uart->lsr;
114}
115
116static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
117{
118 uart->lsr = 0;
119 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
120}
121
122struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
123struct bfin_serial_res {
124 unsigned long uart_base_addr;
125 int uart_irq;
126#ifdef CONFIG_SERIAL_BFIN_DMA
127 unsigned int uart_tx_dma_channel;
128 unsigned int uart_rx_dma_channel;
129#endif
130#ifdef CONFIG_SERIAL_BFIN_CTSRTS
131 int uart_cts_pin;
132 int uart_rts_pin;
133#endif
134};
135
136struct bfin_serial_res bfin_serial_resource[] = {
137#ifdef CONFIG_SERIAL_BFIN_UART0
138 {
139 0xFFC00400,
140 IRQ_UART0_RX,
141#ifdef CONFIG_SERIAL_BFIN_DMA
142 CH_UART0_TX,
143 CH_UART0_RX,
144#endif
145#ifdef CONFIG_BFIN_UART0_CTSRTS
146 CONFIG_UART0_CTS_PIN,
147 CONFIG_UART0_RTS_PIN,
148#endif
149 },
150#endif
151#ifdef CONFIG_SERIAL_BFIN_UART1
152 {
153 0xFFC02000,
154 IRQ_UART1_RX,
155#ifdef CONFIG_SERIAL_BFIN_DMA
156 CH_UART1_TX,
157 CH_UART1_RX,
158#endif
159#ifdef CONFIG_BFIN_UART1_CTSRTS
160 CONFIG_UART1_CTS_PIN,
161 CONFIG_UART1_RTS_PIN,
162#endif
163 },
164#endif
165};
166
167int nr_ports = ARRAY_SIZE(bfin_serial_resource);
168
169#define DRIVER_NAME "bfin-uart"
170
171static void bfin_serial_hw_init(struct bfin_serial_port *uart)
172{
173
174#ifdef CONFIG_SERIAL_BFIN_UART0
175 peripheral_request(P_UART0_TX, DRIVER_NAME);
176 peripheral_request(P_UART0_RX, DRIVER_NAME);
177#endif
178
179#ifdef CONFIG_SERIAL_BFIN_UART1
180 peripheral_request(P_UART1_TX, DRIVER_NAME);
181 peripheral_request(P_UART1_RX, DRIVER_NAME);
182#endif
183
184#ifdef CONFIG_SERIAL_BFIN_CTSRTS
185 if (uart->cts_pin >= 0) {
186 gpio_request(uart->cts_pin, DRIVER_NAME);
187 gpio_direction_input(uart->cts_pin);
188 }
189
190 if (uart->rts_pin >= 0) {
191 gpio_request(uart->rts_pin, DRIVER_NAME);
192 gpio_direction_output(uart->rts_pin, 0);
193 }
194#endif
195}
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_sir.h b/arch/blackfin/mach-bf537/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..cfd8ad4f1f2c
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_sir.h
@@ -0,0 +1,142 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART0_RX,
69 CH_UART0_RX,
70 CH_UART0_TX,
71 },
72#endif
73#ifdef CONFIG_BFIN_SIR1
74 {
75 0xFFC02000,
76 IRQ_UART1_RX,
77 CH_UART1_RX,
78 CH_UART1_TX,
79 },
80#endif
81};
82
83int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
84
85struct bfin_sir_self {
86 struct bfin_sir_port *sir_port;
87 spinlock_t lock;
88 unsigned int open;
89 int speed;
90 int newspeed;
91
92 struct sk_buff *txskb;
93 struct sk_buff *rxskb;
94 struct net_device_stats stats;
95 struct device *dev;
96 struct irlap_cb *irlap;
97 struct qos_info qos;
98
99 iobuff_t tx_buff;
100 iobuff_t rx_buff;
101
102 struct work_struct work;
103 int mtt;
104};
105
106static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
107{
108 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
109 port->lsr |= (lsr & (BI|FE|PE|OE));
110 return lsr | port->lsr;
111}
112
113static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
114{
115 port->lsr = 0;
116 bfin_read16(port->membase + OFFSET_LSR);
117}
118
119#define DRIVER_NAME "bfin_sir"
120
121static int bfin_sir_hw_init(void)
122{
123 int ret = -ENODEV;
124#ifdef CONFIG_BFIN_SIR0
125 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
126 if (ret)
127 return ret;
128 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
129 if (ret)
130 return ret;
131#endif
132
133#ifdef CONFIG_BFIN_SIR1
134 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
135 if (ret)
136 return ret;
137 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
138 if (ret)
139 return ret;
140#endif
141 return ret;
142}
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
new file mode 100644
index 000000000000..cffc786b2a2b
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -0,0 +1,165 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF537_FAMILY
36
37#include "bf537.h"
38#include "mem_map.h"
39#include "defBF534.h"
40#include "anomaly.h"
41
42#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
43#include "defBF537.h"
44#endif
45
46#if !defined(__ASSEMBLY__)
47#include "cdefBF534.h"
48
49/* UART 0*/
50#define bfin_read_UART_THR() bfin_read_UART0_THR()
51#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
52#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
53#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
54#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
55#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
56#define bfin_read_UART_IER() bfin_read_UART0_IER()
57#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
58#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
59#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
60#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
61#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
62#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
63#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
64#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
65#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
66#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
67#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
68#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
69#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
70#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
71#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
72
73#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
74#include "cdefBF537.h"
75#endif
76#endif
77
78/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
79
80/* UART_IIR Register */
81#define STATUS(x) ((x << 1) & 0x06)
82#define STATUS_P1 0x02
83#define STATUS_P0 0x01
84
85/* DMA Channnel */
86#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
87#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
88#define CH_UART_RX CH_UART0_RX
89#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
90#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
91#define CH_UART_TX CH_UART0_TX
92
93/* System Interrupt Controller */
94#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
95#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
96#define IRQ_UART_RX IRQ_UART0_RX
97#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
98#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
99#define IRQ_UART_TX IRQ_UART0_TX
100#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
101#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
102#define IRQ_UART_ERROR IRQ_UART0_ERROR
103
104/* MMR Registers*/
105#define bfin_read_UART_THR() bfin_read_UART0_THR()
106#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
107#define BFIN_UART_THR UART0_THR
108#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
109#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
110#define BFIN_UART_RBR UART0_RBR
111#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
112#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
113#define BFIN_UART_DLL UART0_DLL
114#define bfin_read_UART_IER() bfin_read_UART0_IER()
115#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
116#define BFIN_UART_IER UART0_IER
117#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
118#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
119#define BFIN_UART_DLH UART0_DLH
120#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
121#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
122#define BFIN_UART_IIR UART0_IIR
123#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
124#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
125#define BFIN_UART_LCR UART0_LCR
126#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
127#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
128#define BFIN_UART_MCR UART0_MCR
129#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
130#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
131#define BFIN_UART_LSR UART0_LSR
132#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
133#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
134#define BFIN_UART_SCR UART0_SCR
135#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
136#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
137#define BFIN_UART_GCTL UART0_GCTL
138
139#define BFIN_UART_NR_PORTS 2
140
141#define OFFSET_THR 0x00 /* Transmit Holding register */
142#define OFFSET_RBR 0x00 /* Receive Buffer register */
143#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
144#define OFFSET_IER 0x04 /* Interrupt Enable Register */
145#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
146#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
147#define OFFSET_LCR 0x0C /* Line Control Register */
148#define OFFSET_MCR 0x10 /* Modem Control Register */
149#define OFFSET_LSR 0x14 /* Line Status Register */
150#define OFFSET_MSR 0x18 /* Modem Status Register */
151#define OFFSET_SCR 0x1C /* SCR Scratch Register */
152#define OFFSET_GCTL 0x24 /* Global Control Register */
153
154/* DPMC*/
155#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
156#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
157#define STOPCK_OFF STOPCK
158
159/* PLL_DIV Masks */
160#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
161#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
162#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
163#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
164
165#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
new file mode 100644
index 000000000000..88d491cd9f36
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -0,0 +1,1819 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefbf534.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF534_H
33#define _CDEF_BF534_H
34
35#include <asm/blackfin.h>
36
37/* Include all Core registers and bit definitions */
38#include "defBF534.h"
39
40/* Include core specific register pointer definitions */
41#include <asm/cdef_LPBlackfin.h>
42
43#include <asm/system.h>
44
45/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
46#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
47/* Writing to PLL_CTL initiates a PLL relock sequence. */
48static __inline__ void bfin_write_PLL_CTL(unsigned int val)
49{
50 unsigned long flags, iwr;
51
52 if (val == bfin_read_PLL_CTL())
53 return;
54
55 local_irq_save(flags);
56 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR, IWR_ENABLE(0));
60
61 bfin_write16(PLL_CTL, val);
62 SSYNC();
63 asm("IDLE;");
64
65 bfin_write32(SIC_IWR, iwr);
66 local_irq_restore(flags);
67}
68#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
69#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
70#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
71/* Writing to VR_CTL initiates a PLL relock sequence. */
72static __inline__ void bfin_write_VR_CTL(unsigned int val)
73{
74 unsigned long flags, iwr;
75
76 if (val == bfin_read_VR_CTL())
77 return;
78
79 local_irq_save(flags);
80 /* Enable the PLL Wakeup bit in SIC IWR */
81 iwr = bfin_read32(SIC_IWR);
82 /* Only allow PPL Wakeup) */
83 bfin_write32(SIC_IWR, IWR_ENABLE(0));
84
85 bfin_write16(VR_CTL, val);
86 SSYNC();
87 asm("IDLE;");
88
89 bfin_write32(SIC_IWR, iwr);
90 local_irq_restore(flags);
91}
92#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
93#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
94#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
95#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
96#define bfin_read_CHIPID() bfin_read32(CHIPID)
97
98/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
99#define bfin_read_SWRST() bfin_read16(SWRST)
100#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
101#define bfin_read_SYSCR() bfin_read16(SYSCR)
102#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
103#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
104#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
105#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
106#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
107#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
108#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
109#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
110#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
111#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
112#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
113#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
114#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
115#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
116#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
117#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
118#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
119
120/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
121#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
122#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
123#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
124#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
125#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
126#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
127
128/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
129#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
130#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
131#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
132#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
133#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
134#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
135#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
136#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
137#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
138#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
139#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
140#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
141#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
142#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
143
144/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
145#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
146#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
147#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
148#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
149#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
150#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
151#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
152#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
153#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
154#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
155#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
156#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
157#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
158#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
159#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
160#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
161#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
162#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
163#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
164#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
165#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
166#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
167#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
168#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
169
170/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
171#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
172#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
173#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
174#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
175#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
176#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
177#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
178#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
179#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
180#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
181#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
182#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
183#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
184#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
185
186/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
187#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
188#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
189#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
190#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
191#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
192#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
193#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
194#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
195
196#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
197#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
198#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
199#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
200#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
201#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
202#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
203#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
204
205#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
206#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
207#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
208#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
209#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
210#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
211#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
212#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
213
214#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
215#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
216#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
217#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
218#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
219#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
220#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
221#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
222
223#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
224#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
225#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
226#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
227#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
228#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
229#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
230#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
231
232#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
233#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
234#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
235#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
236#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
237#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
238#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
239#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
240
241#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
242#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
243#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
244#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
245#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
246#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
247#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
248#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
249
250#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
251#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
252#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
253#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
254#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
255#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
256#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
257#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
258
259#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
260#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
261#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
262#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
263#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
264#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
265
266/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
267#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
268#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
269#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
270#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
271#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
272#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
273#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
274#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
275#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
276#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
277#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
278#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
279#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
280#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
281#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
282#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
283#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
284#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
285#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
286#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
287#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
288#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
289#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
290#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
291#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
292#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
293#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
294#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
295#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
296#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
297#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
298#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
299#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
300#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
301
302/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
303#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
304#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
305#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
306#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
307#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
308#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
309#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
310#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
311#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
312#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
313#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
314#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
315#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
316#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
317#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
318#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
319#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
320#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
321#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
322#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
323#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
324#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
325#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
326#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
327#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
328#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
329#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
330#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
331#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
332#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
333#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
334#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
335#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
336#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
337#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
338#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
339#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
340#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
341#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
342#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
343#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
344#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
345#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
346#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
347#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
348#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
349#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
350#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
351#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
352#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
353#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
354#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
355
356/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
357#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
358#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
359#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
360#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
361#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
362#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
363#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
364#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
365#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
366#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
367#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
368#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
369#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
370#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
371#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
372#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
373#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
374#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
375#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
376#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
377#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
378#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
379#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
380#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
381#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
382#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
383#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
384#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
385#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
386#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
387#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
388#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
389#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
390#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
391#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
392#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
393#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
394#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
395#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
396#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
397#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
398#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
399#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
400#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
401#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
402#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
403#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
404#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
405#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
406#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
407#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
408#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
409
410/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
411#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
412#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
413#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
414#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
415#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
416#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
417#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
418#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
419#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
420#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
421#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
422#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
423#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
424#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
425
426/* DMA Traffic Control Registers */
427#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
428#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
429#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
430#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
431
432/* Alternate deprecated register names (below) provided for backwards code compatibility */
433#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
434#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
435#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
436#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
437
438/* DMA Controller */
439#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
440#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
441#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
442#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
443#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
444#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
445#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
446#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
447#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
448#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
449#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
450#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
451#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
452#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
453#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
454#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
455#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
456#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
457#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
458#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
459#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
460#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
461#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
462#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
463#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
464#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
465
466#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
467#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
468#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
469#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
470#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
471#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
472#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
473#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
474#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
475#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
476#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
477#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
478#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
479#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
480#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
481#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
482#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
483#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
484#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
485#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
486#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
487#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
488#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
489#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
490#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
491#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
492
493#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
494#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
495#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
496#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
497#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
498#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
499#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
500#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
501#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
502#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
503#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
504#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
505#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
506#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
507#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
508#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
509#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
510#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
511#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
512#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
513#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
514#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
515#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
516#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
517#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
518#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
519
520#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
521#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
522#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
523#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
524#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
525#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
526#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
527#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
528#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
529#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
530#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
531#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
532#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
533#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
534#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
535#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
536#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
537#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
538#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
539#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
540#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
541#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
542#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
543#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
544#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
545#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
546
547#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
548#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
549#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
550#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
551#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
552#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
553#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
554#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
555#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
556#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
557#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
558#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
559#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
560#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
561#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
562#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
563#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
564#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
565#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
566#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
567#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
568#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
569#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
570#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
571#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
572#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
573
574#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
575#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
576#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
577#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
578#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
579#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
580#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
581#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
582#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
583#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
584#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
585#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
586#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
587#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
588#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
589#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
590#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
591#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
592#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
593#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
594#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
595#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
596#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
597#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
598#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
599#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
600
601#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
602#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
603#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
604#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
605#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
606#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
607#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
608#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
609#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
610#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
611#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
612#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
613#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
614#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
615#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
616#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
617#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
618#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
619#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
620#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
621#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
622#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
623#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
624#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
625#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
626#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
627
628#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
629#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
630#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
631#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
632#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
633#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
634#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
635#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
636#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
637#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
638#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
639#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
640#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
641#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
642#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
643#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
644#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
645#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
646#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
647#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
648#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
649#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
650#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
651#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
652#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
653#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
654
655#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
656#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
657#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
658#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
659#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
660#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
661#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
662#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
663#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
664#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
665#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
666#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
667#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
668#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
669#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
670#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
671#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
672#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
673#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
674#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
675#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
676#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
677#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
678#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
679#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
680#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
681
682#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
683#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
684#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
685#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
686#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
687#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
688#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
689#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
690#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
691#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
692#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
693#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
694#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
695#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
696#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
697#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
698#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
699#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
700#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
701#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
702#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
703#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
704#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
705#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
706#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
707#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
708
709#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
710#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
711#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
712#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
713#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
714#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
715#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
716#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
717#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
718#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
719#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
720#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
721#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
722#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
723#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
724#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
725#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
726#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
727#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
728#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
729#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
730#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
731#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
732#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
733#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
734#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
735
736#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
737#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
738#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
739#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
740#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
741#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
742#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
743#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
744#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
745#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
746#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
747#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
748#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
749#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
750#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
751#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
752#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
753#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
754#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
755#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
756#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
757#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
758#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
759#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
760#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
761#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
762
763#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
764#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
765#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
766#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
767#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
768#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
769#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
770#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
771#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
772#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
773#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
774#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
775#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
776#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
777#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
778#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
779#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
780#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
781#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
782#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
783#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
784#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
785#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
786#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
787#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
788#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
789
790#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
791#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
792#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
793#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
794#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
795#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
796#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
797#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
798#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
799#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
800#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
801#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
802#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
803#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
804#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
805#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
806#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
807#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
808#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
809#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
810#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
811#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
812#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
813#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
814#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
815#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
816
817#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
818#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
819#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
820#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
821#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
822#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
823#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
824#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
825#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
826#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
827#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
828#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
829#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
830#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
831#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
832#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
833#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
834#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
835#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
836#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
837#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
838#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
839#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
840#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
841#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
842#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
843
844#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
845#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
846#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
847#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
848#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
849#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
850#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
851#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
852#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
853#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
854#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
855#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
856#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
857#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
858#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
859#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
860#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
861#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
862#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
863#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
864#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
865#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
866#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
867#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
868#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
869#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
870
871/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
872#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
873#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
874#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
875#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
876#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
877#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
878#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
879#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
880#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
881#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
882#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
883
884/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
885
886/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
887#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
888#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
889#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
890#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
891#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
892#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
893#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
894#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
895#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
896#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
897#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
898#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
899#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
900#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
901#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
902#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
903#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
904#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
905#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
906#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
907#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
908#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
909#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
910#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
911#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
912#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
913#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
914#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
915#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
916#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
917#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
918#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
919#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
920#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
921
922/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
923#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
924#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
925#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
926#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
927#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
928#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
929#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
930#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
931#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
932#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
933#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
934#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
935#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
936#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
937#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
938#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
939#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
940#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
941#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
942#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
943#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
944#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
945#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
946#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
947#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
948#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
949#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
950#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
951#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
952#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
953#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
954#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
955#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
956#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
957
958/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
959#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
960#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
961#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
962#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
963#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
964#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
965#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
966#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
967#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
968#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
969#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
970#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
971#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
972#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
973#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
974#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
975#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
976#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
977#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
978#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
979#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
980#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
981#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
982#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
983
984/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
985/* For Mailboxes 0-15 */
986#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
987#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
988#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
989#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
990#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
991#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
992#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
993#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
994#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
995#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
996#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
997#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
998#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
999#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
1000#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
1001#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
1002#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
1003#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
1004#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
1005#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
1006#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
1007#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
1008#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
1009#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
1010#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
1011#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
1012
1013/* For Mailboxes 16-31 */
1014#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
1015#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
1016#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
1017#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
1018#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
1019#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
1020#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
1021#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
1022#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
1023#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
1024#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
1025#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
1026#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
1027#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
1028#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
1029#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
1030#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
1031#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
1032#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
1033#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
1034#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
1035#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
1036#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
1037#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
1038#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
1039#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
1040
1041#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
1042#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
1043#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
1044#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
1045#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
1046#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
1047#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
1048#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
1049#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
1050#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
1051#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
1052#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
1053#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
1054#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
1055#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
1056#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
1057#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
1058#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
1059#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
1060#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
1061#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER)
1062#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
1063#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
1064#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
1065#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
1066#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
1067#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
1068#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
1069#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
1070#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
1071#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
1072#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
1073#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
1074#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
1075#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
1076#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
1077
1078/* Mailbox Acceptance Masks */
1079#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
1080#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
1081#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
1082#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
1083#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
1084#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
1085#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
1086#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
1087#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
1088#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
1089#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
1090#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
1091#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
1092#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
1093#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
1094#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
1095#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
1096#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
1097#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
1098#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
1099#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
1100#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
1101#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
1102#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
1103#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
1104#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
1105#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
1106#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
1107#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
1108#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
1109#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
1110#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
1111#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
1112#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
1113#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
1114#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
1115#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
1116#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
1117#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
1118#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
1119#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
1120#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
1121#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
1122#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
1123#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
1124#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
1125#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
1126#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
1127#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
1128#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
1129#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
1130#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
1131#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
1132#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
1133#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
1134#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
1135#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
1136#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
1137#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
1138#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
1139#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
1140#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
1141#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
1142#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
1143
1144#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
1145#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
1146#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
1147#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
1148#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
1149#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
1150#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
1151#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
1152#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
1153#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
1154#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
1155#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
1156#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
1157#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
1158#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
1159#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
1160#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
1161#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
1162#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
1163#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
1164#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
1165#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
1166#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
1167#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
1168#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
1169#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
1170#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
1171#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
1172#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
1173#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
1174#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
1175#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
1176#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
1177#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
1178#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
1179#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
1180#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
1181#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
1182#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
1183#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
1184#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
1185#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
1186#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
1187#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
1188#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
1189#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
1190#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
1191#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
1192#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
1193#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
1194#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
1195#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
1196#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
1197#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
1198#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
1199#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
1200#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
1201#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
1202#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
1203#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
1204#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
1205#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
1206#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
1207#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
1208
1209/* CAN Acceptance Mask Area Macros */
1210#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x))
1211#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
1212#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x))
1213#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
1214
1215/* Mailbox Registers */
1216#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
1217#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
1218#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
1219#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
1220#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
1221#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
1222#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
1223#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
1224#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
1225#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
1226#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
1227#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
1228#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
1229#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
1230#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
1231#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
1232
1233#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
1234#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
1235#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
1236#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
1237#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
1238#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
1239#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
1240#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
1241#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
1242#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
1243#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
1244#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
1245#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
1246#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
1247#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
1248#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
1249
1250#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
1251#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
1252#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
1253#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
1254#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
1255#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
1256#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
1257#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
1258#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
1259#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
1260#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
1261#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
1262#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
1263#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
1264#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
1265#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
1266
1267#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
1268#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
1269#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
1270#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
1271#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
1272#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
1273#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
1274#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
1275#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
1276#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
1277#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
1278#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
1279#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
1280#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
1281#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
1282#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
1283
1284#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
1285#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
1286#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
1287#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
1288#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
1289#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
1290#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
1291#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
1292#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
1293#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
1294#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
1295#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
1296#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
1297#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
1298#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
1299#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
1300
1301#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
1302#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
1303#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
1304#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
1305#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
1306#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
1307#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
1308#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
1309#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
1310#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
1311#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
1312#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
1313#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
1314#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
1315#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
1316#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
1317
1318#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
1319#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
1320#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
1321#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
1322#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
1323#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
1324#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
1325#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
1326#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
1327#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
1328#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
1329#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
1330#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
1331#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
1332#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
1333#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
1334
1335#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
1336#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
1337#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
1338#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
1339#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
1340#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
1341#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
1342#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
1343#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
1344#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
1345#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
1346#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
1347#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
1348#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
1349#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
1350#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
1351
1352#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
1353#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
1354#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
1355#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
1356#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
1357#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
1358#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
1359#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
1360#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
1361#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
1362#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
1363#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
1364#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
1365#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
1366#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
1367#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
1368
1369#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
1370#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
1371#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
1372#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
1373#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
1374#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
1375#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
1376#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
1377#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
1378#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
1379#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
1380#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
1381#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
1382#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
1383#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
1384#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
1385
1386#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
1387#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
1388#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
1389#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
1390#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
1391#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
1392#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
1393#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
1394#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
1395#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
1396#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
1397#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
1398#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
1399#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
1400#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
1401#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
1402
1403#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
1404#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
1405#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
1406#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
1407#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
1408#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
1409#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
1410#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
1411#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
1412#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
1413#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
1414#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
1415#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
1416#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
1417#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
1418#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
1419
1420#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
1421#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
1422#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
1423#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
1424#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
1425#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
1426#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
1427#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
1428#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
1429#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
1430#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
1431#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
1432#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
1433#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
1434#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
1435#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
1436
1437#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
1438#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
1439#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
1440#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
1441#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
1442#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
1443#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
1444#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
1445#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
1446#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
1447#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
1448#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
1449#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
1450#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
1451#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
1452#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
1453
1454#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
1455#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
1456#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
1457#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
1458#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
1459#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
1460#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
1461#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
1462#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
1463#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
1464#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
1465#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
1466#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
1467#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
1468#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
1469#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
1470
1471#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
1472#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
1473#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
1474#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
1475#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
1476#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
1477#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
1478#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
1479#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
1480#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
1481#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
1482#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
1483#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
1484#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
1485#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
1486#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
1487
1488#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
1489#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
1490#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
1491#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
1492#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
1493#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
1494#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
1495#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
1496#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
1497#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
1498#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
1499#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
1500#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
1501#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
1502#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
1503#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
1504
1505#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
1506#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
1507#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
1508#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
1509#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
1510#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
1511#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
1512#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
1513#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
1514#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
1515#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
1516#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
1517#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
1518#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
1519#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
1520#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
1521
1522#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
1523#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
1524#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
1525#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
1526#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
1527#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
1528#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
1529#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
1530#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
1531#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
1532#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
1533#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
1534#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
1535#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
1536#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
1537#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
1538
1539#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
1540#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
1541#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
1542#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
1543#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
1544#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
1545#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
1546#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
1547#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
1548#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
1549#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
1550#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
1551#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
1552#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
1553#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
1554#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
1555
1556#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
1557#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
1558#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
1559#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
1560#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
1561#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
1562#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
1563#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
1564#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
1565#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
1566#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
1567#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
1568#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
1569#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
1570#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
1571#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
1572
1573#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
1574#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
1575#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
1576#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
1577#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
1578#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
1579#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
1580#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
1581#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
1582#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
1583#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
1584#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
1585#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
1586#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
1587#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
1588#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
1589
1590#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
1591#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
1592#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
1593#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
1594#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
1595#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
1596#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
1597#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
1598#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
1599#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
1600#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
1601#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
1602#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
1603#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
1604#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
1605#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
1606
1607#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
1608#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
1609#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
1610#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
1611#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
1612#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
1613#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
1614#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
1615#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
1616#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
1617#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
1618#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
1619#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
1620#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
1621#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
1622#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
1623
1624#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
1625#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
1626#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
1627#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
1628#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
1629#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
1630#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
1631#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
1632#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
1633#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
1634#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
1635#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
1636#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
1637#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
1638#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
1639#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
1640
1641#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
1642#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
1643#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
1644#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
1645#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
1646#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
1647#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
1648#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
1649#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
1650#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
1651#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
1652#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
1653#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
1654#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
1655#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
1656#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
1657
1658#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
1659#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
1660#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
1661#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
1662#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
1663#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
1664#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
1665#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
1666#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
1667#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
1668#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
1669#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
1670#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
1671#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
1672#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
1673#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
1674
1675#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
1676#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
1677#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
1678#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
1679#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
1680#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
1681#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
1682#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
1683#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
1684#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
1685#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
1686#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
1687#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
1688#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
1689#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
1690#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
1691
1692#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
1693#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
1694#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
1695#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
1696#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
1697#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
1698#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
1699#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
1700#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
1701#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
1702#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
1703#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
1704#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
1705#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
1706#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
1707#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
1708
1709#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
1710#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
1711#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
1712#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
1713#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
1714#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
1715#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
1716#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
1717#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
1718#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
1719#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
1720#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
1721#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
1722#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
1723#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
1724#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
1725
1726#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
1727#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
1728#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
1729#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
1730#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
1731#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
1732#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
1733#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
1734#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
1735#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
1736#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
1737#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
1738#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
1739#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
1740#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
1741#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
1742
1743#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
1744#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
1745#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
1746#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
1747#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
1748#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
1749#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
1750#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
1751#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
1752#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
1753#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
1754#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
1755#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
1756#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
1757#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
1758#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
1759
1760/* CAN Mailbox Area Macros */
1761#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x))
1762#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
1763#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x))
1764#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
1765#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x))
1766#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
1767#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x))
1768#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
1769#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x))
1770#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
1771#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x))
1772#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
1773#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x))
1774#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
1775#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x))
1776#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
1777
1778/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1779#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1780#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
1781#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1782#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
1783#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1784#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
1785#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX)
1786#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
1787
1788/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1789#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1790#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
1791#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1792#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
1793#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1794#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
1795#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1796#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
1797#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1798#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
1799#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1800#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
1801#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1802#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
1803
1804#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1805#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
1806#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1807#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
1808#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1809#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
1810#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1811#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
1812#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1813#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
1814#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1815#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
1816#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1817#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1818
1819#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
new file mode 100644
index 000000000000..b8fc949a991f
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
@@ -0,0 +1,206 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefBF537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 * System MMR Register Map
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF537_H
33#define _CDEF_BF537_H
34
35/* Include MMRs Common to BF534 */
36#include "cdefBF534.h"
37
38/* Include all Core registers and bit definitions */
39#include "defBF537.h"
40
41/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
42/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
43#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
44#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
45#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
46#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
47#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
48#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
49#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
50#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
51#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
52#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
53#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
54#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
55#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
56#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
57#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
58#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
59#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
60#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
61#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
62#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
63#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
64#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
65#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
66#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
67#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
68#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
69#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
70#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
71#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
72#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
73#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
74#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
75#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
76#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
77#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
78#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
79#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
80#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
81
82#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
83#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
84#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
85#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
86#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
87#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
88#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
89#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
90#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
91#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
92#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
93#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
94#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
95#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
96#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
97#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
98
99#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
100#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
101#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
102#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
103#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
104#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
105#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
106#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
107#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
108#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
109
110#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
111#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
112#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
113#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
114#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
115#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
116#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
117#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
118#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
119#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
120#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
121#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
122#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
123#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
124#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
125#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
126#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
127#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
128#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
129#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
130#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
131#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
132#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
133#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
134#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
135#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
136#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
137#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
138#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
139#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
140#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
141#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
142#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
143#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
144#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
145#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
146#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
147#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
148#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
149#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
150#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
151#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
152#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
153#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
154#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
155#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
156#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
157#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
158
159#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
160#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
161#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
162#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
163#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
164#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
165#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
166#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
167#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
168#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
169#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
170#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
171#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
172#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
173#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
174#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
175#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
176#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
177#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
178#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
179#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
180#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
181#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
182#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
183#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
184#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
185#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
186#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
187#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
188#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
189#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
190#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
191#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
192#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
193#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
194#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
195#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
196#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
197#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
198#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
199#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
200#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
201#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
202#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
203#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
204#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
205
206#endif /* _CDEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
new file mode 100644
index 000000000000..a3227f9003ff
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -0,0 +1,2527 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefBF537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF534_H
32#define _DEF_BF534_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/def_LPBlackfin.h>
36
37/************************************************************************************
38** System MMR Register Map
39*************************************************************************************/
40/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
41#define PLL_CTL 0xFFC00000 /* PLL Control Register */
42#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
43#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
44#define PLL_STAT 0xFFC0000C /* PLL Status Register */
45#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
46#define CHIPID 0xFFC00014 /* Chip ID Register */
47
48/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
49#define SWRST 0xFFC00100 /* Software Reset Register */
50#define SYSCR 0xFFC00104 /* System Configuration Register */
51#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
52#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
53#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
54#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
55#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
56#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
57#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
58#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
59
60/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
61#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
62#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
63#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
64
65/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
66#define RTC_STAT 0xFFC00300 /* RTC Status Register */
67#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
68#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
69#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
70#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
71#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
72#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
73
74/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
75#define UART0_THR 0xFFC00400 /* Transmit Holding register */
76#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
77#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
78#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
79#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
80#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
81#define UART0_LCR 0xFFC0040C /* Line Control Register */
82#define UART0_MCR 0xFFC00410 /* Modem Control Register */
83#define UART0_LSR 0xFFC00414 /* Line Status Register */
84#define UART0_MSR 0xFFC00418 /* Modem Status Register */
85#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
86#define UART0_GCTL 0xFFC00424 /* Global Control Register */
87
88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
89#define SPI0_REGBASE 0xFFC00500
90#define SPI_CTL 0xFFC00500 /* SPI Control Register */
91#define SPI_FLG 0xFFC00504 /* SPI Flag register */
92#define SPI_STAT 0xFFC00508 /* SPI Status register */
93#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
94#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
95#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
96#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
97
98/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
99#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
100#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
101#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
102#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
103
104#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
105#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
106#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
107#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
108
109#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
110#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
111#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
112#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
113
114#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
115#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
116#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
117#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
118
119#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
120#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
121#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
122#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
123
124#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
125#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
126#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
127#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
128
129#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
130#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
131#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
132#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
133
134#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
135#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
136#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
137#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
138
139#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
140#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
141#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
142
143/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
144#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
145#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
146#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
147#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
148#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
149#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
150#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
151#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
152#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
153#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
154#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
155#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
156#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
157#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
158#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
159#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
160#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
161
162/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
163#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
164#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
165#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
166#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
167#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
168#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
169#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
170#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
171#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
172#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
173#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
174#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
175#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
176#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
177#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
178#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
179#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
180#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
181#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
182#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
183#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
184#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
185
186/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
187#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
188#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
189#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
190#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
191#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
192#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
193#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
194#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
195#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
196#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
197#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
198#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
199#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
200#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
201#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
202#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
203#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
204#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
205#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
206#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
207#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
208#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
209
210/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
211#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
212#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
213#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
214#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
215#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
216#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
217#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
218
219/* DMA Traffic Control Registers */
220#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
221#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
222
223/* Alternate deprecated register names (below) provided for backwards code compatibility */
224#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
225#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
226
227/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
228#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
229#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
230#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
231#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
232#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
233#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
234#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
235#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
236#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
237#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
238#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
239#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
240#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
241
242#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
243#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
244#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
245#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
246#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
247#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
248#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
249#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
250#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
251#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
252#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
253#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
254#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
255
256#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
257#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
258#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
259#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
260#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
261#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
262#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
263#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
264#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
265#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
266#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
267#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
268#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
269
270#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
271#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
272#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
273#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
274#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
275#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
276#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
277#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
278#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
279#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
280#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
281#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
282#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
283
284#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
285#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
286#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
287#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
288#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
289#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
290#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
291#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
292#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
293#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
294#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
295#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
296#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
297
298#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
299#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
300#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
301#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
302#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
303#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
304#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
305#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
306#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
307#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
308#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
309#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
310#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
311
312#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
313#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
314#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
315#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
316#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
317#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
318#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
319#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
320#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
321#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
322#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
323#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
324#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
325
326#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
327#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
328#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
329#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
330#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
331#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
332#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
333#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
334#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
335#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
336#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
337#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
338#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
339
340#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
341#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
342#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
343#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
344#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
345#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
346#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
347#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
348#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
349#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
350#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
351#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
352#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
353
354#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
355#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
356#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
357#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
358#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
359#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
360#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
361#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
362#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
363#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
364#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
365#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
366#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
367
368#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
369#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
370#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
371#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
372#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
373#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
374#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
375#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
376#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
377#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
378#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
379#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
380#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
381
382#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
383#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
384#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
385#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
386#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
387#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
388#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
389#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
390#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
391#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
392#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
393#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
394#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
395
396#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
397#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
398#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
399#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
400#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
401#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
402#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
403#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
404#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
405#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
406#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
407#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
408#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
409
410#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
411#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
412#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
413#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
414#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
415#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
416#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
417#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
418#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
419#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
420#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
421#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
422#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
423
424#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
425#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
426#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
427#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
428#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
429#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
430#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
431#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
432#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
433#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
434#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
435#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
436#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
437
438#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
439#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
440#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
441#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
442#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
443#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
444#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
445#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
446#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
447#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
448#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
449#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
450#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
451
452/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
453#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
454#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
455#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
456#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
457#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
458
459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400
461#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
462#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
463#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
464#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
465#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
466#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
467#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
468#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
469#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
470#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
471#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
472#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
473#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
474#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
475#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
476#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
477
478/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
479#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
480#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
481#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
482#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
483#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
484#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
485#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
486#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
487#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
488#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
489#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
490#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
491#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
492#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
493#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
494#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
495#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
496
497/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
498#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
499#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
500#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
501#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
502#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
503#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
504#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
505#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
506#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
507#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
508#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
509#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
510#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
511#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
512#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
513#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
514#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
515
516/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
517#define UART1_THR 0xFFC02000 /* Transmit Holding register */
518#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
519#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
520#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
521#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
522#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
523#define UART1_LCR 0xFFC0200C /* Line Control Register */
524#define UART1_MCR 0xFFC02010 /* Modem Control Register */
525#define UART1_LSR 0xFFC02014 /* Line Status Register */
526#define UART1_MSR 0xFFC02018 /* Modem Status Register */
527#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
528#define UART1_GCTL 0xFFC02024 /* Global Control Register */
529
530/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
531/* For Mailboxes 0-15 */
532#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
533#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
534#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
535#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
536#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
537#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
538#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
539#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
540#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
541#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
542#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
543#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
544#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
545
546/* For Mailboxes 16-31 */
547#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
548#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
549#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
550#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
551#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
552#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
553#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
554#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
555#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
556#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
557#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
558#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
559#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
560
561/* CAN Configuration, Control, and Status Registers */
562#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
563#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
564#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
565#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
566#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
567#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
568#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
569#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
570#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
571#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
572
573#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
574#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
575#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
576#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
577#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
578#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
579#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
580
581/* Mailbox Acceptance Masks */
582#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
583#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
584#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
585#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
586#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
587#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
588#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
589#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
590#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
591#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
592#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
593#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
594#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
595#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
596#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
597#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
598#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
599#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
600#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
601#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
602#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
603#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
604#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
605#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
606#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
607#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
608#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
609#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
610#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
611#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
612#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
613#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
614
615#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
616#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
617#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
618#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
619#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
620#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
621#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
622#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
623#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
624#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
625#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
626#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
627#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
628#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
629#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
630#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
631#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
632#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
633#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
634#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
635#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
636#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
637#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
638#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
639#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
640#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
641#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
642#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
643#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
644#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
645#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
646#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
647
648/* CAN Acceptance Mask Macros */
649#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
650#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
651
652/* Mailbox Registers */
653#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
654#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
655#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
656#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
657#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
658#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
659#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
660#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
661
662#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
663#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
664#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
665#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
666#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
667#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
668#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
669#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
670
671#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
672#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
673#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
674#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
675#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
676#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
677#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
678#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
679
680#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
681#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
682#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
683#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
684#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
685#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
686#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
687#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
688
689#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
690#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
691#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
692#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
693#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
694#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
695#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
696#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
697
698#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
699#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
700#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
701#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
702#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
703#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
704#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
705#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
706
707#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
708#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
709#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
710#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
711#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
712#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
713#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
714#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
715
716#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
717#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
718#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
719#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
720#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
721#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
722#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
723#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
724
725#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
726#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
727#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
728#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
729#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
730#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
731#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
732#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
733
734#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
735#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
736#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
737#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
738#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
739#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
740#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
741#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
742
743#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
744#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
745#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
746#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
747#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
748#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
749#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
750#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
751
752#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
753#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
754#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
755#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
756#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
757#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
758#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
759#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
760
761#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
762#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
763#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
764#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
765#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
766#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
767#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
768#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
769
770#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
771#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
772#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
773#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
774#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
775#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
776#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
777#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
778
779#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
780#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
781#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
782#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
783#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
784#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
785#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
786#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
787
788#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
789#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
790#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
791#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
792#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
793#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
794#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
795#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
796
797#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
798#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
799#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
800#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
801#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
802#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
803#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
804#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
805
806#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
807#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
808#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
809#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
810#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
811#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
812#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
813#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
814
815#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
816#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
817#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
818#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
819#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
820#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
821#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
822#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
823
824#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
825#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
826#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
827#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
828#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
829#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
830#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
831#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
832
833#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
834#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
835#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
836#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
837#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
838#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
839#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
840#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
841
842#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
843#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
844#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
845#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
846#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
847#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
848#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
849#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
850
851#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
852#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
853#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
854#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
855#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
856#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
857#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
858#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
859
860#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
861#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
862#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
863#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
864#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
865#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
866#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
867#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
868
869#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
870#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
871#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
872#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
873#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
874#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
875#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
876#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
877
878#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
879#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
880#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
881#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
882#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
883#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
884#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
885#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
886
887#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
888#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
889#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
890#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
891#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
892#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
893#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
894#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
895
896#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
897#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
898#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
899#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
900#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
901#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
902#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
903#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
904
905#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
906#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
907#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
908#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
909#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
910#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
911#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
912#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
913
914#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
915#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
916#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
917#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
918#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
919#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
920#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
921#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
922
923#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
924#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
925#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
926#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
927#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
928#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
929#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
930#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
931
932#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
933#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
934#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
935#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
936#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
937#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
938#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
939#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
940
941/* CAN Mailbox Area Macros */
942#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
943#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
944#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
945#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
946#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
947#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
948#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
949#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
950
951/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
952#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
953#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
954#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
955#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
956
957/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
958#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
959#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
960#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
961#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
962#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
963#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
964#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
965
966#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
967#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
968#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
969#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
970#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
971#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
972#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
973
974/***********************************************************************************
975** System MMR Register Bits And Macros
976**
977** Disclaimer: All macros are intended to make C and Assembly code more readable.
978** Use these macros carefully, as any that do left shifts for field
979** depositing will result in the lower order bits being destroyed. Any
980** macro that shifts left to properly position the bit-field should be
981** used as part of an OR to initialize a register and NOT as a dynamic
982** modifier UNLESS the lower order bits are saved and ORed back in when
983** the macro is used.
984*************************************************************************************/
985/*
986** ********************* PLL AND RESET MASKS ****************************************/
987/* PLL_CTL Masks */
988#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
989#define PLL_OFF 0x0002 /* PLL Not Powered */
990#define STOPCK 0x0008 /* Core Clock Off */
991#define PDWN 0x0020 /* Enter Deep Sleep Mode */
992#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
993#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
994#define BYPASS 0x0100 /* Bypass the PLL */
995#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
996/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
997#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
998
999/* PLL_DIV Masks */
1000#define SSEL 0x000F /* System Select */
1001#define CSEL 0x0030 /* Core Select */
1002#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
1003#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
1004#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
1005#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1006/* PLL_DIV Macros */
1007#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1008
1009/* VR_CTL Masks */
1010#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1011#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1012#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1013#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1014#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1015
1016#define GAIN 0x000C /* Voltage Level Gain */
1017#define GAIN_5 0x0000 /* GAIN = 5 */
1018#define GAIN_10 0x0004 /* GAIN = 10 */
1019#define GAIN_20 0x0008 /* GAIN = 20 */
1020#define GAIN_50 0x000C /* GAIN = 50 */
1021
1022#define VLEV 0x00F0 /* Internal Voltage Level */
1023#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
1024#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
1025#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
1026#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
1027#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
1028#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
1029#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
1030#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
1031#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
1032#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
1033
1034#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1035#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1036#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
1037#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
1038#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
1039#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1040
1041/* PLL_STAT Masks */
1042#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1043#define FULL_ON 0x0002 /* Processor In Full On Mode */
1044#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1045#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1046
1047/* CHIPID Masks */
1048#define CHIPID_VERSION 0xF0000000
1049#define CHIPID_FAMILY 0x0FFFF000
1050#define CHIPID_MANUFACTURE 0x00000FFE
1051
1052/* SWRST Masks */
1053#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1054#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
1055#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1056#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
1057#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1058
1059/* SYSCR Masks */
1060#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
1061#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1062
1063/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
1064
1065/* SIC_IAR0 Macros */
1066#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
1067#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
1068#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
1069#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
1070#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
1071#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
1072#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
1073#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
1074
1075/* SIC_IAR1 Macros */
1076#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
1077#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
1078#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
1079#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
1080#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
1081#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
1082#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
1083#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
1084
1085/* SIC_IAR2 Macros */
1086#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
1087#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
1088#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
1089#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
1090#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
1091#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
1092#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
1093#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
1094
1095/* SIC_IAR3 Macros */
1096#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
1097#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
1098#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
1099#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
1100#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
1101#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
1102#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
1103#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
1104
1105/* SIC_IMASK Masks */
1106#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1107#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1108#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1109#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1110
1111/* SIC_IWR Masks */
1112#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1113#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1114#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1115#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1116
1117/* ************** UART CONTROLLER MASKS *************************/
1118/* UARTx_LCR Masks */
1119#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1120#define STB 0x04 /* Stop Bits */
1121#define PEN 0x08 /* Parity Enable */
1122#define EPS 0x10 /* Even Parity Select */
1123#define STP 0x20 /* Stick Parity */
1124#define SB 0x40 /* Set Break */
1125#define DLAB 0x80 /* Divisor Latch Access */
1126
1127/* UARTx_MCR Mask */
1128#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1129#define LOOP_ENA_P 0x04
1130/* UARTx_LSR Masks */
1131#define DR 0x01 /* Data Ready */
1132#define OE 0x02 /* Overrun Error */
1133#define PE 0x04 /* Parity Error */
1134#define FE 0x08 /* Framing Error */
1135#define BI 0x10 /* Break Interrupt */
1136#define THRE 0x20 /* THR Empty */
1137#define TEMT 0x40 /* TSR and UART_THR Empty */
1138
1139/* UARTx_IER Masks */
1140#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1141#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1142#define ELSI 0x04 /* Enable RX Status Interrupt */
1143
1144/* UARTx_IIR Masks */
1145#define NINT 0x01 /* Pending Interrupt */
1146#define IIR_TX_READY 0x02 /* UART_THR empty */
1147#define IIR_RX_READY 0x04 /* Receive data ready */
1148#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1149#define IIR_STATUS 0x06
1150
1151/* UARTx_GCTL Masks */
1152#define UCEN 0x01 /* Enable UARTx Clocks */
1153#define IREN 0x02 /* Enable IrDA Mode */
1154#define TPOLC 0x04 /* IrDA TX Polarity Change */
1155#define RPOLC 0x08 /* IrDA RX Polarity Change */
1156#define FPE 0x10 /* Force Parity Error On Transmit */
1157#define FFE 0x20 /* Force Framing Error On Transmit */
1158
1159/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1160/* SPI_CTL Masks */
1161#define TIMOD 0x0003 /* Transfer Initiate Mode */
1162#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1163#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1164#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1165#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1166#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1167#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1168#define PSSE 0x0010 /* Slave-Select Input Enable */
1169#define EMISO 0x0020 /* Enable MISO As Output */
1170#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1171#define LSBF 0x0200 /* LSB First */
1172#define CPHA 0x0400 /* Clock Phase */
1173#define CPOL 0x0800 /* Clock Polarity */
1174#define MSTR 0x1000 /* Master/Slave* */
1175#define WOM 0x2000 /* Write Open Drain Master */
1176#define SPE 0x4000 /* SPI Enable */
1177
1178/* SPI_FLG Masks */
1179#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1180#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1181#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1182#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1183#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1184#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1185#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1186#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1187#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1188#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1189#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1190#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1191#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1192#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1193
1194/* SPI_STAT Masks */
1195#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1196#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1197#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1198#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1199#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1200#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1201#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1202
1203/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1204/* TIMER_ENABLE Masks */
1205#define TIMEN0 0x0001 /* Enable Timer 0 */
1206#define TIMEN1 0x0002 /* Enable Timer 1 */
1207#define TIMEN2 0x0004 /* Enable Timer 2 */
1208#define TIMEN3 0x0008 /* Enable Timer 3 */
1209#define TIMEN4 0x0010 /* Enable Timer 4 */
1210#define TIMEN5 0x0020 /* Enable Timer 5 */
1211#define TIMEN6 0x0040 /* Enable Timer 6 */
1212#define TIMEN7 0x0080 /* Enable Timer 7 */
1213
1214/* TIMER_DISABLE Masks */
1215#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
1216#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
1217#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
1218#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
1219#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
1220#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
1221#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
1222#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
1223
1224/* TIMER_STATUS Masks */
1225#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
1226#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1227#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1228#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1229#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1230#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1231#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1232#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1233#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1234#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1235#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
1236#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
1237#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
1238#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1239#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1240#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1241#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1242#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1243#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1244#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1245#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1246#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1247#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1248#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1249
1250/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1251#define TOVL_ERR0 TOVF_ERR0
1252#define TOVL_ERR1 TOVF_ERR1
1253#define TOVL_ERR2 TOVF_ERR2
1254#define TOVL_ERR3 TOVF_ERR3
1255#define TOVL_ERR4 TOVF_ERR4
1256#define TOVL_ERR5 TOVF_ERR5
1257#define TOVL_ERR6 TOVF_ERR6
1258#define TOVL_ERR7 TOVF_ERR7
1259/* TIMERx_CONFIG Masks */
1260#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1261#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
1262#define EXT_CLK 0x0003 /* External Clock Mode */
1263#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
1264#define PERIOD_CNT 0x0008 /* Period Count */
1265#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1266#define TIN_SEL 0x0020 /* Timer Input Select */
1267#define OUT_DIS 0x0040 /* Output Pad Disable */
1268#define CLK_SEL 0x0080 /* Timer Clock Select */
1269#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1270#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1271#define ERR_TYP 0xC000 /* Error Type */
1272
1273/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1274/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1275/* Port F Masks */
1276#define PF0 0x0001
1277#define PF1 0x0002
1278#define PF2 0x0004
1279#define PF3 0x0008
1280#define PF4 0x0010
1281#define PF5 0x0020
1282#define PF6 0x0040
1283#define PF7 0x0080
1284#define PF8 0x0100
1285#define PF9 0x0200
1286#define PF10 0x0400
1287#define PF11 0x0800
1288#define PF12 0x1000
1289#define PF13 0x2000
1290#define PF14 0x4000
1291#define PF15 0x8000
1292
1293/* Port G Masks */
1294#define PG0 0x0001
1295#define PG1 0x0002
1296#define PG2 0x0004
1297#define PG3 0x0008
1298#define PG4 0x0010
1299#define PG5 0x0020
1300#define PG6 0x0040
1301#define PG7 0x0080
1302#define PG8 0x0100
1303#define PG9 0x0200
1304#define PG10 0x0400
1305#define PG11 0x0800
1306#define PG12 0x1000
1307#define PG13 0x2000
1308#define PG14 0x4000
1309#define PG15 0x8000
1310
1311/* Port H Masks */
1312#define PH0 0x0001
1313#define PH1 0x0002
1314#define PH2 0x0004
1315#define PH3 0x0008
1316#define PH4 0x0010
1317#define PH5 0x0020
1318#define PH6 0x0040
1319#define PH7 0x0080
1320#define PH8 0x0100
1321#define PH9 0x0200
1322#define PH10 0x0400
1323#define PH11 0x0800
1324#define PH12 0x1000
1325#define PH13 0x2000
1326#define PH14 0x4000
1327#define PH15 0x8000
1328
1329/* ******************* SERIAL PORT MASKS **************************************/
1330/* SPORTx_TCR1 Masks */
1331#define TSPEN 0x0001 /* Transmit Enable */
1332#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1333#define DTYPE_NORM 0x0004 /* Data Format Normal */
1334#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1335#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1336#define TLSBIT 0x0010 /* Transmit Bit Order */
1337#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1338#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1339#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1340#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1341#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1342#define TCKFE 0x4000 /* Clock Falling Edge Select */
1343
1344/* SPORTx_TCR2 Masks and Macro */
1345#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1346#define TXSE 0x0100 /* TX Secondary Enable */
1347#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1348#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1349
1350/* SPORTx_RCR1 Masks */
1351#define RSPEN 0x0001 /* Receive Enable */
1352#define IRCLK 0x0002 /* Internal Receive Clock Select */
1353#define DTYPE_NORM 0x0004 /* Data Format Normal */
1354#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1355#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1356#define RLSBIT 0x0010 /* Receive Bit Order */
1357#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1358#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1359#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1360#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1361#define RCKFE 0x4000 /* Clock Falling Edge Select */
1362
1363/* SPORTx_RCR2 Masks */
1364#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1365#define RXSE 0x0100 /* RX Secondary Enable */
1366#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1367#define RRFST 0x0400 /* Right-First Data Order */
1368
1369/* SPORTx_STAT Masks */
1370#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1371#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1372#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1373#define TXF 0x0008 /* Transmit FIFO Full Status */
1374#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1375#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1376#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1377
1378/* SPORTx_MCMC1 Macros */
1379#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1380
1381/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1382#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1383
1384/* SPORTx_MCMC2 Masks */
1385#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1386#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1387#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1388#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1389#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1390#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1391#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1392#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1393#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1394#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1395#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1396#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1397#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1398#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1399#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1400#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1401#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1402#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1403#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1404#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1405#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1406#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1407#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1408
1409/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1410/* EBIU_AMGCTL Masks */
1411#define AMCKEN 0x0001 /* Enable CLKOUT */
1412#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1413#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1414#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1415#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1416#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1417
1418/* EBIU_AMBCTL0 Masks */
1419#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1420#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1421#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1422#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1423#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1424#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1425#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1426#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1427#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1428#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1429#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1430#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1431#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1432#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1433#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1434#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1435#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1436#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1437#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1438#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1439#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1440#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1441#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1442#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1443#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1444#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1445#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1446#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1447#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1448#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1449#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1450#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1451#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1452#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1453#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1454#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1455#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1456#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1457#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1458#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1459#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1460#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1461#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1462#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1463
1464#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1465#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1466#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1467#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1468#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1469#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1470#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1471#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1472#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1473#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1474#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1475#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1476#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1477#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1478#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1479#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1480#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1481#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1482#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1483#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1484#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1485#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1486#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1487#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1488#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1489#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1490#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1491#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1492#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1493#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1494#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1495#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1496#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1497#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1498#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1499#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1500#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1501#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1502#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1503#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1504#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1505#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1506#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1507#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1508
1509/* EBIU_AMBCTL1 Masks */
1510#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1511#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1512#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1513#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1514#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1515#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1516#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1517#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1518#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1519#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1520#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1521#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1522#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1523#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1524#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1525#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1526#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1527#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1528#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1529#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1530#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1531#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1532#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1533#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1534#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1535#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1536#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1537#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1538#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1539#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1540#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1541#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1542#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1543#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1544#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1545#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1546#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1547#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1548#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1549#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1550#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1551#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1552#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1553#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1554
1555#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1556#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1557#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1558#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1559#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1560#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1561#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1562#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1563#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1564#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1565#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1566#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1567#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1568#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1569#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1570#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1571#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1572#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1573#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1574#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1575#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1576#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1577#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1578#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1579#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1580#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1581#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1582#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1583#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1584#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1585#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1586#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1587#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1588#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1589#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1590#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1591#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1592#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1593#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1594#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1595#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1596#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1597#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1598#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1599
1600/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1601/* EBIU_SDGCTL Masks */
1602#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1603#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1604#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1605#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1606#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1607#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1608#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1609#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1610#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1611#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1612#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1613#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1614#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1615#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1616#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1617#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1618#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1619#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1620#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1621#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1622#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1623#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1624#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1625#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1626#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1627#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1628#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1629#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1630#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1631#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1632#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1633#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1634#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1635#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1636#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1637#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1638#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1639#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1640#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1641#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1642#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1643#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1644#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1645#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1646#define EMREN 0x10000000 /* Extended Mode Register Enable */
1647#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1648#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1649
1650/* EBIU_SDBCTL Masks */
1651#define EBE 0x0001 /* Enable SDRAM External Bank */
1652#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1653#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1654#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1655#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1656#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1657#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1658#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1659#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1660#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1661#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1662
1663/* EBIU_SDSTAT Masks */
1664#define SDCI 0x0001 /* SDRAM Controller Idle */
1665#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1666#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1667#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1668#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1669#define BGSTAT 0x0020 /* Bus Grant Status */
1670
1671/* ************************** DMA CONTROLLER MASKS ********************************/
1672/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1673#define DMAEN 0x0001 /* DMA Channel Enable */
1674#define WNR 0x0002 /* Channel Direction (W/R*) */
1675#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1676#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1677#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1678#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1679#define RESTART 0x0020 /* DMA Buffer Clear */
1680#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1681#define DI_EN 0x0080 /* Data Interrupt Enable */
1682#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1683#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1684#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1685#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1686#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1687#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1688#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1689#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1690#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1691#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1692#define NDSIZE 0x0900 /* Next Descriptor Size */
1693
1694#define DMAFLOW 0x7000 /* Flow Control */
1695#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1696#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1697#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1698#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1699#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1700
1701/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1702#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1703#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1704#define PMAP_PPI 0x0000 /* PPI Port DMA */
1705#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1706#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1707#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1708#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1709#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1710#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1711#define PMAP_SPI 0x7000 /* SPI Port DMA */
1712#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1713#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1714#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1715#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1716
1717/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1718#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1719#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1720#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1721#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1722
1723/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1724/* PPI_CONTROL Masks */
1725#define PORT_EN 0x0001 /* PPI Port Enable */
1726#define PORT_DIR 0x0002 /* PPI Port Direction */
1727#define XFR_TYPE 0x000C /* PPI Transfer Type */
1728#define PORT_CFG 0x0030 /* PPI Port Configuration */
1729#define FLD_SEL 0x0040 /* PPI Active Field Select */
1730#define PACK_EN 0x0080 /* PPI Packing Mode */
1731#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1732#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1733#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1734#define DLENGTH 0x3800 /* PPI Data Length */
1735#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1736#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1737#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1738#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1739#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1740#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1741#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1742#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1743#define POLC 0x4000 /* PPI Clock Polarity */
1744#define POLS 0x8000 /* PPI Frame Sync Polarity */
1745
1746/* PPI_STATUS Masks */
1747#define FLD 0x0400 /* Field Indicator */
1748#define FT_ERR 0x0800 /* Frame Track Error */
1749#define OVR 0x1000 /* FIFO Overflow Error */
1750#define UNDR 0x2000 /* FIFO Underrun Error */
1751#define ERR_DET 0x4000 /* Error Detected Indicator */
1752#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1753
1754/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1755/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1756#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1757#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1758
1759/* TWI_PRESCALE Masks */
1760#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1761#define TWI_ENA 0x0080 /* TWI Enable */
1762#define SCCB 0x0200 /* SCCB Compatibility Enable */
1763
1764/* TWI_SLAVE_CTRL Masks */
1765#define SEN 0x0001 /* Slave Enable */
1766#define SADD_LEN 0x0002 /* Slave Address Length */
1767#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1768#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1769#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1770
1771/* TWI_SLAVE_STAT Masks */
1772#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1773#define GCALL 0x0002 /* General Call Indicator */
1774
1775/* TWI_MASTER_CTRL Masks */
1776#define MEN 0x0001 /* Master Mode Enable */
1777#define MADD_LEN 0x0002 /* Master Address Length */
1778#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1779#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1780#define STOP 0x0010 /* Issue Stop Condition */
1781#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1782#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1783#define SDAOVR 0x4000 /* Serial Data Override */
1784#define SCLOVR 0x8000 /* Serial Clock Override */
1785
1786/* TWI_MASTER_STAT Masks */
1787#define MPROG 0x0001 /* Master Transfer In Progress */
1788#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1789#define ANAK 0x0004 /* Address Not Acknowledged */
1790#define DNAK 0x0008 /* Data Not Acknowledged */
1791#define BUFRDERR 0x0010 /* Buffer Read Error */
1792#define BUFWRERR 0x0020 /* Buffer Write Error */
1793#define SDASEN 0x0040 /* Serial Data Sense */
1794#define SCLSEN 0x0080 /* Serial Clock Sense */
1795#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1796
1797/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1798#define SINIT 0x0001 /* Slave Transfer Initiated */
1799#define SCOMP 0x0002 /* Slave Transfer Complete */
1800#define SERR 0x0004 /* Slave Transfer Error */
1801#define SOVF 0x0008 /* Slave Overflow */
1802#define MCOMP 0x0010 /* Master Transfer Complete */
1803#define MERR 0x0020 /* Master Transfer Error */
1804#define XMTSERV 0x0040 /* Transmit FIFO Service */
1805#define RCVSERV 0x0080 /* Receive FIFO Service */
1806
1807/* TWI_FIFO_CTRL Masks */
1808#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1809#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1810#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1811#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1812
1813/* TWI_FIFO_STAT Masks */
1814#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1815#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1816#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1817#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1818
1819#define RCVSTAT 0x000C /* Receive FIFO Status */
1820#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1821#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1822#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1823
1824/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
1825/* CAN_CONTROL Masks */
1826#define SRS 0x0001 /* Software Reset */
1827#define DNM 0x0002 /* Device Net Mode */
1828#define ABO 0x0004 /* Auto-Bus On Enable */
1829#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
1830#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
1831#define SMR 0x0020 /* Sleep Mode Request */
1832#define CSR 0x0040 /* CAN Suspend Mode Request */
1833#define CCR 0x0080 /* CAN Configuration Mode Request */
1834
1835/* CAN_STATUS Masks */
1836#define WT 0x0001 /* TX Warning Flag */
1837#define WR 0x0002 /* RX Warning Flag */
1838#define EP 0x0004 /* Error Passive Mode */
1839#define EBO 0x0008 /* Error Bus Off Mode */
1840#define SMA 0x0020 /* Sleep Mode Acknowledge */
1841#define CSA 0x0040 /* Suspend Mode Acknowledge */
1842#define CCA 0x0080 /* Configuration Mode Acknowledge */
1843#define MBPTR 0x1F00 /* Mailbox Pointer */
1844#define TRM 0x4000 /* Transmit Mode */
1845#define REC 0x8000 /* Receive Mode */
1846
1847/* CAN_CLOCK Masks */
1848#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
1849
1850/* CAN_TIMING Masks */
1851#define TSEG1 0x000F /* Time Segment 1 */
1852#define TSEG2 0x0070 /* Time Segment 2 */
1853#define SAM 0x0080 /* Sampling */
1854#define SJW 0x0300 /* Synchronization Jump Width */
1855
1856/* CAN_DEBUG Masks */
1857#define DEC 0x0001 /* Disable CAN Error Counters */
1858#define DRI 0x0002 /* Disable CAN RX Input */
1859#define DTO 0x0004 /* Disable CAN TX Output */
1860#define DIL 0x0008 /* Disable CAN Internal Loop */
1861#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
1862#define MRB 0x0020 /* Mode Read Back Enable */
1863#define CDE 0x8000 /* CAN Debug Enable */
1864
1865/* CAN_CEC Masks */
1866#define RXECNT 0x00FF /* Receive Error Counter */
1867#define TXECNT 0xFF00 /* Transmit Error Counter */
1868
1869/* CAN_INTR Masks */
1870#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
1871#define MBRIF MBRIRQ /* legacy */
1872#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
1873#define MBTIF MBTIRQ /* legacy */
1874#define GIRQ 0x0004 /* Global Interrupt */
1875#define SMACK 0x0008 /* Sleep Mode Acknowledge */
1876#define CANTX 0x0040 /* CAN TX Bus Value */
1877#define CANRX 0x0080 /* CAN RX Bus Value */
1878
1879/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
1880#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
1881#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
1882#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
1883#define BASEID 0x1FFC /* Base Identifier */
1884#define IDE 0x2000 /* Identifier Extension */
1885#define RTR 0x4000 /* Remote Frame Transmission Request */
1886#define AME 0x8000 /* Acceptance Mask Enable */
1887
1888/* CAN_MBxx_TIMESTAMP Masks */
1889#define TSV 0xFFFF /* Timestamp */
1890
1891/* CAN_MBxx_LENGTH Masks */
1892#define DLC 0x000F /* Data Length Code */
1893
1894/* CAN_AMxxH and CAN_AMxxL Masks */
1895#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
1896#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
1897#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
1898#define BASEID 0x1FFC /* Base Identifier */
1899#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
1900#define FMD 0x4000 /* Full Mask Data Field Enable */
1901#define FDF 0x8000 /* Filter On Data Field Enable */
1902
1903/* CAN_MC1 Masks */
1904#define MC0 0x0001 /* Enable Mailbox 0 */
1905#define MC1 0x0002 /* Enable Mailbox 1 */
1906#define MC2 0x0004 /* Enable Mailbox 2 */
1907#define MC3 0x0008 /* Enable Mailbox 3 */
1908#define MC4 0x0010 /* Enable Mailbox 4 */
1909#define MC5 0x0020 /* Enable Mailbox 5 */
1910#define MC6 0x0040 /* Enable Mailbox 6 */
1911#define MC7 0x0080 /* Enable Mailbox 7 */
1912#define MC8 0x0100 /* Enable Mailbox 8 */
1913#define MC9 0x0200 /* Enable Mailbox 9 */
1914#define MC10 0x0400 /* Enable Mailbox 10 */
1915#define MC11 0x0800 /* Enable Mailbox 11 */
1916#define MC12 0x1000 /* Enable Mailbox 12 */
1917#define MC13 0x2000 /* Enable Mailbox 13 */
1918#define MC14 0x4000 /* Enable Mailbox 14 */
1919#define MC15 0x8000 /* Enable Mailbox 15 */
1920
1921/* CAN_MC2 Masks */
1922#define MC16 0x0001 /* Enable Mailbox 16 */
1923#define MC17 0x0002 /* Enable Mailbox 17 */
1924#define MC18 0x0004 /* Enable Mailbox 18 */
1925#define MC19 0x0008 /* Enable Mailbox 19 */
1926#define MC20 0x0010 /* Enable Mailbox 20 */
1927#define MC21 0x0020 /* Enable Mailbox 21 */
1928#define MC22 0x0040 /* Enable Mailbox 22 */
1929#define MC23 0x0080 /* Enable Mailbox 23 */
1930#define MC24 0x0100 /* Enable Mailbox 24 */
1931#define MC25 0x0200 /* Enable Mailbox 25 */
1932#define MC26 0x0400 /* Enable Mailbox 26 */
1933#define MC27 0x0800 /* Enable Mailbox 27 */
1934#define MC28 0x1000 /* Enable Mailbox 28 */
1935#define MC29 0x2000 /* Enable Mailbox 29 */
1936#define MC30 0x4000 /* Enable Mailbox 30 */
1937#define MC31 0x8000 /* Enable Mailbox 31 */
1938
1939/* CAN_MD1 Masks */
1940#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
1941#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
1942#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
1943#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
1944#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
1945#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
1946#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
1947#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
1948#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
1949#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
1950#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
1951#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
1952#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
1953#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
1954#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
1955#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
1956
1957/* CAN_MD2 Masks */
1958#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
1959#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
1960#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
1961#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
1962#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
1963#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
1964#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
1965#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
1966#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
1967#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
1968#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
1969#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
1970#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
1971#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
1972#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
1973#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
1974
1975/* CAN_RMP1 Masks */
1976#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
1977#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
1978#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
1979#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
1980#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
1981#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
1982#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
1983#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
1984#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
1985#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
1986#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
1987#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
1988#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
1989#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
1990#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
1991#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
1992
1993/* CAN_RMP2 Masks */
1994#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
1995#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
1996#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
1997#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
1998#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
1999#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
2000#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
2001#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
2002#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
2003#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
2004#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
2005#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
2006#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
2007#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
2008#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
2009#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
2010
2011/* CAN_RML1 Masks */
2012#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
2013#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
2014#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
2015#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
2016#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
2017#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
2018#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
2019#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
2020#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
2021#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
2022#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
2023#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
2024#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
2025#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
2026#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
2027#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
2028
2029/* CAN_RML2 Masks */
2030#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
2031#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
2032#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
2033#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
2034#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
2035#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
2036#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
2037#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
2038#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
2039#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
2040#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
2041#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
2042#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
2043#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
2044#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
2045#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
2046
2047/* CAN_OPSS1 Masks */
2048#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
2049#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
2050#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
2051#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
2052#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
2053#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
2054#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
2055#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
2056#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
2057#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
2058#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
2059#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
2060#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
2061#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
2062#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
2063#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
2064
2065/* CAN_OPSS2 Masks */
2066#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
2067#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
2068#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
2069#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
2070#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
2071#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
2072#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
2073#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
2074#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
2075#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
2076#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
2077#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
2078#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
2079#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
2080#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
2081#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
2082
2083/* CAN_TRR1 Masks */
2084#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
2085#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
2086#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
2087#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
2088#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
2089#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
2090#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
2091#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
2092#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
2093#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
2094#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
2095#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
2096#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
2097#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
2098#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
2099#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
2100
2101/* CAN_TRR2 Masks */
2102#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
2103#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
2104#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
2105#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
2106#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
2107#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
2108#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
2109#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
2110#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
2111#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
2112#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
2113#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
2114#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
2115#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
2116#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
2117#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
2118
2119/* CAN_TRS1 Masks */
2120#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
2121#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
2122#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
2123#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
2124#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
2125#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
2126#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
2127#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
2128#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
2129#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
2130#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
2131#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
2132#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
2133#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
2134#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
2135#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
2136
2137/* CAN_TRS2 Masks */
2138#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
2139#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
2140#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
2141#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
2142#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
2143#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
2144#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
2145#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
2146#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
2147#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
2148#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
2149#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
2150#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
2151#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
2152#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
2153#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
2154
2155/* CAN_AA1 Masks */
2156#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
2157#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
2158#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
2159#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
2160#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
2161#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
2162#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
2163#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
2164#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
2165#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
2166#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
2167#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
2168#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
2169#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
2170#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
2171#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
2172
2173/* CAN_AA2 Masks */
2174#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
2175#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
2176#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
2177#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
2178#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
2179#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
2180#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
2181#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
2182#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
2183#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
2184#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
2185#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
2186#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
2187#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
2188#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
2189#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
2190
2191/* CAN_TA1 Masks */
2192#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
2193#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
2194#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
2195#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
2196#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
2197#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
2198#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
2199#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
2200#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
2201#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
2202#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
2203#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
2204#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
2205#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
2206#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
2207#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
2208
2209/* CAN_TA2 Masks */
2210#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
2211#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
2212#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
2213#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
2214#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
2215#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
2216#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
2217#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
2218#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
2219#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
2220#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
2221#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
2222#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
2223#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
2224#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
2225#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
2226
2227/* CAN_MBTD Masks */
2228#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
2229#define TDA 0x0040 /* Temporary Disable Acknowledge */
2230#define TDR 0x0080 /* Temporary Disable Request */
2231
2232/* CAN_RFH1 Masks */
2233#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
2234#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
2235#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
2236#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
2237#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
2238#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
2239#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
2240#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
2241#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
2242#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
2243#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
2244#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
2245#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
2246#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
2247#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
2248#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
2249
2250/* CAN_RFH2 Masks */
2251#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
2252#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
2253#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
2254#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
2255#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
2256#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
2257#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
2258#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
2259#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
2260#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
2261#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
2262#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
2263#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
2264#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
2265#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
2266#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
2267
2268/* CAN_MBTIF1 Masks */
2269#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
2270#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
2271#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
2272#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
2273#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
2274#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
2275#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
2276#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
2277#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
2278#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
2279#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
2280#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
2281#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
2282#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
2283#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
2284#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
2285
2286/* CAN_MBTIF2 Masks */
2287#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
2288#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
2289#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
2290#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
2291#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
2292#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
2293#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
2294#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
2295#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
2296#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
2297#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
2298#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
2299#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
2300#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
2301#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
2302#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
2303
2304/* CAN_MBRIF1 Masks */
2305#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
2306#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
2307#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
2308#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
2309#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
2310#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
2311#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
2312#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
2313#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
2314#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
2315#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
2316#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
2317#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
2318#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
2319#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
2320#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
2321
2322/* CAN_MBRIF2 Masks */
2323#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
2324#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
2325#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
2326#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
2327#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
2328#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
2329#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
2330#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
2331#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
2332#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
2333#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
2334#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
2335#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
2336#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
2337#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
2338#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
2339
2340/* CAN_MBIM1 Masks */
2341#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
2342#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
2343#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
2344#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
2345#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
2346#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
2347#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
2348#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
2349#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
2350#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
2351#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
2352#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
2353#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
2354#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
2355#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
2356#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
2357
2358/* CAN_MBIM2 Masks */
2359#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
2360#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
2361#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
2362#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
2363#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
2364#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
2365#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
2366#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
2367#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
2368#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
2369#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
2370#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
2371#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
2372#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
2373#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
2374#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
2375
2376/* CAN_GIM Masks */
2377#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
2378#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
2379#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
2380#define BOIM 0x0008 /* Enable Bus Off Interrupt */
2381#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
2382#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
2383#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
2384#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
2385#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
2386#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
2387#define ADIM 0x0400 /* Enable Access Denied Interrupt */
2388
2389/* CAN_GIS Masks */
2390#define EWTIS 0x0001 /* TX Error Count IRQ Status */
2391#define EWRIS 0x0002 /* RX Error Count IRQ Status */
2392#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
2393#define BOIS 0x0008 /* Bus Off IRQ Status */
2394#define WUIS 0x0010 /* Wake-Up IRQ Status */
2395#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
2396#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
2397#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
2398#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
2399#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
2400#define ADIS 0x0400 /* Access Denied IRQ Status */
2401
2402/* CAN_GIF Masks */
2403#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
2404#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
2405#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
2406#define BOIF 0x0008 /* Bus Off IRQ Flag */
2407#define WUIF 0x0010 /* Wake-Up IRQ Flag */
2408#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
2409#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
2410#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
2411#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
2412#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
2413#define ADIF 0x0400 /* Access Denied IRQ Flag */
2414
2415/* CAN_UCCNF Masks */
2416#define UCCNF 0x000F /* Universal Counter Mode */
2417#define UC_STAMP 0x0001 /* Timestamp Mode */
2418#define UC_WDOG 0x0002 /* Watchdog Mode */
2419#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
2420#define UC_ERROR 0x0006 /* CAN Error Frame Count */
2421#define UC_OVER 0x0007 /* CAN Overload Frame Count */
2422#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
2423#define UC_AA 0x0009 /* TX Abort Count */
2424#define UC_TA 0x000A /* TX Successful Count */
2425#define UC_REJECT 0x000B /* RX Message Rejected Count */
2426#define UC_RML 0x000C /* RX Message Lost Count */
2427#define UC_RX 0x000D /* Total Successful RX Messages Count */
2428#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
2429#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
2430#define UCRC 0x0020 /* Universal Counter Reload/Clear */
2431#define UCCT 0x0040 /* Universal Counter CAN Trigger */
2432#define UCE 0x0080 /* Universal Counter Enable */
2433
2434/* CAN_ESR Masks */
2435#define ACKE 0x0004 /* Acknowledge Error */
2436#define SER 0x0008 /* Stuff Error */
2437#define CRCE 0x0010 /* CRC Error */
2438#define SA0 0x0020 /* Stuck At Dominant Error */
2439#define BEF 0x0040 /* Bit Error Flag */
2440#define FER 0x0080 /* Form Error Flag */
2441
2442/* CAN_EWR Masks */
2443#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
2444#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
2445
2446/* ******************* PIN CONTROL REGISTER MASKS ************************/
2447/* PORT_MUX Masks */
2448#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
2449#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
2450#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
2451
2452#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
2453#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
2454#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
2455#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
2456
2457#define PFDE 0x0008 /* Port F DMA Request Enable */
2458#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
2459#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
2460
2461#define PFTE 0x0010 /* Port F Timer Enable */
2462#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
2463#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
2464
2465#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
2466#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
2467#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
2468
2469#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
2470#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
2471#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
2472
2473#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
2474#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
2475#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
2476
2477#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
2478#define PFFE_TIMER 0x0000 /* Enable TMR2 */
2479#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
2480
2481#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
2482#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
2483#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
2484
2485#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
2486#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
2487#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
2488
2489#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
2490#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
2491#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
2492
2493/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
2494/* HDMAx_CTL Masks */
2495#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
2496#define REP 0x0002 /* HDMA Request Polarity */
2497#define UTE 0x0004 /* Urgency Threshold Enable */
2498#define OIE 0x0010 /* Overflow Interrupt Enable */
2499#define BDIE 0x0020 /* Block Done Interrupt Enable */
2500#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
2501#define DRQ 0x0300 /* HDMA Request Type */
2502#define DRQ_NONE 0x0000 /* No Request */
2503#define DRQ_SINGLE 0x0100 /* Channels Request Single */
2504#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
2505#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
2506#define RBC 0x1000 /* Reload BCNT With IBCNT */
2507#define PS 0x2000 /* HDMA Pin Status */
2508#define OI 0x4000 /* Overflow Interrupt Generated */
2509#define BDI 0x8000 /* Block Done Interrupt Generated */
2510
2511/* entry addresses of the user-callable Boot ROM functions */
2512
2513#define _BOOTROM_RESET 0xEF000000
2514#define _BOOTROM_FINAL_INIT 0xEF000002
2515#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
2516#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
2517#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
2518#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
2519#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
2520#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
2521#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
2522
2523/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
2524#define PGDE_UART PFDE_UART
2525#define PGDE_DMA PFDE_DMA
2526#define CKELOW SCKELOW
2527#endif /* _DEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
new file mode 100644
index 000000000000..3d6c83e31b1e
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -0,0 +1,405 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/defbf537.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _DEF_BF537_H
33#define _DEF_BF537_H
34
35/* Include all Core registers and bit definitions*/
36#include <asm/cdef_LPBlackfin.h>
37
38/* Include all MMR and bit defines common to BF534 */
39#include "defBF534.h"
40
41/************************************************************************************
42** Define EMAC Section Unique to BF536/BF537
43*************************************************************************************/
44
45/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
46#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
47#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
48#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
49#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
50#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
51#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
52#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
53#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
54#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
55#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
56#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
57#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
58#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
59#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
60#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
61#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
62#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
63#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
64#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
65
66#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
67#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
68#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
69#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
70#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
71#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
72#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
73#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
74
75#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
76#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
77#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
78#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
79#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
80
81#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
82#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
83#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
84#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
85#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
86#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
87#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
88#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
89#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
90#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
91#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
92#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
93#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
94#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
95#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
96#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
97#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
98#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
99#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
100#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
101#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
102#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
103#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
104#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
105
106#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
107#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
108#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
109#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
110#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
111#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
112#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
113#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
114#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
115#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
116#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
117#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
118#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
119#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
120#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
121#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
122#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
123#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
124#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
125#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
126#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
127#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
128#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
129
130/* Listing for IEEE-Supported Count Registers */
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
192/* EMAC_OPMODE Masks */
193#define RE 0x00000001 /* Receiver Enable */
194#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
195#define HU 0x00000010 /* Hash Filter Unicast Address */
196#define HM 0x00000020 /* Hash Filter Multicast Address */
197#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
198#define PR 0x00000080 /* Promiscuous Mode Enable */
199#define IFE 0x00000100 /* Inverse Filtering Enable */
200#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
201#define PBF 0x00000400 /* Pass Bad Frames Enable */
202#define PSF 0x00000800 /* Pass Short Frames Enable */
203#define RAF 0x00001000 /* Receive-All Mode */
204#define TE 0x00010000 /* Transmitter Enable */
205#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
206#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
207#define DC 0x00080000 /* Deferral Check */
208#define BOLMT 0x00300000 /* Back-Off Limit */
209#define BOLMT_10 0x00000000 /* 10-bit range */
210#define BOLMT_8 0x00100000 /* 8-bit range */
211#define BOLMT_4 0x00200000 /* 4-bit range */
212#define BOLMT_1 0x00300000 /* 1-bit range */
213#define DRTY 0x00400000 /* Disable TX Retry On Collision */
214#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
215#define RMII 0x01000000 /* RMII/MII* Mode */
216#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
217#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
218#define LB 0x08000000 /* Internal Loopback Enable */
219#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
220
221/* EMAC_STAADD Masks */
222#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
223#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
224#define STADISPRE 0x00000004 /* Disable Preamble Generation */
225#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
226#define REGAD 0x000007C0 /* STA Register Address */
227#define PHYAD 0x0000F800 /* PHY Device Address */
228
229#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
230#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
231
232/* EMAC_STADAT Mask */
233#define STADATA 0x0000FFFF /* Station Management Data */
234
235/* EMAC_FLC Masks */
236#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
237#define FLCE 0x00000002 /* Flow Control Enable */
238#define PCF 0x00000004 /* Pass Control Frames */
239#define BKPRSEN 0x00000008 /* Enable Backpressure */
240#define FLCPAUSE 0xFFFF0000 /* Pause Time */
241
242#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
243
244/* EMAC_WKUP_CTL Masks */
245#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
246#define MPKE 0x00000002 /* Magic Packet Enable */
247#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
248#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
249#define MPKS 0x00000020 /* Magic Packet Received Status */
250#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
251
252/* EMAC_WKUP_FFCMD Masks */
253#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
254#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
255#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
256#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
257#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
258#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
259#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
260#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
261
262/* EMAC_WKUP_FFOFF Masks */
263#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
264#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
265#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
266#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
267
268#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
269#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
270#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
271#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
272/* Set ALL Offsets */
273#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
274
275/* EMAC_WKUP_FFCRC0 Masks */
276#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
277#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
278
279#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
280#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
281
282/* EMAC_WKUP_FFCRC1 Masks */
283#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
284#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
285
286#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
287#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
288
289/* EMAC_SYSCTL Masks */
290#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
291#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
292#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
293#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
294#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
295
296#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
297
298/* EMAC_SYSTAT Masks */
299#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
300#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
301#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
302#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
303#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
304#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
305#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
306#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
307
308/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
309#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
310#define RX_COMP 0x00001000 /* RX Frame Complete */
311#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
312#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
313#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
314#define RX_CRC 0x00010000 /* RX Frame CRC Error */
315#define RX_LEN 0x00020000 /* RX Frame Length Error */
316#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
317#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
318#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
319#define RX_PHY 0x00200000 /* RX Frame PHY Error */
320#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
321#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
322#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
323#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
324#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
325#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
326#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
327#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
328#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
329#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
330
331/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
332#define TX_COMP 0x00000001 /* TX Frame Complete */
333#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
334#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
335#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
336#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
337#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
338#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
339#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
340#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
341#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
342#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
343#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
344#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
345#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
346#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
347
348/* EMAC_MMC_CTL Masks */
349#define RSTC 0x00000001 /* Reset All Counters */
350#define CROLL 0x00000002 /* Counter Roll-Over Enable */
351#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
352#define MMCE 0x00000008 /* Enable MMC Counter Operation */
353
354/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
355#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
356#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
357#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
358#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
359#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
360#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
361#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
362#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
363#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
364#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
365#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
366#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
367#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
368#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
369#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
370#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
371#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
372#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
373#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
374#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
375#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
376#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
377#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
378#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
379
380/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
381#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
382#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
383#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
384#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
385#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
386#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
387#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
388#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
389#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
390#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
391#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
392#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
393#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
394#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
395#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
396#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
397#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
398#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
399#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
400#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
401#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
402#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
403#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
404
405#endif /* _DEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/dma.h b/arch/blackfin/mach-bf537/include/mach/dma.h
new file mode 100644
index 000000000000..7a964040870a
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/dma.h
@@ -0,0 +1,55 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0
38#define CH_EMAC_RX 1
39#define CH_EMAC_TX 2
40#define CH_SPORT0_RX 3
41#define CH_SPORT0_TX 4
42#define CH_SPORT1_RX 5
43#define CH_SPORT1_TX 6
44#define CH_SPI 7
45#define CH_UART0_RX 8
46#define CH_UART0_TX 9
47#define CH_UART1_RX 10
48#define CH_UART1_TX 11
49
50#define CH_MEM_STREAM0_DEST 12 /* TX */
51#define CH_MEM_STREAM0_SRC 13 /* RX */
52#define CH_MEM_STREAM1_DEST 14 /* TX */
53#define CH_MEM_STREAM1_SRC 15 /* RX */
54
55#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
new file mode 100644
index 000000000000..2e68a8a1e730
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -0,0 +1,214 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/irq.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF537_IRQ_H_
33#define _BF537_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 * Event Source Core Event Name
38 * Core Emulation **
39 * Events (highest priority) EMU 0
40 * Reset RST 1
41 * NMI NMI 2
42 * Exception EVX 3
43 * Reserved -- 4
44 * Hardware Error IVHW 5
45 * Core Timer IVTMR 6
46 * .....
47 *
48 * Softirq IVG14
49 * System Call --
50 * (lowest priority) IVG15
51 */
52
53#define SYS_IRQS 39
54#define NR_PERI_INTS 32
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /*Emulation */
59#define IRQ_RST 1 /*reset */
60#define IRQ_NMI 2 /*Non Maskable */
61#define IRQ_EVX 3 /*Exception */
62#define IRQ_UNUSED 4 /*- unused interrupt*/
63#define IRQ_HWERR 5 /*Hardware Error */
64#define IRQ_CORETMR 6 /*Core timer */
65
66#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
67#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
68#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
69#define IRQ_RTC 10 /*RTC Interrupt */
70#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
71#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
72#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
73#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
74#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
75#define IRQ_TWI 16 /*TWI Interrupt */
76#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
77#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
78#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
79#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
80#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
81#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
82#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
83#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
84#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
85#define IRQ_TMR0 26 /*Timer 0 */
86#define IRQ_TMR1 27 /*Timer 1 */
87#define IRQ_TMR2 28 /*Timer 2 */
88#define IRQ_TMR3 29 /*Timer 3 */
89#define IRQ_TMR4 30 /*Timer 4 */
90#define IRQ_TMR5 31 /*Timer 5 */
91#define IRQ_TMR6 32 /*Timer 6 */
92#define IRQ_TMR7 33 /*Timer 7 */
93#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
94#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
95#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
96#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
97#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
98#define IRQ_WATCH 38 /*Watch Dog Timer */
99
100#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
101#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
102#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */
103#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
104#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
105#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
106#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
107#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
108
109#define IRQ_PF0 50
110#define IRQ_PF1 51
111#define IRQ_PF2 52
112#define IRQ_PF3 53
113#define IRQ_PF4 54
114#define IRQ_PF5 55
115#define IRQ_PF6 56
116#define IRQ_PF7 57
117#define IRQ_PF8 58
118#define IRQ_PF9 59
119#define IRQ_PF10 60
120#define IRQ_PF11 61
121#define IRQ_PF12 62
122#define IRQ_PF13 63
123#define IRQ_PF14 64
124#define IRQ_PF15 65
125
126#define IRQ_PG0 66
127#define IRQ_PG1 67
128#define IRQ_PG2 68
129#define IRQ_PG3 69
130#define IRQ_PG4 70
131#define IRQ_PG5 71
132#define IRQ_PG6 72
133#define IRQ_PG7 73
134#define IRQ_PG8 74
135#define IRQ_PG9 75
136#define IRQ_PG10 76
137#define IRQ_PG11 77
138#define IRQ_PG12 78
139#define IRQ_PG13 79
140#define IRQ_PG14 80
141#define IRQ_PG15 81
142
143#define IRQ_PH0 82
144#define IRQ_PH1 83
145#define IRQ_PH2 84
146#define IRQ_PH3 85
147#define IRQ_PH4 86
148#define IRQ_PH5 87
149#define IRQ_PH6 88
150#define IRQ_PH7 89
151#define IRQ_PH8 90
152#define IRQ_PH9 91
153#define IRQ_PH10 92
154#define IRQ_PH11 93
155#define IRQ_PH12 94
156#define IRQ_PH13 95
157#define IRQ_PH14 96
158#define IRQ_PH15 97
159
160#define GPIO_IRQ_BASE IRQ_PF0
161
162#define NR_IRQS (IRQ_PH15+1)
163
164#define IVG7 7
165#define IVG8 8
166#define IVG9 9
167#define IVG10 10
168#define IVG11 11
169#define IVG12 12
170#define IVG13 13
171#define IVG14 14
172#define IVG15 15
173
174/* IAR0 BIT FIELDS*/
175#define IRQ_PLL_WAKEUP_POS 0
176#define IRQ_DMA_ERROR_POS 4
177#define IRQ_ERROR_POS 8
178#define IRQ_RTC_POS 12
179#define IRQ_PPI_POS 16
180#define IRQ_SPORT0_RX_POS 20
181#define IRQ_SPORT0_TX_POS 24
182#define IRQ_SPORT1_RX_POS 28
183
184/* IAR1 BIT FIELDS*/
185#define IRQ_SPORT1_TX_POS 0
186#define IRQ_TWI_POS 4
187#define IRQ_SPI_POS 8
188#define IRQ_UART0_RX_POS 12
189#define IRQ_UART0_TX_POS 16
190#define IRQ_UART1_RX_POS 20
191#define IRQ_UART1_TX_POS 24
192#define IRQ_CAN_RX_POS 28
193
194/* IAR2 BIT FIELDS*/
195#define IRQ_CAN_TX_POS 0
196#define IRQ_MAC_RX_POS 4
197#define IRQ_MAC_TX_POS 8
198#define IRQ_TMR0_POS 12
199#define IRQ_TMR1_POS 16
200#define IRQ_TMR2_POS 20
201#define IRQ_TMR3_POS 24
202#define IRQ_TMR4_POS 28
203
204/* IAR3 BIT FIELDS*/
205#define IRQ_TMR5_POS 0
206#define IRQ_TMR6_POS 4
207#define IRQ_TMR7_POS 8
208#define IRQ_PROG_INTA_POS 12
209#define IRQ_PORTG_INTB_POS 16
210#define IRQ_MEM_DMA0_POS 20
211#define IRQ_MEM_DMA1_POS 24
212#define IRQ_WATCH_POS 28
213
214#endif /* _BF537_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_init.h b/arch/blackfin/mach-bf537/include/mach/mem_init.h
new file mode 100644
index 000000000000..f67698f670ca
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/mem_init.h
@@ -0,0 +1,303 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_MT48LC32M8A2_75)
122 /*SDRAM INFORMATION: */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129 /*SDRAM INFORMATION: */
130#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132#define SDRAM_CL CL_3
133#endif
134
135#if (CONFIG_MEM_GENERIC_BOARD)
136 /*SDRAM INFORMATION: Modify this for your board */
137#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139#define SDRAM_CL CL_3
140#endif
141
142/* Equation from section 17 (p17-46) of BF533 HRM */
143#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
144
145/* Enable SCLK Out */
146#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
147
148#if defined CONFIG_CLKIN_HALF
149#define CLKIN_HALF 1
150#else
151#define CLKIN_HALF 0
152#endif
153
154#if defined CONFIG_PLL_BYPASS
155#define PLL_BYPASS 1
156#else
157#define PLL_BYPASS 0
158#endif
159
160/***************************************Currently Not Being Used *********************************/
161#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
162#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
163#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
164#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
165#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
166
167#if (flash_EBIU_AMBCTL_TT > 3)
168#define flash_EBIU_AMBCTL0_TT B0TT_4
169#endif
170#if (flash_EBIU_AMBCTL_TT == 3)
171#define flash_EBIU_AMBCTL0_TT B0TT_3
172#endif
173#if (flash_EBIU_AMBCTL_TT == 2)
174#define flash_EBIU_AMBCTL0_TT B0TT_2
175#endif
176#if (flash_EBIU_AMBCTL_TT < 2)
177#define flash_EBIU_AMBCTL0_TT B0TT_1
178#endif
179
180#if (flash_EBIU_AMBCTL_ST > 3)
181#define flash_EBIU_AMBCTL0_ST B0ST_4
182#endif
183#if (flash_EBIU_AMBCTL_ST == 3)
184#define flash_EBIU_AMBCTL0_ST B0ST_3
185#endif
186#if (flash_EBIU_AMBCTL_ST == 2)
187#define flash_EBIU_AMBCTL0_ST B0ST_2
188#endif
189#if (flash_EBIU_AMBCTL_ST < 2)
190#define flash_EBIU_AMBCTL0_ST B0ST_1
191#endif
192
193#if (flash_EBIU_AMBCTL_HT > 2)
194#define flash_EBIU_AMBCTL0_HT B0HT_3
195#endif
196#if (flash_EBIU_AMBCTL_HT == 2)
197#define flash_EBIU_AMBCTL0_HT B0HT_2
198#endif
199#if (flash_EBIU_AMBCTL_HT == 1)
200#define flash_EBIU_AMBCTL0_HT B0HT_1
201#endif
202#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
203#define flash_EBIU_AMBCTL0_HT B0HT_0
204#endif
205#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
206#define flash_EBIU_AMBCTL0_HT B0HT_1
207#endif
208
209#if (flash_EBIU_AMBCTL_WAT > 14)
210#define flash_EBIU_AMBCTL0_WAT B0WAT_15
211#endif
212#if (flash_EBIU_AMBCTL_WAT == 14)
213#define flash_EBIU_AMBCTL0_WAT B0WAT_14
214#endif
215#if (flash_EBIU_AMBCTL_WAT == 13)
216#define flash_EBIU_AMBCTL0_WAT B0WAT_13
217#endif
218#if (flash_EBIU_AMBCTL_WAT == 12)
219#define flash_EBIU_AMBCTL0_WAT B0WAT_12
220#endif
221#if (flash_EBIU_AMBCTL_WAT == 11)
222#define flash_EBIU_AMBCTL0_WAT B0WAT_11
223#endif
224#if (flash_EBIU_AMBCTL_WAT == 10)
225#define flash_EBIU_AMBCTL0_WAT B0WAT_10
226#endif
227#if (flash_EBIU_AMBCTL_WAT == 9)
228#define flash_EBIU_AMBCTL0_WAT B0WAT_9
229#endif
230#if (flash_EBIU_AMBCTL_WAT == 8)
231#define flash_EBIU_AMBCTL0_WAT B0WAT_8
232#endif
233#if (flash_EBIU_AMBCTL_WAT == 7)
234#define flash_EBIU_AMBCTL0_WAT B0WAT_7
235#endif
236#if (flash_EBIU_AMBCTL_WAT == 6)
237#define flash_EBIU_AMBCTL0_WAT B0WAT_6
238#endif
239#if (flash_EBIU_AMBCTL_WAT == 5)
240#define flash_EBIU_AMBCTL0_WAT B0WAT_5
241#endif
242#if (flash_EBIU_AMBCTL_WAT == 4)
243#define flash_EBIU_AMBCTL0_WAT B0WAT_4
244#endif
245#if (flash_EBIU_AMBCTL_WAT == 3)
246#define flash_EBIU_AMBCTL0_WAT B0WAT_3
247#endif
248#if (flash_EBIU_AMBCTL_WAT == 2)
249#define flash_EBIU_AMBCTL0_WAT B0WAT_2
250#endif
251#if (flash_EBIU_AMBCTL_WAT == 1)
252#define flash_EBIU_AMBCTL0_WAT B0WAT_1
253#endif
254
255#if (flash_EBIU_AMBCTL_RAT > 14)
256#define flash_EBIU_AMBCTL0_RAT B0RAT_15
257#endif
258#if (flash_EBIU_AMBCTL_RAT == 14)
259#define flash_EBIU_AMBCTL0_RAT B0RAT_14
260#endif
261#if (flash_EBIU_AMBCTL_RAT == 13)
262#define flash_EBIU_AMBCTL0_RAT B0RAT_13
263#endif
264#if (flash_EBIU_AMBCTL_RAT == 12)
265#define flash_EBIU_AMBCTL0_RAT B0RAT_12
266#endif
267#if (flash_EBIU_AMBCTL_RAT == 11)
268#define flash_EBIU_AMBCTL0_RAT B0RAT_11
269#endif
270#if (flash_EBIU_AMBCTL_RAT == 10)
271#define flash_EBIU_AMBCTL0_RAT B0RAT_10
272#endif
273#if (flash_EBIU_AMBCTL_RAT == 9)
274#define flash_EBIU_AMBCTL0_RAT B0RAT_9
275#endif
276#if (flash_EBIU_AMBCTL_RAT == 8)
277#define flash_EBIU_AMBCTL0_RAT B0RAT_8
278#endif
279#if (flash_EBIU_AMBCTL_RAT == 7)
280#define flash_EBIU_AMBCTL0_RAT B0RAT_7
281#endif
282#if (flash_EBIU_AMBCTL_RAT == 6)
283#define flash_EBIU_AMBCTL0_RAT B0RAT_6
284#endif
285#if (flash_EBIU_AMBCTL_RAT == 5)
286#define flash_EBIU_AMBCTL0_RAT B0RAT_5
287#endif
288#if (flash_EBIU_AMBCTL_RAT == 4)
289#define flash_EBIU_AMBCTL0_RAT B0RAT_4
290#endif
291#if (flash_EBIU_AMBCTL_RAT == 3)
292#define flash_EBIU_AMBCTL0_RAT B0RAT_3
293#endif
294#if (flash_EBIU_AMBCTL_RAT == 2)
295#define flash_EBIU_AMBCTL0_RAT B0RAT_2
296#endif
297#if (flash_EBIU_AMBCTL_RAT == 1)
298#define flash_EBIU_AMBCTL0_RAT B0RAT_1
299#endif
300
301#define flash_EBIU_AMBCTL0 \
302 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
303 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h
new file mode 100644
index 000000000000..5078b669431f
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/mem_map.h
@@ -0,0 +1,179 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_537_H_
32#define _MEM_MAP_537_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x800
51
52/* Level 1 Memory */
53
54/* Memory Map for ADSP-BF537 processors */
55
56#ifdef CONFIG_BFIN_ICACHE
57#define BFIN_ICACHESIZE (16*1024)
58#else
59#define BFIN_ICACHESIZE (0*1024)
60#endif
61
62
63#ifdef CONFIG_BF537
64#define L1_CODE_START 0xFFA00000
65#define L1_DATA_A_START 0xFF800000
66#define L1_DATA_B_START 0xFF900000
67
68#define L1_CODE_LENGTH 0xC000
69
70#ifdef CONFIG_BFIN_DCACHE
71
72#ifdef CONFIG_BFIN_DCACHE_BANKA
73#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
74#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
75#define L1_DATA_B_LENGTH 0x8000
76#define BFIN_DCACHESIZE (16*1024)
77#define BFIN_DSUPBANKS 1
78#else
79#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
80#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
81#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
82#define BFIN_DCACHESIZE (32*1024)
83#define BFIN_DSUPBANKS 2
84#endif
85
86#else
87#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
88#define L1_DATA_A_LENGTH 0x8000
89#define L1_DATA_B_LENGTH 0x8000
90#define BFIN_DCACHESIZE (0*1024)
91#define BFIN_DSUPBANKS 0
92#endif /*CONFIG_BFIN_DCACHE*/
93
94#endif /*CONFIG_BF537*/
95
96/* Memory Map for ADSP-BF536 processors */
97
98#ifdef CONFIG_BF536
99#define L1_CODE_START 0xFFA00000
100#define L1_DATA_A_START 0xFF804000
101#define L1_DATA_B_START 0xFF904000
102
103#define L1_CODE_LENGTH 0xC000
104
105
106#ifdef CONFIG_BFIN_DCACHE
107
108#ifdef CONFIG_BFIN_DCACHE_BANKA
109#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
110#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
111#define L1_DATA_B_LENGTH 0x4000
112#define BFIN_DCACHESIZE (16*1024)
113#define BFIN_DSUPBANKS 1
114
115#else
116#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
117#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
118#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
119#define BFIN_DCACHESIZE (32*1024)
120#define BFIN_DSUPBANKS 2
121#endif
122
123#else
124#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
125#define L1_DATA_A_LENGTH 0x4000
126#define L1_DATA_B_LENGTH 0x4000
127#define BFIN_DCACHESIZE (0*1024)
128#define BFIN_DSUPBANKS 0
129#endif /*CONFIG_BFIN_DCACHE*/
130
131#endif
132
133/* Memory Map for ADSP-BF534 processors */
134
135#ifdef CONFIG_BF534
136#define L1_CODE_START 0xFFA00000
137#define L1_DATA_A_START 0xFF800000
138#define L1_DATA_B_START 0xFF900000
139
140#define L1_CODE_LENGTH 0xC000
141
142#ifdef CONFIG_BFIN_DCACHE
143
144#ifdef CONFIG_BFIN_DCACHE_BANKA
145#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
146#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
147#define L1_DATA_B_LENGTH 0x8000
148#define BFIN_DCACHESIZE (16*1024)
149#define BFIN_DSUPBANKS 1
150
151#else
152#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
153#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
154#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
155#define BFIN_DCACHESIZE (32*1024)
156#define BFIN_DSUPBANKS 2
157#endif
158
159#else
160#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
161#define L1_DATA_A_LENGTH 0x8000
162#define L1_DATA_B_LENGTH 0x8000
163#define BFIN_DCACHESIZE (0*1024)
164#define BFIN_DSUPBANKS 0
165#endif /*CONFIG_BFIN_DCACHE*/
166
167#endif
168
169/* Level 2 Memory - none */
170
171#define L2_START 0
172#define L2_LENGTH 0
173
174/* Scratch Pad Memory */
175
176#define L1_SCRATCH_START 0xFFB00000
177#define L1_SCRATCH_LENGTH 0x1000
178
179#endif /* _MEM_MAP_537_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h
new file mode 100644
index 000000000000..78fee6e0f237
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/portmux.h
@@ -0,0 +1,144 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
5
6#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
7#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
8#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
9#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
10#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
11#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
12#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
13#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
14#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
15#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
16#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
17#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
18#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
19#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
20#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
21#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
22#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
23#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
24#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
25#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
26#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
27#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
28#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
29#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
30#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
31#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
32#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
33#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
34
35#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
36#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
37#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
38#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
39#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
40#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
41#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
42#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
43#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
44#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
45#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
46#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
47#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
48#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
49#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
50#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
51#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
52#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
53#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
54#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
55#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
56#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
57#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
58#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
59
60#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
61#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
62#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
63#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
64#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
65#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
66#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
67#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
68#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
69#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
70#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
71#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
72#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
73#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
74#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
75#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
76#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
77#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
78#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
79
80#define PORT_PJ0 (GPIO_PH15 + 1)
81#define PORT_PJ1 (GPIO_PH15 + 2)
82#define PORT_PJ2 (GPIO_PH15 + 3)
83#define PORT_PJ3 (GPIO_PH15 + 4)
84#define PORT_PJ4 (GPIO_PH15 + 5)
85#define PORT_PJ5 (GPIO_PH15 + 6)
86#define PORT_PJ6 (GPIO_PH15 + 7)
87#define PORT_PJ7 (GPIO_PH15 + 8)
88#define PORT_PJ8 (GPIO_PH15 + 9)
89#define PORT_PJ9 (GPIO_PH15 + 10)
90#define PORT_PJ10 (GPIO_PH15 + 11)
91#define PORT_PJ11 (GPIO_PH15 + 12)
92
93#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
94#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
95#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
96#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
97#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
98#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
99#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
100#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
101#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
102#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
103#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
104#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
105#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
106#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
107#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
108#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
109#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
110
111#define P_MII0 {\
112 P_MII0_ETxD0, \
113 P_MII0_ETxD1, \
114 P_MII0_ETxD2, \
115 P_MII0_ETxD3, \
116 P_MII0_ETxEN, \
117 P_MII0_TxCLK, \
118 P_MII0_PHYINT, \
119 P_MII0_COL, \
120 P_MII0_ERxD0, \
121 P_MII0_ERxD1, \
122 P_MII0_ERxD2, \
123 P_MII0_ERxD3, \
124 P_MII0_ERxDV, \
125 P_MII0_ERxCLK, \
126 P_MII0_ERxER, \
127 P_MII0_CRS, \
128 P_MDC, \
129 P_MDIO, 0}
130
131
132#define P_RMII0 {\
133 P_MII0_ETxD0, \
134 P_MII0_ETxD1, \
135 P_MII0_ETxEN, \
136 P_MII0_ERxD0, \
137 P_MII0_ERxD1, \
138 P_MII0_ERxER, \
139 P_RMII0_REF_CLK, \
140 P_RMII0_MDINT, \
141 P_RMII0_CRS_DV, \
142 P_MDC, \
143 P_MDIO, 0}
144#endif /* _MACH_PORTMUX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-10 19:12:30 -0500