diff options
Diffstat (limited to 'arch/blackfin/mach-bf537/include/mach/defBF534.h')
| -rw-r--r-- | arch/blackfin/mach-bf537/include/mach/defBF534.h | 80 |
1 files changed, 0 insertions, 80 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index aad61b887373..6f56907a18c0 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h | |||
| @@ -1241,86 +1241,6 @@ | |||
| 1241 | #define PH14 0x4000 | 1241 | #define PH14 0x4000 |
| 1242 | #define PH15 0x8000 | 1242 | #define PH15 0x8000 |
| 1243 | 1243 | ||
| 1244 | /* ******************* SERIAL PORT MASKS **************************************/ | ||
| 1245 | /* SPORTx_TCR1 Masks */ | ||
| 1246 | #define TSPEN 0x0001 /* Transmit Enable */ | ||
| 1247 | #define ITCLK 0x0002 /* Internal Transmit Clock Select */ | ||
| 1248 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ | ||
| 1249 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 1250 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 1251 | #define TLSBIT 0x0010 /* Transmit Bit Order */ | ||
| 1252 | #define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ | ||
| 1253 | #define TFSR 0x0400 /* Transmit Frame Sync Required Select */ | ||
| 1254 | #define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ | ||
| 1255 | #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ | ||
| 1256 | #define LATFS 0x2000 /* Late Transmit Frame Sync Select */ | ||
| 1257 | #define TCKFE 0x4000 /* Clock Falling Edge Select */ | ||
| 1258 | |||
| 1259 | /* SPORTx_TCR2 Masks and Macro */ | ||
| 1260 | #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ | ||
| 1261 | #define TXSE 0x0100 /* TX Secondary Enable */ | ||
| 1262 | #define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ | ||
| 1263 | #define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ | ||
| 1264 | |||
| 1265 | /* SPORTx_RCR1 Masks */ | ||
| 1266 | #define RSPEN 0x0001 /* Receive Enable */ | ||
| 1267 | #define IRCLK 0x0002 /* Internal Receive Clock Select */ | ||
| 1268 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ | ||
| 1269 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 1270 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 1271 | #define RLSBIT 0x0010 /* Receive Bit Order */ | ||
| 1272 | #define IRFS 0x0200 /* Internal Receive Frame Sync Select */ | ||
| 1273 | #define RFSR 0x0400 /* Receive Frame Sync Required Select */ | ||
| 1274 | #define LRFS 0x1000 /* Low Receive Frame Sync Select */ | ||
| 1275 | #define LARFS 0x2000 /* Late Receive Frame Sync Select */ | ||
| 1276 | #define RCKFE 0x4000 /* Clock Falling Edge Select */ | ||
| 1277 | |||
| 1278 | /* SPORTx_RCR2 Masks */ | ||
| 1279 | #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ | ||
| 1280 | #define RXSE 0x0100 /* RX Secondary Enable */ | ||
| 1281 | #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ | ||
| 1282 | #define RRFST 0x0400 /* Right-First Data Order */ | ||
| 1283 | |||
| 1284 | /* SPORTx_STAT Masks */ | ||
| 1285 | #define RXNE 0x0001 /* Receive FIFO Not Empty Status */ | ||
| 1286 | #define RUVF 0x0002 /* Sticky Receive Underflow Status */ | ||
| 1287 | #define ROVF 0x0004 /* Sticky Receive Overflow Status */ | ||
| 1288 | #define TXF 0x0008 /* Transmit FIFO Full Status */ | ||
| 1289 | #define TUVF 0x0010 /* Sticky Transmit Underflow Status */ | ||
| 1290 | #define TOVF 0x0020 /* Sticky Transmit Overflow Status */ | ||
| 1291 | #define TXHRE 0x0040 /* Transmit Hold Register Empty */ | ||
| 1292 | |||
| 1293 | /* SPORTx_MCMC1 Macros */ | ||
| 1294 | #define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ | ||
| 1295 | |||
| 1296 | /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ | ||
| 1297 | #define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ | ||
| 1298 | |||
| 1299 | /* SPORTx_MCMC2 Masks */ | ||
| 1300 | #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ | ||
| 1301 | #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ | ||
| 1302 | #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ | ||
| 1303 | #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ | ||
| 1304 | #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ | ||
| 1305 | #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ | ||
| 1306 | #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ | ||
| 1307 | #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ | ||
| 1308 | #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ | ||
| 1309 | #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ | ||
| 1310 | #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ | ||
| 1311 | #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ | ||
| 1312 | #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ | ||
| 1313 | #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ | ||
| 1314 | #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ | ||
| 1315 | #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ | ||
| 1316 | #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ | ||
| 1317 | #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ | ||
| 1318 | #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ | ||
| 1319 | #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ | ||
| 1320 | #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ | ||
| 1321 | #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ | ||
| 1322 | #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ | ||
| 1323 | |||
| 1324 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ | 1244 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ |
| 1325 | /* EBIU_AMGCTL Masks */ | 1245 | /* EBIU_AMGCTL Masks */ |
| 1326 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | 1246 | #define AMCKEN 0x0001 /* Enable CLKOUT */ |