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-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h91
-rw-r--r--arch/blackfin/mach-bf533/include/mach/fio_flag.h55
-rw-r--r--arch/blackfin/mach-bf533/include/mach/pll.h57
3 files changed, 112 insertions, 91 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index feb2392c43ea..401e524f5321 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -7,11 +7,6 @@
7#ifndef _CDEF_BF532_H 7#ifndef _CDEF_BF532_H
8#define _CDEF_BF532_H 8#define _CDEF_BF532_H
9 9
10#include <asm/blackfin.h>
11
12/*include all Core registers and bit definitions*/
13#include "defBF532.h"
14
15/*include core specific register pointer definitions*/ 10/*include core specific register pointer definitions*/
16#include <asm/cdef_LPBlackfin.h> 11#include <asm/cdef_LPBlackfin.h>
17 12
@@ -655,90 +650,4 @@
655/* These need to be last due to the cdef/linux inter-dependencies */ 650/* These need to be last due to the cdef/linux inter-dependencies */
656#include <asm/irq.h> 651#include <asm/irq.h>
657 652
658#if ANOMALY_05000311
659#define BFIN_WRITE_FIO_FLAG(name) \
660static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
661{ \
662 unsigned long flags; \
663 local_irq_save_hw(flags); \
664 bfin_write16(FIO_FLAG_##name, val); \
665 bfin_read_CHIPID(); \
666 local_irq_restore_hw(flags); \
667}
668BFIN_WRITE_FIO_FLAG(D)
669BFIN_WRITE_FIO_FLAG(C)
670BFIN_WRITE_FIO_FLAG(S)
671BFIN_WRITE_FIO_FLAG(T)
672
673#define BFIN_READ_FIO_FLAG(name) \
674static inline u16 bfin_read_FIO_FLAG_##name(void) \
675{ \
676 unsigned long flags; \
677 u16 ret; \
678 local_irq_save_hw(flags); \
679 ret = bfin_read16(FIO_FLAG_##name); \
680 bfin_read_CHIPID(); \
681 local_irq_restore_hw(flags); \
682 return ret; \
683}
684BFIN_READ_FIO_FLAG(D)
685BFIN_READ_FIO_FLAG(C)
686BFIN_READ_FIO_FLAG(S)
687BFIN_READ_FIO_FLAG(T)
688
689#else
690#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
691#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
692#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
693#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
694#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
695#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
696#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
697#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
698#endif
699
700/* Writing to PLL_CTL initiates a PLL relock sequence. */
701static __inline__ void bfin_write_PLL_CTL(unsigned int val)
702{
703 unsigned long flags, iwr;
704
705 if (val == bfin_read_PLL_CTL())
706 return;
707
708 local_irq_save_hw(flags);
709 /* Enable the PLL Wakeup bit in SIC IWR */
710 iwr = bfin_read32(SIC_IWR);
711 /* Only allow PPL Wakeup) */
712 bfin_write32(SIC_IWR, IWR_ENABLE(0));
713
714 bfin_write16(PLL_CTL, val);
715 SSYNC();
716 asm("IDLE;");
717
718 bfin_write32(SIC_IWR, iwr);
719 local_irq_restore_hw(flags);
720}
721
722/* Writing to VR_CTL initiates a PLL relock sequence. */
723static __inline__ void bfin_write_VR_CTL(unsigned int val)
724{
725 unsigned long flags, iwr;
726
727 if (val == bfin_read_VR_CTL())
728 return;
729
730 local_irq_save_hw(flags);
731 /* Enable the PLL Wakeup bit in SIC IWR */
732 iwr = bfin_read32(SIC_IWR);
733 /* Only allow PPL Wakeup) */
734 bfin_write32(SIC_IWR, IWR_ENABLE(0));
735
736 bfin_write16(VR_CTL, val);
737 SSYNC();
738 asm("IDLE;");
739
740 bfin_write32(SIC_IWR, iwr);
741 local_irq_restore_hw(flags);
742}
743
744#endif /* _CDEF_BF532_H */ 653#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/fio_flag.h b/arch/blackfin/mach-bf533/include/mach/fio_flag.h
new file mode 100644
index 000000000000..d0bfba0b083b
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/fio_flag.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_FIO_FLAG_H
8#define _MACH_FIO_FLAG_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13#if ANOMALY_05000311
14#define BFIN_WRITE_FIO_FLAG(name) \
15static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
16{ \
17 unsigned long flags; \
18 flags = hard_local_irq_save(); \
19 bfin_write16(FIO_FLAG_##name, val); \
20 bfin_read_CHIPID(); \
21 hard_local_irq_restore(flags); \
22}
23BFIN_WRITE_FIO_FLAG(D)
24BFIN_WRITE_FIO_FLAG(C)
25BFIN_WRITE_FIO_FLAG(S)
26BFIN_WRITE_FIO_FLAG(T)
27
28#define BFIN_READ_FIO_FLAG(name) \
29static inline u16 bfin_read_FIO_FLAG_##name(void) \
30{ \
31 unsigned long flags; \
32 u16 ret; \
33 flags = hard_local_irq_save(); \
34 ret = bfin_read16(FIO_FLAG_##name); \
35 bfin_read_CHIPID(); \
36 hard_local_irq_restore(flags); \
37 return ret; \
38}
39BFIN_READ_FIO_FLAG(D)
40BFIN_READ_FIO_FLAG(C)
41BFIN_READ_FIO_FLAG(S)
42BFIN_READ_FIO_FLAG(T)
43
44#else
45#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
46#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
47#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
48#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
49#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
50#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
51#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
52#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
53#endif
54
55#endif /* _MACH_FIO_FLAG_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
new file mode 100644
index 000000000000..169c106d0edb
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/pll.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2005-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr = bfin_read32(SIC_IWR);
24 /* Only allow PPL Wakeup) */
25 bfin_write32(SIC_IWR, IWR_ENABLE(0));
26
27 bfin_write16(PLL_CTL, val);
28 SSYNC();
29 asm("IDLE;");
30
31 bfin_write32(SIC_IWR, iwr);
32 hard_local_irq_restore(flags);
33}
34
35/* Writing to VR_CTL initiates a PLL relock sequence. */
36static __inline__ void bfin_write_VR_CTL(unsigned int val)
37{
38 unsigned long flags, iwr;
39
40 if (val == bfin_read_VR_CTL())
41 return;
42
43 flags = hard_local_irq_save();
44 /* Enable the PLL Wakeup bit in SIC IWR */
45 iwr = bfin_read32(SIC_IWR);
46 /* Only allow PPL Wakeup) */
47 bfin_write32(SIC_IWR, IWR_ENABLE(0));
48
49 bfin_write16(VR_CTL, val);
50 SSYNC();
51 asm("IDLE;");
52
53 bfin_write32(SIC_IWR, iwr);
54 hard_local_irq_restore(flags);
55}
56
57#endif /* _MACH_PLL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-06 10:14:43 -0500