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-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h272
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bf533.h161
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h164
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_sir.h125
-rw-r--r--arch/blackfin/mach-bf533/include/mach/blackfin.h60
-rw-r--r--arch/blackfin/mach-bf533/include/mach/cdefBF532.h767
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h1266
-rw-r--r--arch/blackfin/mach-bf533/include/mach/dma.h54
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h173
-rw-r--r--arch/blackfin/mach-bf533/include/mach/mem_init.h297
-rw-r--r--arch/blackfin/mach-bf533/include/mach/mem_map.h171
-rw-r--r--arch/blackfin/mach-bf533/include/mach/portmux.h67
12 files changed, 3577 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
new file mode 100644
index 000000000000..8f7ea112fd3a
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -0,0 +1,272 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file shoule be up to date with:
10 * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.1 or 0.2 silicon - sorry */
17#if __SILICON_REVISION__ < 3
18# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
19#endif
20
21#if defined(__ADSPBF531__)
22# define ANOMALY_BF531 1
23#else
24# define ANOMALY_BF531 0
25#endif
26#if defined(__ADSPBF532__)
27# define ANOMALY_BF532 1
28#else
29# define ANOMALY_BF532 0
30#endif
31#if defined(__ADSPBF533__)
32# define ANOMALY_BF533 1
33#else
34# define ANOMALY_BF533 0
35#endif
36
37/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
38#define ANOMALY_05000074 (1)
39/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
40#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
41/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
42#define ANOMALY_05000105 (1)
43/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
44#define ANOMALY_05000119 (1)
45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
46#define ANOMALY_05000122 (1)
47/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
48#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
49/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
50#define ANOMALY_05000166 (1)
51/* Turning Serial Ports on with External Frame Syncs */
52#define ANOMALY_05000167 (1)
53/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
54#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
55/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
56#define ANOMALY_05000180 (1)
57/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
58#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
59/* False Protection Exceptions */
60#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
61/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
62#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
63/* Restarting SPORT in Specific Modes May Cause Data Corruption */
64#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
65/* Failing MMR Accesses When Stalled by Preceding Memory Read */
66#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
67/* Current DMA Address Shows Wrong Value During Carry Fix */
68#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
69/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
70#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
71/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
72#define ANOMALY_05000201 (__SILICON_REVISION__ < 4)
73/* Possible Infinite Stall with Specific Dual-DAG Situation */
74#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
75/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
76#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
77/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
78#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
79/* Recovery from "Brown-Out" Condition */
80#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
81/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
82#define ANOMALY_05000208 (1)
83/* Speed Path in Computational Unit Affects Certain Instructions */
84#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
85/* UART TX Interrupt Masked Erroneously */
86#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
87/* NMI Event at Boot Time Results in Unpredictable State */
88#define ANOMALY_05000219 (1)
89/* Incorrect Pulse-Width of UART Start Bit */
90#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
91/* Scratchpad Memory Bank Reads May Return Incorrect Data */
92#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
93/* SPI Slave Boot Mode Modifies Registers from Reset Value */
94#define ANOMALY_05000229 (1)
95/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
96#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
97/* UART STB Bit Incorrectly Affects Receiver Setting */
98#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
99/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
100#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
101/* Incorrect Revision Number in DSPID Register */
102#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
103/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
104#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
105/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
106#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
107/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
108#define ANOMALY_05000245 (1)
109/* Data CPLBs Should Prevent Spurious Hardware Errors */
110#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
111/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
112#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
113/* Maximum External Clock Speed for Timers */
114#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
115/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
116#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
117/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
118#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
119/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
120#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
121/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
122#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
123/* ICPLB_STATUS MMR Register May Be Corrupted */
124#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
125/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
126#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
127/* Stores To Data Cache May Be Lost */
128#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
129/* Hardware Loop Corrupted When Taking an ICPLB Exception */
130#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
131/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
132#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
133/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
134#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
135/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
136#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
137/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
138#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
139/* Spontaneous Reset of Internal Voltage Regulator */
140#define ANOMALY_05000271 (__SILICON_REVISION__ < 4)
141/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
142#define ANOMALY_05000272 (1)
143/* Writes to Synchronous SDRAM Memory May Be Lost */
144#define ANOMALY_05000273 (1)
145/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
146#define ANOMALY_05000276 (1)
147/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
148#define ANOMALY_05000277 (1)
149/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
150#define ANOMALY_05000278 (1)
151/* False Hardware Error Exception When ISR Context Is Not Restored */
152#define ANOMALY_05000281 (1)
153/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
154#define ANOMALY_05000282 (1)
155/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
156#define ANOMALY_05000283 (1)
157/* SPORTs May Receive Bad Data If FIFOs Fill Up */
158#define ANOMALY_05000288 (1)
159/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
160#define ANOMALY_05000301 (1)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
167/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
168#define ANOMALY_05000310 (1)
169/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
170#define ANOMALY_05000311 (1)
171/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
172#define ANOMALY_05000312 (1)
173/* PPI Is Level-Sensitive on First Transfer */
174#define ANOMALY_05000313 (1)
175/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
176#define ANOMALY_05000315 (1)
177/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
178#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
179/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
180#define ANOMALY_05000357 (1)
181/* UART Break Signal Issues */
182#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
183/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
184#define ANOMALY_05000366 (1)
185/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
186#define ANOMALY_05000371 (1)
187/* PPI Does Not Start Properly In Specific Mode */
188#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
189/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
190#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
191/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
192#define ANOMALY_05000403 (1)
193
194
195/* These anomalies have been "phased" out of analog.com anomaly sheets and are
196 * here to show running on older silicon just isn't feasible.
197 */
198
199/* Watchpoints (Hardware Breakpoints) are not supported */
200#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
201/* Reserved bits in SYSCFG register not set at power on */
202#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
203/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
204#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
205/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
206#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
207/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
208#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
209/* Erroneous exception when enabling cache */
210#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
211/* SPI clock polarity and phase bits incorrect during booting */
212#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
213/* DMEM_CONTROL is not set on Reset */
214#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
215/* SPI boot will not complete if there is a zero fill block in the loader file */
216#define ANOMALY_05000138 (__SILICON_REVISION__ < 3)
217/* Allowing the SPORT RX FIFO to fill will cause an overflow */
218#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
219/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
220#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
221/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
222#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
223/* A read from external memory may return a wrong value with data cache enabled */
224#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
225/* DMA and TESTSET conflict when both are accessing external memory */
226#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
227/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
228#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
229/* MDMA may lose the first few words of a descriptor chain */
230#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
231/* The source MDMA descriptor may stop with a DMA Error */
232#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
233/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
234#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
235/* Frame Delay in SPORT Multichannel Mode */
236#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
237/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */
238#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
239/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
240#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
241/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */
242#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
243/* SPORT transmit data is not gated by external frame sync in certain conditions */
244#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
245/* SDRAM auto-refresh and subsequent Power Ups */
246#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
247/* DATA CPLB page miss can result in lost write-through cache data writes */
248#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
249/* DMA vs Core accesses to external memory */
250#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
251/* Cache Fill Buffer Data lost */
252#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
253/* Overlapping Sequencer and Memory Stalls */
254#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
255/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
256#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
257/* Disabling the PPI resets the PPI configuration registers */
258#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
259/* PPI TX Mode with 2 External Frame Syncs */
260#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
261/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
262#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
263/* In PPI Transmit Modes with External Frame Syncs POLC */
264#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
265/* Internal Voltage Regulator may not start up */
266#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
267
268/* Anomalies that don't exist on this proc */
269#define ANOMALY_05000266 (0)
270#define ANOMALY_05000323 (0)
271
272#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h
new file mode 100644
index 000000000000..12a416931991
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bf533.h
@@ -0,0 +1,161 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/bf533.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF533_H__
31#define __MACH_BF533_H__
32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54
55#define BFIN_DSUBBANKS 4
56#define BFIN_DWAYS 2
57#define BFIN_DLINES 64
58#define BFIN_ISUBBANKS 4
59#define BFIN_IWAYS 4
60#define BFIN_ILINES 32
61
62#define WAY0_L 0x1
63#define WAY1_L 0x2
64#define WAY01_L 0x3
65#define WAY2_L 0x4
66#define WAY02_L 0x5
67#define WAY12_L 0x6
68#define WAY012_L 0x7
69
70#define WAY3_L 0x8
71#define WAY03_L 0x9
72#define WAY13_L 0xA
73#define WAY013_L 0xB
74
75#define WAY32_L 0xC
76#define WAY320_L 0xD
77#define WAY321_L 0xE
78#define WAYALL_L 0xF
79
80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
81
82/* IAR0 BIT FIELDS*/
83#define RTC_ERROR_BIT 0x0FFFFFFF
84#define UART_ERROR_BIT 0xF0FFFFFF
85#define SPORT1_ERROR_BIT 0xFF0FFFFF
86#define SPI_ERROR_BIT 0xFFF0FFFF
87#define SPORT0_ERROR_BIT 0xFFFF0FFF
88#define PPI_ERROR_BIT 0xFFFFF0FF
89#define DMA_ERROR_BIT 0xFFFFFF0F
90#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
91
92/* IAR1 BIT FIELDS*/
93#define DMA7_UARTTX_BIT 0x0FFFFFFF
94#define DMA6_UARTRX_BIT 0xF0FFFFFF
95#define DMA5_SPI_BIT 0xFF0FFFFF
96#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
97#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
98#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
99#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
100#define DMA0_PPI_BIT 0xFFFFFFFF
101
102/* IAR2 BIT FIELDS*/
103#define WDTIMER_BIT 0x0FFFFFFF
104#define MEMDMA1_BIT 0xF0FFFFFF
105#define MEMDMA0_BIT 0xFF0FFFFF
106#define PFB_BIT 0xFFF0FFFF
107#define PFA_BIT 0xFFFF0FFF
108#define TIMER2_BIT 0xFFFFF0FF
109#define TIMER1_BIT 0xFFFFFF0F
110#define TIMER0_BIT 0xFFFFFFFF
111
112/********************************* EBIU Settings ************************************/
113#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
114#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
115
116#ifdef CONFIG_C_AMBEN_ALL
117#define V_AMBEN AMBEN_ALL
118#endif
119#ifdef CONFIG_C_AMBEN
120#define V_AMBEN 0x0
121#endif
122#ifdef CONFIG_C_AMBEN_B0
123#define V_AMBEN AMBEN_B0
124#endif
125#ifdef CONFIG_C_AMBEN_B0_B1
126#define V_AMBEN AMBEN_B0_B1
127#endif
128#ifdef CONFIG_C_AMBEN_B0_B1_B2
129#define V_AMBEN AMBEN_B0_B1_B2
130#endif
131#ifdef CONFIG_C_AMCKEN
132#define V_AMCKEN AMCKEN
133#else
134#define V_AMCKEN 0x0
135#endif
136#ifdef CONFIG_C_CDPRIO
137#define V_CDPRIO 0x100
138#else
139#define V_CDPRIO 0x0
140#endif
141
142#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
143
144#ifdef CONFIG_BF533
145#define CPU "BF533"
146#define CPUID 0x027a5000
147#endif
148#ifdef CONFIG_BF532
149#define CPU "BF532"
150#define CPUID 0x0275A000
151#endif
152#ifdef CONFIG_BF531
153#define CPU "BF531"
154#define CPUID 0x027a5000
155#endif
156#ifndef CPU
157#define CPU "UNKNOWN"
158#define CPUID 0x0
159#endif
160
161#endif /* __MACH_BF533_H__ */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
new file mode 100644
index 000000000000..ebf592b59aab
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -0,0 +1,164 @@
1/*
2 * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#include <linux/serial.h>
33#include <asm/dma.h>
34#include <asm/portmux.h>
35
36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
56#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
57#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
58#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
59#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
60#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
61
62#ifdef CONFIG_BFIN_UART0_CTSRTS
63# define CONFIG_SERIAL_BFIN_CTSRTS
64# ifndef CONFIG_UART0_CTS_PIN
65# define CONFIG_UART0_CTS_PIN -1
66# endif
67# ifndef CONFIG_UART0_RTS_PIN
68# define CONFIG_UART0_RTS_PIN -1
69# endif
70#endif
71
72struct bfin_serial_port {
73 struct uart_port port;
74 unsigned int old_status;
75 unsigned int lsr;
76#ifdef CONFIG_SERIAL_BFIN_DMA
77 int tx_done;
78 int tx_count;
79 struct circ_buf rx_dma_buf;
80 struct timer_list rx_dma_timer;
81 int rx_dma_nrows;
82 unsigned int tx_dma_channel;
83 unsigned int rx_dma_channel;
84 struct work_struct tx_dma_workqueue;
85#else
86# if ANOMALY_05000230
87 unsigned int anomaly_threshold;
88# endif
89#endif
90#ifdef CONFIG_SERIAL_BFIN_CTSRTS
91 struct timer_list cts_timer;
92 int cts_pin;
93 int rts_pin;
94#endif
95};
96
97/* The hardware clears the LSR bits upon read, so we need to cache
98 * some of the more fun bits in software so they don't get lost
99 * when checking the LSR in other code paths (TX).
100 */
101static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
102{
103 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
104 uart->lsr |= (lsr & (BI|FE|PE|OE));
105 return lsr | uart->lsr;
106}
107
108static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
109{
110 uart->lsr = 0;
111 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
112}
113
114struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
115struct bfin_serial_res {
116 unsigned long uart_base_addr;
117 int uart_irq;
118#ifdef CONFIG_SERIAL_BFIN_DMA
119 unsigned int uart_tx_dma_channel;
120 unsigned int uart_rx_dma_channel;
121#endif
122#ifdef CONFIG_SERIAL_BFIN_CTSRTS
123 int uart_cts_pin;
124 int uart_rts_pin;
125#endif
126};
127
128struct bfin_serial_res bfin_serial_resource[] = {
129 {
130 0xFFC00400,
131 IRQ_UART_RX,
132#ifdef CONFIG_SERIAL_BFIN_DMA
133 CH_UART_TX,
134 CH_UART_RX,
135#endif
136#ifdef CONFIG_BFIN_UART0_CTSRTS
137 CONFIG_UART0_CTS_PIN,
138 CONFIG_UART0_RTS_PIN,
139#endif
140 }
141};
142
143#define DRIVER_NAME "bfin-uart"
144
145int nr_ports = BFIN_UART_NR_PORTS;
146static void bfin_serial_hw_init(struct bfin_serial_port *uart)
147{
148
149#ifdef CONFIG_SERIAL_BFIN_UART0
150 peripheral_request(P_UART0_TX, DRIVER_NAME);
151 peripheral_request(P_UART0_RX, DRIVER_NAME);
152#endif
153
154#ifdef CONFIG_SERIAL_BFIN_CTSRTS
155 if (uart->cts_pin >= 0) {
156 gpio_request(uart->cts_pin, DRIVER_NAME);
157 gpio_direction_input(uart->cts_pin);
158 }
159 if (uart->rts_pin >= 0) {
160 gpio_request(uart->rts_pin, DRIVER_NAME);
161 gpio_direction_input(uart->rts_pin, 0);
162 }
163#endif
164}
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_sir.h b/arch/blackfin/mach-bf533/include/mach/bfin_sir.h
new file mode 100644
index 000000000000..9bb87e9e2e9b
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_sir.h
@@ -0,0 +1,125 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static int bfin_sir_hw_init(void)
114{
115 int ret = -ENODEV;
116#ifdef CONFIG_BFIN_SIR0
117 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
118 if (ret)
119 return ret;
120 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
121 if (ret)
122 return ret;
123#endif
124 return ret;
125}
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
new file mode 100644
index 000000000000..d80971b4e3aa
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -0,0 +1,60 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MACH_BLACKFIN_H_
32#define _MACH_BLACKFIN_H_
33
34#define BF533_FAMILY
35
36#include "bf533.h"
37#include "mem_map.h"
38#include "defBF532.h"
39#include "anomaly.h"
40
41#if !defined(__ASSEMBLY__)
42#include "cdefBF532.h"
43#endif
44
45#define BFIN_UART_NR_PORTS 1
46
47#define OFFSET_THR 0x00 /* Transmit Holding register */
48#define OFFSET_RBR 0x00 /* Receive Buffer register */
49#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
50#define OFFSET_IER 0x04 /* Interrupt Enable Register */
51#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
52#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
53#define OFFSET_LCR 0x0C /* Line Control Register */
54#define OFFSET_MCR 0x10 /* Modem Control Register */
55#define OFFSET_LSR 0x14 /* Line Status Register */
56#define OFFSET_MSR 0x18 /* Modem Status Register */
57#define OFFSET_SCR 0x1C /* SCR Scratch Register */
58#define OFFSET_GCTL 0x24 /* Global Control Register */
59
60#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
new file mode 100644
index 000000000000..3d8978a52c17
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -0,0 +1,767 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/cdefBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF532_H
32#define _CDEF_BF532_H
33
34#include <asm/blackfin.h>
35
36/*include all Core registers and bit definitions*/
37#include "defBF532.h"
38
39/*include core specific register pointer definitions*/
40#include <asm/cdef_LPBlackfin.h>
41
42#include <asm/system.h>
43
44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr = bfin_read32(SIC_IWR);
57 /* Only allow PPL Wakeup) */
58 bfin_write32(SIC_IWR, IWR_ENABLE(0));
59
60 bfin_write16(PLL_CTL, val);
61 SSYNC();
62 asm("IDLE;");
63
64 bfin_write32(SIC_IWR, iwr);
65 local_irq_restore(flags);
66}
67#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
68#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
69#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
70#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
71#define bfin_read_CHIPID() bfin_read32(CHIPID)
72#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
73#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
74#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
75/* Writing to VR_CTL initiates a PLL relock sequence. */
76static __inline__ void bfin_write_VR_CTL(unsigned int val)
77{
78 unsigned long flags, iwr;
79
80 if (val == bfin_read_VR_CTL())
81 return;
82
83 local_irq_save(flags);
84 /* Enable the PLL Wakeup bit in SIC IWR */
85 iwr = bfin_read32(SIC_IWR);
86 /* Only allow PPL Wakeup) */
87 bfin_write32(SIC_IWR, IWR_ENABLE(0));
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR, iwr);
94 local_irq_restore(flags);
95}
96
97/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
98#define bfin_read_SWRST() bfin_read16(SWRST)
99#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
100#define bfin_read_SYSCR() bfin_read16(SYSCR)
101#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
102#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
103#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
104#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
105#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
106#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
107#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
108#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
109#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
110#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
111#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
112#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
113#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
114#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
115#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
116
117/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
118#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
119#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
120#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
121#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
122#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
123#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
124
125/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
126#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
127#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
128#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
129#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
130#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
131#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
132#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
133#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
134#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
135#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
136#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
137#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
138#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
139#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
140
141/* DMA Traffic controls */
142#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
143#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
144#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
145#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
146
147/* Alternate deprecated register names (below) provided for backwards code compatibility */
148#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
149#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
150#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
151#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
152
153/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
154#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
155#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
156#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
157#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
158#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
159#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
160#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
161#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
162#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
163#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
164#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
165#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
166#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
167#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
168#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
169#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
170#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
171#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
172#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
173#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
174#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
175#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
176#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
177#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
178#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
179#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
180
181
182#if ANOMALY_05000311
183#define BFIN_WRITE_FIO_FLAG(name) \
184static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\
185{\
186 unsigned long flags;\
187 local_irq_save(flags);\
188 bfin_write16(FIO_FLAG_ ## name,val);\
189 bfin_read_CHIPID();\
190 local_irq_restore(flags);\
191}
192BFIN_WRITE_FIO_FLAG(D)
193BFIN_WRITE_FIO_FLAG(C)
194BFIN_WRITE_FIO_FLAG(S)
195BFIN_WRITE_FIO_FLAG(T)
196
197#define BFIN_READ_FIO_FLAG(name) \
198static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\
199{\
200 unsigned long flags;\
201 unsigned short ret;\
202 local_irq_save(flags);\
203 ret = bfin_read16(FIO_FLAG_ ## name);\
204 bfin_read_CHIPID();\
205 local_irq_restore(flags);\
206 return ret;\
207}
208BFIN_READ_FIO_FLAG(D)
209BFIN_READ_FIO_FLAG(C)
210BFIN_READ_FIO_FLAG(S)
211BFIN_READ_FIO_FLAG(T)
212
213#else
214#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val)
215#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val)
216#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val)
217#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val)
218#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
219#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
220#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
221#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
222#endif
223
224
225/* DMA Controller */
226#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
227#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
228#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
229#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
230#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
231#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
232#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
233#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
234#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
235#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
236#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
237#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
238#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
239#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
240#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
241#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
242#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
243#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
244#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
245#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
246#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
247#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
248#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
249#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
250#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
251#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
252
253#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
254#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
255#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
256#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
257#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
258#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
259#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
260#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
261#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
262#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
263#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
264#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
265#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
266#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
267#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
268#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
269#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
270#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
271#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
272#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
273#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
274#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
275#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
276#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
277#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
278#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
279
280#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
281#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
282#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
283#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
284#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
285#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
286#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
287#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
288#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
289#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
290#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
291#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
292#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
293#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
294#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
295#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
296#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
297#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
298#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
299#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
300#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
301#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
302#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
303#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
304#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
305#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
306
307#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
308#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
309#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
310#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
311#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
312#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
313#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
314#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
315#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
316#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
317#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
318#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
319#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
320#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
321#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
322#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
323#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
324#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
325#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
326#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
327#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
328#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
329#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
330#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
331#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
332#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
333
334#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
335#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
336#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
337#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
338#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
339#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
340#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
341#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
342#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
343#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
344#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
345#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
346#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
347#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
348#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
349#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
350#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
351#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
352#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
353#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
354#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
355#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
356#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
357#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
358#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
359#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
360
361#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
362#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
363#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
364#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
365#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
366#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
367#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
368#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
369#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
370#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
371#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
372#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
373#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
374#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
375#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
376#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
377#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
378#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
379#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
380#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
381#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
382#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
383#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
384#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
385#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
386#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
387
388#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
389#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
390#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
391#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
392#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
393#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
394#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
395#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
396#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
397#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
398#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
399#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
400#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
401#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
402#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
403#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
404#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
405#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
406#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
407#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
408#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
409#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
410#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
411#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
412#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
413#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
414
415#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
416#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
417#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
418#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
419#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
420#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
421#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
422#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
423#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
424#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
425#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
426#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
427#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
428#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
429#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
430#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
431#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
432#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
433#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
434#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
435#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
436#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
437#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
438#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
439#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
440#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
441
442#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
443#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
444#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
445#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
446#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
447#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
448#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
449#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
450#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
451#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
452#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
453#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
454#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
455#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
456#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
457#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
458#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
459#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
460#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
461#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
462#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
463#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
464#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
465#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
466#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
467#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
468
469#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
470#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
471#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
472#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
473#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
474#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
475#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
476#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
477#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
478#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
479#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
480#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
481#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
482#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
483#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
484#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
485#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
486#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
487#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
488#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
489#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
490#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
491#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
492#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
493#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
494#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
495
496#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
497#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
498#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
499#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
500#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
501#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
502#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
503#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
504#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
505#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
506#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
507#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
508#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
509#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
510#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
511#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
512#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
513#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
514#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
515#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
516#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
517#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
518#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
519#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
520#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
521#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
522
523#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
524#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
525#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
526#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
527#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
528#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
529#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
530#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
531#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
532#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
533#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
534#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
535#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
536#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
537#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
538#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
539#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
540#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
541#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
542#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
543#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
544#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
545#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
546#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
547#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
548#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
549
550/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
551#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
552#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
553#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
554#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
555#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
556#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
557
558/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
559#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
560#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
561#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
562#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
563#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
564#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
565#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
566#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
567
568/* UART Controller */
569#define bfin_read_UART_THR() bfin_read16(UART_THR)
570#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
571#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
572#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
573#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
574#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
575#define bfin_read_UART_IER() bfin_read16(UART_IER)
576#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
577#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
578#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
579#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
580#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
581#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
582#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
583#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
584#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
585#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
586#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
587/*
588#define UART_MSR
589*/
590#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
591#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
592#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
593#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
594
595/* SPI Controller */
596#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
597#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
598#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
599#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
600#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
601#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
602#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
603#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
604#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
605#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
606#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
607#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
608#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
609#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
610
611/* TIMER 0, 1, 2 Registers */
612#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
613#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
614#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
615#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
616#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
617#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
618#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
619#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
620
621#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
622#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
623#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
624#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
625#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
626#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
627#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
628#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
629
630#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
631#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
632#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
633#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
634#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
635#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
636#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
637#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
638
639#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
640#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
641#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
642#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
643#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
644#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
645
646/* SPORT0 Controller */
647#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
648#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
649#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
650#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
651#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
652#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
653#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
654#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
655#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
656#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
657#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
658#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
659#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
660#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
661#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
662#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
663#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
664#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
665#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
666#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
667#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
668#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
669#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
670#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
671#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
672#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
673#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
674#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
675#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
676#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
677#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
678#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
679#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
680#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
681#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
682#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
683#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
684#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
685#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
686#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
687#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
688#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
689#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
690#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
691#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
692#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
693#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
694#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
695#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
696#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
697#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
698#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
699
700/* SPORT1 Controller */
701#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
702#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
703#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
704#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
705#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
706#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
707#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
708#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
709#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
710#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
711#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
712#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
713#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
714#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
715#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
716#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
717#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
718#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
719#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
720#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
721#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
722#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
723#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
724#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
725#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
726#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
727#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
728#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
729#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
730#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
731#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
732#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
733#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
734#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
735#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
736#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
737#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
738#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
739#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
740#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
741#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
742#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
743#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
744#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
745#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
746#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
747#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
748#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
749#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
750#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
751#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
752#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
753
754/* Parallel Peripheral Interface (PPI) */
755#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
756#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
757#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
758#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
759#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
760#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
761#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
762#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
763#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
764#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
765#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
766
767#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
new file mode 100644
index 000000000000..7f4633223e6d
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -0,0 +1,1266 @@
1/************************************************************************
2 *
3 * This file is subject to the terms and conditions of the GNU Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Non-GPL License also available as part of VisualDSP++
8 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
9 *
10 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
11 *
12 * This file under source code control, please send bugs or changes to:
13 * dsptools.support@analog.com
14 *
15 ************************************************************************/
16/*
17 * File: include/asm-blackfin/mach-bf533/defBF532.h
18 * Based on:
19 * Author:
20 *
21 * Created:
22 * Description:
23 *
24 * Rev:
25 *
26 * Modified:
27 *
28 * Bugs: Enter bugs at http://blackfin.uclinux.org/
29 *
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2, or (at your option)
33 * any later version.
34 *
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; see the file COPYING.
42 * If not, write to the Free Software Foundation,
43 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
44 */
45/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
46
47#ifndef _DEF_BF532_H
48#define _DEF_BF532_H
49
50/* include all Core registers and bit definitions */
51#include <asm/def_LPBlackfin.h>
52
53/*********************************************************************************** */
54/* System MMR Register Map */
55/*********************************************************************************** */
56/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
57
58#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
59#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
60#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
61#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
62#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
63#define CHIPID 0xFFC00014 /* Chip ID Register */
64
65/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
66#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
67#define SYSCR 0xFFC00104 /* System Configuration registe */
68#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
69#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
70#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
71#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
72#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
73#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
74#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
75
76/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
77#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
78#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
79#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
80
81/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
82#define RTC_STAT 0xFFC00300 /* RTC Status Register */
83#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
84#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
85#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
86#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
87#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
88#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
89
90/* UART Controller (0xFFC00400 - 0xFFC004FF) */
91
92/*
93 * Because include/linux/serial_reg.h have defined UART_*,
94 * So we define blackfin uart regs to BFIN_UART_*.
95 */
96#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
97#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
98#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
99#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
100#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
101#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
102#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
103#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
104#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
105#if 0
106#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
107#endif
108#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
109#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
110
111/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
112#define SPI0_REGBASE 0xFFC00500
113#define SPI_CTL 0xFFC00500 /* SPI Control Register */
114#define SPI_FLG 0xFFC00504 /* SPI Flag register */
115#define SPI_STAT 0xFFC00508 /* SPI Status register */
116#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
117#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
118#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
119#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
120
121/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
122
123#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
124#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
125#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
126#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
127
128#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
129#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
130#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
131#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
132
133#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
134#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
135#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
136#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
137
138#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
139#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
140#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
141
142/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
143
144#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
145#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
146#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
147#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
148#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
149#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
150#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
151#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
152#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
153#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
154#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
155#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
156#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
157#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
158#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
159#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
160#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
161
162/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
163#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
164#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
165#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
166#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
167#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
168#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
169#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
170#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
171#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
172#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
173#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
174#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
175#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
176#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
177#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
178#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
179#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
180#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
181#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
182#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
183#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
184#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
185
186/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
187#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
188#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
189#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
190#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
191#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
192#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
193#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
194#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
195#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
196#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
197#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
198#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
199#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
200#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
201#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
202#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
203#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
204#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
205#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
206#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
207#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
208#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
209
210/* Asynchronous Memory Controller - External Bus Interface Unit */
211#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
212#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
213#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
214
215/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
216
217#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
218#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
219#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
220#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
221
222/* DMA Traffic controls */
223#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
224#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
225
226/* Alternate deprecated register names (below) provided for backwards code compatibility */
227#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
228#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
229
230/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
231#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
232#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
233#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
234#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
235#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
236#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
237#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
238#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
239#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
240#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
241#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
242#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
243#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
244
245#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
246#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
247#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
248#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
249#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
250#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
251#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
252#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
253#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
254#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
255#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
256#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
257#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
258
259#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
260#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
261#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
262#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
263#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
264#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
265#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
266#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
267#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
268#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
269#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
270#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
271#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
272
273#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
274#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
275#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
276#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
277#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
278#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
279#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
280#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
281#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
282#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
283#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
284#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
285#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
286
287#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
288#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
289#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
290#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
291#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
292#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
293#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
294#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
295#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
296#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
297#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
298#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
299#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
300
301#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
302#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
303#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
304#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
305#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
306#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
307#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
308#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
309#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
310#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
311#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
312#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
313#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
314
315#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
316#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
317#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
318#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
319#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
320#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
321#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
322#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
323#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
324#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
325#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
326#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
327#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
328
329#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
330#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
331#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
332#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
333#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
334#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
335#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
336#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
337#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
338#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
339#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
340#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
341#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
342
343#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
344#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
345#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
346#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
347#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
348#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
349#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
350#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
351#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
352#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
353#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
354#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
355#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
356
357#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
358#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
359#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
360#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
361#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
362#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
363#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
364#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
365#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
366#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
367#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
368#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
369#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
370
371#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
372#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
373#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
374#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
375#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
376#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
377#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
378#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
379#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
380#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
381#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
382#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
383#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
384
385#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
386#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
387#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
388#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
389#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
390#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
391#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
392#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
393#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
394#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
395#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
396#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
397#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
398
399/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
400
401#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
402#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
403#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
404#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
405#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
406
407/*********************************************************************************** */
408/* System MMR Register Bits */
409/******************************************************************************* */
410
411/* ********************* PLL AND RESET MASKS ************************ */
412
413/* PLL_CTL Masks */
414#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
415#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
416#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
417#define PLL_OFF 0x0002 /* Shut off PLL clocks */
418#define STOPCK_OFF 0x0008 /* Core clock off */
419#define STOPCK 0x0008 /* Core Clock Off */
420#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
421#if !defined(__ADSPBF538__)
422/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
423# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
424# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
425#endif
426#define BYPASS 0x0100 /* Bypass the PLL */
427/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
428#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
429
430/* PLL_DIV Masks */
431#define SSEL 0x000F /* System Select */
432#define CSEL 0x0030 /* Core Select */
433
434#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
435
436#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
437#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
438#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
439#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
440/* PLL_DIV Macros */
441#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
442
443/* PLL_STAT Masks */
444#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
445#define FULL_ON 0x0002 /* Processor In Full On Mode */
446#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
447#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
448
449/* VR_CTL Masks */
450#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
451#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
452#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
453#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
454#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
455
456#define GAIN 0x000C /* Voltage Level Gain */
457#define GAIN_5 0x0000 /* GAIN = 5 */
458#define GAIN_10 0x0004 /* GAIN = 10 */
459#define GAIN_20 0x0008 /* GAIN = 20 */
460#define GAIN_50 0x000C /* GAIN = 50 */
461
462#define VLEV 0x00F0 /* Internal Voltage Level */
463#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
464#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
465#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
466#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
467#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
468#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
469#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
470#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
471#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
472#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
473
474#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
475#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
476
477/* CHIPID Masks */
478#define CHIPID_VERSION 0xF0000000
479#define CHIPID_FAMILY 0x0FFFF000
480#define CHIPID_MANUFACTURE 0x00000FFE
481
482/* SWRST Mask */
483#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
484#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
485#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
486#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
487#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
488
489/* SYSCR Masks */
490#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
491#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
492
493/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
494
495 /* SIC_IAR0 Masks */
496
497#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
498#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
499#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
500#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
501#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
502#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
503#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
504#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
505
506/* SIC_IAR1 Masks */
507
508#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
509#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
510#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
511#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
512#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
513#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
514#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
515#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
516
517/* SIC_IAR2 Masks */
518#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
519#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
520#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
521#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
522#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
523#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
524#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
525#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
526
527/* SIC_IMASK Masks */
528#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
529#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
530#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
531#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
532
533/* SIC_IWR Masks */
534#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
535#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
536#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
537#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
538
539/* ***************************** UART CONTROLLER MASKS ********************** */
540
541/* UART_LCR Register */
542
543#define DLAB 0x80
544#define SB 0x40
545#define STP 0x20
546#define EPS 0x10
547#define PEN 0x08
548#define STB 0x04
549#define WLS(x) ((x-5) & 0x03)
550
551#define DLAB_P 0x07
552#define SB_P 0x06
553#define STP_P 0x05
554#define EPS_P 0x04
555#define PEN_P 0x03
556#define STB_P 0x02
557#define WLS_P1 0x01
558#define WLS_P0 0x00
559
560/* UART_MCR Register */
561#define LOOP_ENA 0x10
562#define LOOP_ENA_P 0x04
563
564/* UART_LSR Register */
565#define TEMT 0x40
566#define THRE 0x20
567#define BI 0x10
568#define FE 0x08
569#define PE 0x04
570#define OE 0x02
571#define DR 0x01
572
573#define TEMP_P 0x06
574#define THRE_P 0x05
575#define BI_P 0x04
576#define FE_P 0x03
577#define PE_P 0x02
578#define OE_P 0x01
579#define DR_P 0x00
580
581/* UART_IER Register */
582#define ELSI 0x04
583#define ETBEI 0x02
584#define ERBFI 0x01
585
586#define ELSI_P 0x02
587#define ETBEI_P 0x01
588#define ERBFI_P 0x00
589
590/* UART_IIR Register */
591#define STATUS(x) ((x << 1) & 0x06)
592#define NINT 0x01
593#define STATUS_P1 0x02
594#define STATUS_P0 0x01
595#define NINT_P 0x00
596#define IIR_TX_READY 0x02 /* UART_THR empty */
597#define IIR_RX_READY 0x04 /* Receive data ready */
598#define IIR_LINE_CHANGE 0x06 /* Receive line status */
599#define IIR_STATUS 0x06
600
601/* UART_GCTL Register */
602#define FFE 0x20
603#define FPE 0x10
604#define RPOLC 0x08
605#define TPOLC 0x04
606#define IREN 0x02
607#define UCEN 0x01
608
609#define FFE_P 0x05
610#define FPE_P 0x04
611#define RPOLC_P 0x03
612#define TPOLC_P 0x02
613#define IREN_P 0x01
614#define UCEN_P 0x00
615
616/* ********** SERIAL PORT MASKS ********************** */
617
618/* SPORTx_TCR1 Masks */
619#define TSPEN 0x0001 /* TX enable */
620#define ITCLK 0x0002 /* Internal TX Clock Select */
621#define TDTYPE 0x000C /* TX Data Formatting Select */
622#define DTYPE_NORM 0x0000 /* Data Format Normal */
623#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
624#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
625#define TLSBIT 0x0010 /* TX Bit Order */
626#define ITFS 0x0200 /* Internal TX Frame Sync Select */
627#define TFSR 0x0400 /* TX Frame Sync Required Select */
628#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
629#define LTFS 0x1000 /* Low TX Frame Sync Select */
630#define LATFS 0x2000 /* Late TX Frame Sync Select */
631#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
632
633/* SPORTx_TCR2 Masks */
634#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
635 defined(__ADSPBF533__)
636# define SLEN 0x001F /*TX Word Length */
637#else
638# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
639#endif
640#define TXSE 0x0100 /*TX Secondary Enable */
641#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
642#define TRFST 0x0400 /*TX Right-First Data Order */
643
644/* SPORTx_RCR1 Masks */
645#define RSPEN 0x0001 /* RX enable */
646#define IRCLK 0x0002 /* Internal RX Clock Select */
647#define RDTYPE 0x000C /* RX Data Formatting Select */
648#define DTYPE_NORM 0x0000 /* no companding */
649#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
650#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
651#define RLSBIT 0x0010 /* RX Bit Order */
652#define IRFS 0x0200 /* Internal RX Frame Sync Select */
653#define RFSR 0x0400 /* RX Frame Sync Required Select */
654#define LRFS 0x1000 /* Low RX Frame Sync Select */
655#define LARFS 0x2000 /* Late RX Frame Sync Select */
656#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
657
658/* SPORTx_RCR2 Masks */
659/* SLEN defined above */
660#define RXSE 0x0100 /*RX Secondary Enable */
661#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
662#define RRFST 0x0400 /*Right-First Data Order */
663
664/*SPORTx_STAT Masks */
665#define RXNE 0x0001 /*RX FIFO Not Empty Status */
666#define RUVF 0x0002 /*RX Underflow Status */
667#define ROVF 0x0004 /*RX Overflow Status */
668#define TXF 0x0008 /*TX FIFO Full Status */
669#define TUVF 0x0010 /*TX Underflow Status */
670#define TOVF 0x0020 /*TX Overflow Status */
671#define TXHRE 0x0040 /*TX Hold Register Empty */
672
673/*SPORTx_MCMC1 Masks */
674#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
675#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
676/* SPORTx_MCMC1 Macros */
677#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
678/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
679#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
680
681/*SPORTx_MCMC2 Masks */
682#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
683#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
684#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
685#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
686#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
687#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
688#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
689#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
690#define MFD 0x0000F000 /*Multichannel Frame Delay */
691#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
692#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
693#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
694#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
695#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
696#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
697#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
698#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
699#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
700#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
701#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
702#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
703#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
704#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
705#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
706#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
707
708/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
709
710/* PPI_CONTROL Masks */
711#define PORT_EN 0x00000001 /* PPI Port Enable */
712#define PORT_DIR 0x00000002 /* PPI Port Direction */
713#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
714#define PORT_CFG 0x00000030 /* PPI Port Configuration */
715#define FLD_SEL 0x00000040 /* PPI Active Field Select */
716#define PACK_EN 0x00000080 /* PPI Packing Mode */
717#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
718#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
719#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
720#define DLENGTH 0x00003800 /* PPI Data Length */
721#define DLEN_8 0x0000 /* Data Length = 8 Bits */
722#define DLEN_10 0x0800 /* Data Length = 10 Bits */
723#define DLEN_11 0x1000 /* Data Length = 11 Bits */
724#define DLEN_12 0x1800 /* Data Length = 12 Bits */
725#define DLEN_13 0x2000 /* Data Length = 13 Bits */
726#define DLEN_14 0x2800 /* Data Length = 14 Bits */
727#define DLEN_15 0x3000 /* Data Length = 15 Bits */
728#define DLEN_16 0x3800 /* Data Length = 16 Bits */
729#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
730#define POL 0x0000C000 /* PPI Signal Polarities */
731#define POLC 0x4000 /* PPI Clock Polarity */
732#define POLS 0x8000 /* PPI Frame Sync Polarity */
733
734/* PPI_STATUS Masks */
735#define FLD 0x00000400 /* Field Indicator */
736#define FT_ERR 0x00000800 /* Frame Track Error */
737#define OVR 0x00001000 /* FIFO Overflow Error */
738#define UNDR 0x00002000 /* FIFO Underrun Error */
739#define ERR_DET 0x00004000 /* Error Detected Indicator */
740#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
741
742/* ********** DMA CONTROLLER MASKS *********************8 */
743
744/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
745#define DMAEN 0x00000001 /* Channel Enable */
746#define WNR 0x00000002 /* Channel Direction (W/R*) */
747#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
748#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
749#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
750#define DMA2D 0x00000010 /* 2D/1D* Mode */
751#define RESTART 0x00000020 /* Restart */
752#define DI_SEL 0x00000040 /* Data Interrupt Select */
753#define DI_EN 0x00000080 /* Data Interrupt Enable */
754#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
755#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
756#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
757#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
758#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
759#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
760#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
761#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
762#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
763#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
764#define NDSIZE 0x00000900 /* Next Descriptor Size */
765#define DMAFLOW 0x00007000 /* Flow Control */
766#define DMAFLOW_STOP 0x0000 /* Stop Mode */
767#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
768#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
769#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
770#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
771
772#define DMAEN_P 0 /* Channel Enable */
773#define WNR_P 1 /* Channel Direction (W/R*) */
774#define DMA2D_P 4 /* 2D/1D* Mode */
775#define RESTART_P 5 /* Restart */
776#define DI_SEL_P 6 /* Data Interrupt Select */
777#define DI_EN_P 7 /* Data Interrupt Enable */
778
779/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
780
781#define DMA_DONE 0x00000001 /* DMA Done Indicator */
782#define DMA_ERR 0x00000002 /* DMA Error Indicator */
783#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
784#define DMA_RUN 0x00000008 /* DMA Running Indicator */
785
786#define DMA_DONE_P 0 /* DMA Done Indicator */
787#define DMA_ERR_P 1 /* DMA Error Indicator */
788#define DFETCH_P 2 /* Descriptor Fetch Indicator */
789#define DMA_RUN_P 3 /* DMA Running Indicator */
790
791/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
792
793#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
794#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
795#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
796#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
797#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
798#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
799#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
800#define PMAP 0x00007000 /* DMA Peripheral Map Field */
801
802#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
803#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
804#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
805#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
806#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
807#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
808#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
809#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
810
811/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
812
813/* PWM Timer bit definitions */
814
815/* TIMER_ENABLE Register */
816#define TIMEN0 0x0001
817#define TIMEN1 0x0002
818#define TIMEN2 0x0004
819
820#define TIMEN0_P 0x00
821#define TIMEN1_P 0x01
822#define TIMEN2_P 0x02
823
824/* TIMER_DISABLE Register */
825#define TIMDIS0 0x0001
826#define TIMDIS1 0x0002
827#define TIMDIS2 0x0004
828
829#define TIMDIS0_P 0x00
830#define TIMDIS1_P 0x01
831#define TIMDIS2_P 0x02
832
833/* TIMER_STATUS Register */
834#define TIMIL0 0x0001
835#define TIMIL1 0x0002
836#define TIMIL2 0x0004
837#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
838#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
839#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
840#define TRUN0 0x1000
841#define TRUN1 0x2000
842#define TRUN2 0x4000
843
844#define TIMIL0_P 0x00
845#define TIMIL1_P 0x01
846#define TIMIL2_P 0x02
847#define TOVF_ERR0_P 0x04
848#define TOVF_ERR1_P 0x05
849#define TOVF_ERR2_P 0x06
850#define TRUN0_P 0x0C
851#define TRUN1_P 0x0D
852#define TRUN2_P 0x0E
853
854/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
855#define TOVL_ERR0 TOVF_ERR0
856#define TOVL_ERR1 TOVF_ERR1
857#define TOVL_ERR2 TOVF_ERR2
858#define TOVL_ERR0_P TOVF_ERR0_P
859#define TOVL_ERR1_P TOVF_ERR1_P
860#define TOVL_ERR2_P TOVF_ERR2_P
861
862/* TIMERx_CONFIG Registers */
863#define PWM_OUT 0x0001
864#define WDTH_CAP 0x0002
865#define EXT_CLK 0x0003
866#define PULSE_HI 0x0004
867#define PERIOD_CNT 0x0008
868#define IRQ_ENA 0x0010
869#define TIN_SEL 0x0020
870#define OUT_DIS 0x0040
871#define CLK_SEL 0x0080
872#define TOGGLE_HI 0x0100
873#define EMU_RUN 0x0200
874#define ERR_TYP(x) ((x & 0x03) << 14)
875
876#define TMODE_P0 0x00
877#define TMODE_P1 0x01
878#define PULSE_HI_P 0x02
879#define PERIOD_CNT_P 0x03
880#define IRQ_ENA_P 0x04
881#define TIN_SEL_P 0x05
882#define OUT_DIS_P 0x06
883#define CLK_SEL_P 0x07
884#define TOGGLE_HI_P 0x08
885#define EMU_RUN_P 0x09
886#define ERR_TYP_P0 0x0E
887#define ERR_TYP_P1 0x0F
888
889/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
890
891/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
892#define PF0 0x0001
893#define PF1 0x0002
894#define PF2 0x0004
895#define PF3 0x0008
896#define PF4 0x0010
897#define PF5 0x0020
898#define PF6 0x0040
899#define PF7 0x0080
900#define PF8 0x0100
901#define PF9 0x0200
902#define PF10 0x0400
903#define PF11 0x0800
904#define PF12 0x1000
905#define PF13 0x2000
906#define PF14 0x4000
907#define PF15 0x8000
908
909/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
910#define PF0_P 0
911#define PF1_P 1
912#define PF2_P 2
913#define PF3_P 3
914#define PF4_P 4
915#define PF5_P 5
916#define PF6_P 6
917#define PF7_P 7
918#define PF8_P 8
919#define PF9_P 9
920#define PF10_P 10
921#define PF11_P 11
922#define PF12_P 12
923#define PF13_P 13
924#define PF14_P 14
925#define PF15_P 15
926
927/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
928
929/* SPI_CTL Masks */
930#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
931#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
932#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
933#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
934#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
935#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
936#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
937#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
938#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
939#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
940#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
941#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
942#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
943#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
944#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
945#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
946
947/* SPI_FLG Masks */
948#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
949#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
950#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
951#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
952#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
953#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
954#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
955#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
956#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
957#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
958#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
959#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
960#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
961#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
962
963/* SPI_FLG Bit Positions */
964#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
965#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
966#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
967#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
968#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
969#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
970#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
971#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
972#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
973#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
974#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
975#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
976#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
977#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
978
979/* SPI_STAT Masks */
980#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
981#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
982#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
983#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
984#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
985#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
986#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
987
988/* SPIx_FLG Masks */
989#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
990#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
991#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
992#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
993#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
994#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
995#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
996
997/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
998
999/* AMGCTL Masks */
1000#define AMCKEN 0x00000001 /* Enable CLKOUT */
1001#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
1002#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
1003#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
1004#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1005#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1006
1007/* AMGCTL Bit Positions */
1008#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
1009#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1010#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1011#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1012
1013/* AMBCTL0 Masks */
1014#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
1015#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
1016#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
1017#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1018#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1019#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1020#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1021#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1022#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1023#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1024#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1025#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1026#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1027#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1028#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
1029#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1030#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1031#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1032#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1033#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1034#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1035#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1036#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1037#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1038#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1039#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1040#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1041#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1042#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1043#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
1044#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1045#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1046#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1047#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1048#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1049#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1050#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1051#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1052#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1053#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1054#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1055#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1056#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1057#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1058#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
1059#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
1060#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
1061#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1062#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1063#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1064#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1065#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1066#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1067#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1068#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1069#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1070#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1071#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1072#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
1073#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1074#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1075#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1076#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1077#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1078#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1079#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1080#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1081#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1082#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1083#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1084#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1085#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1086#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1087#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1088#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1089#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1090#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1091#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1092#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1093#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1094#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1095#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1096#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1097#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1098#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
1099#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
1100#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1101#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1102
1103/* AMBCTL1 Masks */
1104#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1105#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1106#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1107#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1108#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1109#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1110#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1111#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1112#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1113#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1114#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1115#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1116#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1117#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1118#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1119#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1120#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1121#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1122#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1123#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1124#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1125#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1126#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1127#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1128#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1129#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1130#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1131#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1132#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1133#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1134#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1135#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1136#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1137#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1138#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1139#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1140#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1141#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1142#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1143#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1144#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1145#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1146#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1147#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1148#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1149#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1150#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1151#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1152#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1153#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1154#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1155#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1156#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1157#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1158#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1159#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1160#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1161#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1162#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1163#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1164#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1165#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1166#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1167#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1168#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1169#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1170#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1171#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1172#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1173#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1174#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1175#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1176#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1177#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1178#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1179#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1180#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1181#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1182#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1183#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1184#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1185#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1186#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1187#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1188#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1189#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1190#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1191#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1192
1193/* ********************** SDRAM CONTROLLER MASKS *************************** */
1194
1195/* SDGCTL Masks */
1196#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1197#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1198#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1199#define PFE 0x00000010 /* Enable SDRAM prefetch */
1200#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1201#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1202#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1203#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1204#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1205#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1206#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1207#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1208#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1209#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1210#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1211#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1212#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1213#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1214#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1215#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1216#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1217#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1218#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1219#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1220#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1221#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1222#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1223#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1224#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1225#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1226#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1227#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1228#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1229#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1230#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1231#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1232#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1233#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1234#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1235#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1236#define PUPSD 0x00200000 /*Power-up start delay */
1237#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1238#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1239#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1240#define EBUFE 0x02000000 /* Enable external buffering timing */
1241#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1242#define EMREN 0x10000000 /* Extended mode register enable */
1243#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1244#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1245
1246/* EBIU_SDBCTL Masks */
1247#define EBE 0x00000001 /* Enable SDRAM external bank */
1248#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1249#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1250#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1251#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1252#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1253#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1254#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1255#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1256
1257/* EBIU_SDSTAT Masks */
1258#define SDCI 0x00000001 /* SDRAM controller is idle */
1259#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1260#define SDPUA 0x00000004 /* SDRAM power up active */
1261#define SDRS 0x00000008 /* SDRAM is in reset state */
1262#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1263#define BGSTAT 0x00000020 /* Bus granted */
1264
1265
1266#endif /* _DEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h
new file mode 100644
index 000000000000..bd9d5e94307d
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/dma.h
@@ -0,0 +1,54 @@
1/*****************************************************************************
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6/*
7 * File: include/asm-blackfin/mach-bf533/dma.h
8 * Based on:
9 * Author:
10 *
11 * Created:
12 * Description:
13 *
14 * Rev:
15 *
16 * Modified:
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING.
32 * If not, write to the Free Software Foundation,
33 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 */
35
36#ifndef _MACH_DMA_H_
37#define _MACH_DMA_H_
38
39#define MAX_BLACKFIN_DMA_CHANNEL 12
40
41#define CH_PPI 0
42#define CH_SPORT0_RX 1
43#define CH_SPORT0_TX 2
44#define CH_SPORT1_RX 3
45#define CH_SPORT1_TX 4
46#define CH_SPI 5
47#define CH_UART_RX 6
48#define CH_UART_TX 7
49#define CH_MEM_STREAM0_DEST 8 /* TX */
50#define CH_MEM_STREAM0_SRC 9 /* RX */
51#define CH_MEM_STREAM1_DEST 10 /* TX */
52#define CH_MEM_STREAM1_SRC 11 /* RX */
53
54#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
new file mode 100644
index 000000000000..5aa38e5da6b7
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -0,0 +1,173 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/defBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _BF533_IRQ_H_
32#define _BF533_IRQ_H_
33
34/*
35 * Interrupt source definitions
36 Event Source Core Event Name
37Core Emulation **
38 Events (highest priority) EMU 0
39 Reset RST 1
40 NMI NMI 2
41 Exception EVX 3
42 Reserved -- 4
43 Hardware Error IVHW 5
44 Core Timer IVTMR 6 *
45 PLL Wakeup Interrupt IVG7 7
46 DMA Error (generic) IVG7 8
47 PPI Error Interrupt IVG7 9
48 SPORT0 Error Interrupt IVG7 10
49 SPORT1 Error Interrupt IVG7 11
50 SPI Error Interrupt IVG7 12
51 UART Error Interrupt IVG7 13
52 RTC Interrupt IVG8 14
53 DMA0 Interrupt (PPI) IVG8 15
54 DMA1 (SPORT0 RX) IVG9 16
55 DMA2 (SPORT0 TX) IVG9 17
56 DMA3 (SPORT1 RX) IVG9 18
57 DMA4 (SPORT1 TX) IVG9 19
58 DMA5 (PPI) IVG10 20
59 DMA6 (UART RX) IVG10 21
60 DMA7 (UART TX) IVG10 22
61 Timer0 IVG11 23
62 Timer1 IVG11 24
63 Timer2 IVG11 25
64 PF Interrupt A IVG12 26
65 PF Interrupt B IVG12 27
66 DMA8/9 Interrupt IVG13 28
67 DMA10/11 Interrupt IVG13 29
68 Watchdog Timer IVG13 30
69
70 Softirq IVG14 31
71 System Call --
72 (lowest priority) IVG15 32 *
73 */
74#define SYS_IRQS 31
75#define NR_PERI_INTS 24
76
77/* The ABSTRACT IRQ definitions */
78/** the first seven of the following are fixed, the rest you change if you need to **/
79#define IRQ_EMU 0 /*Emulation */
80#define IRQ_RST 1 /*reset */
81#define IRQ_NMI 2 /*Non Maskable */
82#define IRQ_EVX 3 /*Exception */
83#define IRQ_UNUSED 4 /*- unused interrupt*/
84#define IRQ_HWERR 5 /*Hardware Error */
85#define IRQ_CORETMR 6 /*Core timer */
86
87#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
88#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
89#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
90#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
91#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
92#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
93#define IRQ_UART_ERROR 13 /*UART Error Interrupt */
94#define IRQ_RTC 14 /*RTC Interrupt */
95#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
96#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
97#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
98#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
99#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
101#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
102#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
103#define IRQ_TMR0 23 /*Timer 0 */
104#define IRQ_TMR1 24 /*Timer 1 */
105#define IRQ_TMR2 25 /*Timer 2 */
106#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
107#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
108#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
109#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
110#define IRQ_WATCH 30 /*Watch Dog Timer */
111
112#define IRQ_PF0 33
113#define IRQ_PF1 34
114#define IRQ_PF2 35
115#define IRQ_PF3 36
116#define IRQ_PF4 37
117#define IRQ_PF5 38
118#define IRQ_PF6 39
119#define IRQ_PF7 40
120#define IRQ_PF8 41
121#define IRQ_PF9 42
122#define IRQ_PF10 43
123#define IRQ_PF11 44
124#define IRQ_PF12 45
125#define IRQ_PF13 46
126#define IRQ_PF14 47
127#define IRQ_PF15 48
128
129#define GPIO_IRQ_BASE IRQ_PF0
130
131#define NR_IRQS (IRQ_PF15+1)
132
133#define IVG7 7
134#define IVG8 8
135#define IVG9 9
136#define IVG10 10
137#define IVG11 11
138#define IVG12 12
139#define IVG13 13
140#define IVG14 14
141#define IVG15 15
142
143/* IAR0 BIT FIELDS*/
144#define RTC_ERROR_POS 28
145#define UART_ERROR_POS 24
146#define SPORT1_ERROR_POS 20
147#define SPI_ERROR_POS 16
148#define SPORT0_ERROR_POS 12
149#define PPI_ERROR_POS 8
150#define DMA_ERROR_POS 4
151#define PLLWAKE_ERROR_POS 0
152
153/* IAR1 BIT FIELDS*/
154#define DMA7_UARTTX_POS 28
155#define DMA6_UARTRX_POS 24
156#define DMA5_SPI_POS 20
157#define DMA4_SPORT1TX_POS 16
158#define DMA3_SPORT1RX_POS 12
159#define DMA2_SPORT0TX_POS 8
160#define DMA1_SPORT0RX_POS 4
161#define DMA0_PPI_POS 0
162
163/* IAR2 BIT FIELDS*/
164#define WDTIMER_POS 28
165#define MEMDMA1_POS 24
166#define MEMDMA0_POS 20
167#define PFB_POS 16
168#define PFA_POS 12
169#define TIMER2_POS 8
170#define TIMER1_POS 4
171#define TIMER0_POS 0
172
173#endif /* _BF533_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_init.h b/arch/blackfin/mach-bf533/include/mach/mem_init.h
new file mode 100644
index 000000000000..ed2034bf10ec
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/mem_init.h
@@ -0,0 +1,297 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
33 CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
34#if (CONFIG_SCLK_HZ > 119402985)
35#define SDRAM_tRP TRP_2
36#define SDRAM_tRP_num 2
37#define SDRAM_tRAS TRAS_7
38#define SDRAM_tRAS_num 7
39#define SDRAM_tRCD TRCD_2
40#define SDRAM_tWR TWR_2
41#endif
42#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
43#define SDRAM_tRP TRP_2
44#define SDRAM_tRP_num 2
45#define SDRAM_tRAS TRAS_6
46#define SDRAM_tRAS_num 6
47#define SDRAM_tRCD TRCD_2
48#define SDRAM_tWR TWR_2
49#endif
50#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
51#define SDRAM_tRP TRP_2
52#define SDRAM_tRP_num 2
53#define SDRAM_tRAS TRAS_5
54#define SDRAM_tRAS_num 5
55#define SDRAM_tRCD TRCD_2
56#define SDRAM_tWR TWR_2
57#endif
58#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
59#define SDRAM_tRP TRP_2
60#define SDRAM_tRP_num 2
61#define SDRAM_tRAS TRAS_4
62#define SDRAM_tRAS_num 4
63#define SDRAM_tRCD TRCD_2
64#define SDRAM_tWR TWR_2
65#endif
66#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
67#define SDRAM_tRP TRP_2
68#define SDRAM_tRP_num 2
69#define SDRAM_tRAS TRAS_3
70#define SDRAM_tRAS_num 3
71#define SDRAM_tRCD TRCD_2
72#define SDRAM_tWR TWR_2
73#endif
74#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
75#define SDRAM_tRP TRP_1
76#define SDRAM_tRP_num 1
77#define SDRAM_tRAS TRAS_4
78#define SDRAM_tRAS_num 3
79#define SDRAM_tRCD TRCD_1
80#define SDRAM_tWR TWR_2
81#endif
82#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
83#define SDRAM_tRP TRP_1
84#define SDRAM_tRP_num 1
85#define SDRAM_tRAS TRAS_3
86#define SDRAM_tRAS_num 3
87#define SDRAM_tRCD TRCD_1
88#define SDRAM_tWR TWR_2
89#endif
90#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
91#define SDRAM_tRP TRP_1
92#define SDRAM_tRP_num 1
93#define SDRAM_tRAS TRAS_2
94#define SDRAM_tRAS_num 2
95#define SDRAM_tRCD TRCD_1
96#define SDRAM_tWR TWR_2
97#endif
98#if (CONFIG_SCLK_HZ <= 29850746)
99#define SDRAM_tRP TRP_1
100#define SDRAM_tRP_num 1
101#define SDRAM_tRAS TRAS_1
102#define SDRAM_tRAS_num 1
103#define SDRAM_tRCD TRCD_1
104#define SDRAM_tWR TWR_2
105#endif
106#endif
107
108#if (CONFIG_MEM_MT48LC16M16A2TG_75)
109 /*SDRAM INFORMATION: */
110#define SDRAM_Tref 64 /* Refresh period in milliseconds */
111#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
112#define SDRAM_CL CL_3
113#endif
114
115#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
116 /*SDRAM INFORMATION: */
117#define SDRAM_Tref 64 /* Refresh period in milliseconds */
118#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
119#define SDRAM_CL CL_3
120#endif
121
122#if (CONFIG_MEM_MT48LC32M16A2TG_75)
123 /*SDRAM INFORMATION: */
124#define SDRAM_Tref 64 /* Refresh period in milliseconds */
125#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
126#define SDRAM_CL CL_3
127#endif
128
129#if (CONFIG_MEM_GENERIC_BOARD)
130 /*SDRAM INFORMATION: Modify this for your board */
131#define SDRAM_Tref 64 /* Refresh period in milliseconds */
132#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
133#define SDRAM_CL CL_3
134#endif
135
136/* Equation from section 17 (p17-46) of BF533 HRM */
137#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
138
139/* Enable SCLK Out */
140#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
141
142#if defined CONFIG_CLKIN_HALF
143#define CLKIN_HALF 1
144#else
145#define CLKIN_HALF 0
146#endif
147
148#if defined CONFIG_PLL_BYPASS
149#define PLL_BYPASS 1
150#else
151#define PLL_BYPASS 0
152#endif
153
154/***************************************Currently Not Being Used *********************************/
155#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
156#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
158#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
159#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
160
161#if (flash_EBIU_AMBCTL_TT > 3)
162#define flash_EBIU_AMBCTL0_TT B0TT_4
163#endif
164#if (flash_EBIU_AMBCTL_TT == 3)
165#define flash_EBIU_AMBCTL0_TT B0TT_3
166#endif
167#if (flash_EBIU_AMBCTL_TT == 2)
168#define flash_EBIU_AMBCTL0_TT B0TT_2
169#endif
170#if (flash_EBIU_AMBCTL_TT < 2)
171#define flash_EBIU_AMBCTL0_TT B0TT_1
172#endif
173
174#if (flash_EBIU_AMBCTL_ST > 3)
175#define flash_EBIU_AMBCTL0_ST B0ST_4
176#endif
177#if (flash_EBIU_AMBCTL_ST == 3)
178#define flash_EBIU_AMBCTL0_ST B0ST_3
179#endif
180#if (flash_EBIU_AMBCTL_ST == 2)
181#define flash_EBIU_AMBCTL0_ST B0ST_2
182#endif
183#if (flash_EBIU_AMBCTL_ST < 2)
184#define flash_EBIU_AMBCTL0_ST B0ST_1
185#endif
186
187#if (flash_EBIU_AMBCTL_HT > 2)
188#define flash_EBIU_AMBCTL0_HT B0HT_3
189#endif
190#if (flash_EBIU_AMBCTL_HT == 2)
191#define flash_EBIU_AMBCTL0_HT B0HT_2
192#endif
193#if (flash_EBIU_AMBCTL_HT == 1)
194#define flash_EBIU_AMBCTL0_HT B0HT_1
195#endif
196#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
197#define flash_EBIU_AMBCTL0_HT B0HT_0
198#endif
199#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
200#define flash_EBIU_AMBCTL0_HT B0HT_1
201#endif
202
203#if (flash_EBIU_AMBCTL_WAT > 14)
204#define flash_EBIU_AMBCTL0_WAT B0WAT_15
205#endif
206#if (flash_EBIU_AMBCTL_WAT == 14)
207#define flash_EBIU_AMBCTL0_WAT B0WAT_14
208#endif
209#if (flash_EBIU_AMBCTL_WAT == 13)
210#define flash_EBIU_AMBCTL0_WAT B0WAT_13
211#endif
212#if (flash_EBIU_AMBCTL_WAT == 12)
213#define flash_EBIU_AMBCTL0_WAT B0WAT_12
214#endif
215#if (flash_EBIU_AMBCTL_WAT == 11)
216#define flash_EBIU_AMBCTL0_WAT B0WAT_11
217#endif
218#if (flash_EBIU_AMBCTL_WAT == 10)
219#define flash_EBIU_AMBCTL0_WAT B0WAT_10
220#endif
221#if (flash_EBIU_AMBCTL_WAT == 9)
222#define flash_EBIU_AMBCTL0_WAT B0WAT_9
223#endif
224#if (flash_EBIU_AMBCTL_WAT == 8)
225#define flash_EBIU_AMBCTL0_WAT B0WAT_8
226#endif
227#if (flash_EBIU_AMBCTL_WAT == 7)
228#define flash_EBIU_AMBCTL0_WAT B0WAT_7
229#endif
230#if (flash_EBIU_AMBCTL_WAT == 6)
231#define flash_EBIU_AMBCTL0_WAT B0WAT_6
232#endif
233#if (flash_EBIU_AMBCTL_WAT == 5)
234#define flash_EBIU_AMBCTL0_WAT B0WAT_5
235#endif
236#if (flash_EBIU_AMBCTL_WAT == 4)
237#define flash_EBIU_AMBCTL0_WAT B0WAT_4
238#endif
239#if (flash_EBIU_AMBCTL_WAT == 3)
240#define flash_EBIU_AMBCTL0_WAT B0WAT_3
241#endif
242#if (flash_EBIU_AMBCTL_WAT == 2)
243#define flash_EBIU_AMBCTL0_WAT B0WAT_2
244#endif
245#if (flash_EBIU_AMBCTL_WAT == 1)
246#define flash_EBIU_AMBCTL0_WAT B0WAT_1
247#endif
248
249#if (flash_EBIU_AMBCTL_RAT > 14)
250#define flash_EBIU_AMBCTL0_RAT B0RAT_15
251#endif
252#if (flash_EBIU_AMBCTL_RAT == 14)
253#define flash_EBIU_AMBCTL0_RAT B0RAT_14
254#endif
255#if (flash_EBIU_AMBCTL_RAT == 13)
256#define flash_EBIU_AMBCTL0_RAT B0RAT_13
257#endif
258#if (flash_EBIU_AMBCTL_RAT == 12)
259#define flash_EBIU_AMBCTL0_RAT B0RAT_12
260#endif
261#if (flash_EBIU_AMBCTL_RAT == 11)
262#define flash_EBIU_AMBCTL0_RAT B0RAT_11
263#endif
264#if (flash_EBIU_AMBCTL_RAT == 10)
265#define flash_EBIU_AMBCTL0_RAT B0RAT_10
266#endif
267#if (flash_EBIU_AMBCTL_RAT == 9)
268#define flash_EBIU_AMBCTL0_RAT B0RAT_9
269#endif
270#if (flash_EBIU_AMBCTL_RAT == 8)
271#define flash_EBIU_AMBCTL0_RAT B0RAT_8
272#endif
273#if (flash_EBIU_AMBCTL_RAT == 7)
274#define flash_EBIU_AMBCTL0_RAT B0RAT_7
275#endif
276#if (flash_EBIU_AMBCTL_RAT == 6)
277#define flash_EBIU_AMBCTL0_RAT B0RAT_6
278#endif
279#if (flash_EBIU_AMBCTL_RAT == 5)
280#define flash_EBIU_AMBCTL0_RAT B0RAT_5
281#endif
282#if (flash_EBIU_AMBCTL_RAT == 4)
283#define flash_EBIU_AMBCTL0_RAT B0RAT_4
284#endif
285#if (flash_EBIU_AMBCTL_RAT == 3)
286#define flash_EBIU_AMBCTL0_RAT B0RAT_3
287#endif
288#if (flash_EBIU_AMBCTL_RAT == 2)
289#define flash_EBIU_AMBCTL0_RAT B0RAT_2
290#endif
291#if (flash_EBIU_AMBCTL_RAT == 1)
292#define flash_EBIU_AMBCTL0_RAT B0RAT_1
293#endif
294
295#define flash_EBIU_AMBCTL0 \
296 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
297 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h
new file mode 100644
index 000000000000..581fc6eea789
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h
@@ -0,0 +1,171 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_map.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MEM_MAP_533_H_
32#define _MEM_MAP_533_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x400
51
52/* Level 1 Memory */
53
54#ifdef CONFIG_BFIN_ICACHE
55#define BFIN_ICACHESIZE (16*1024)
56#else
57#define BFIN_ICACHESIZE (0*1024)
58#endif
59
60/* Memory Map for ADSP-BF533 processors */
61
62#ifdef CONFIG_BF533
63#define L1_CODE_START 0xFFA00000
64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000
66
67#ifdef CONFIG_BFIN_ICACHE
68#define L1_CODE_LENGTH (0x14000 - 0x4000)
69#else
70#define L1_CODE_LENGTH 0x14000
71#endif
72
73#ifdef CONFIG_BFIN_DCACHE
74
75#ifdef CONFIG_BFIN_DCACHE_BANKA
76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH 0x8000
79#define BFIN_DCACHESIZE (16*1024)
80#define BFIN_DSUPBANKS 1
81#else
82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
83#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
84#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
85#define BFIN_DCACHESIZE (32*1024)
86#define BFIN_DSUPBANKS 2
87#endif
88
89#else
90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
91#define L1_DATA_A_LENGTH 0x8000
92#define L1_DATA_B_LENGTH 0x8000
93#define BFIN_DCACHESIZE (0*1024)
94#define BFIN_DSUPBANKS 0
95#endif /*CONFIG_BFIN_DCACHE*/
96#endif
97
98/* Memory Map for ADSP-BF532 processors */
99
100#ifdef CONFIG_BF532
101#define L1_CODE_START 0xFFA08000
102#define L1_DATA_A_START 0xFF804000
103#define L1_DATA_B_START 0xFF904000
104
105#ifdef CONFIG_BFIN_ICACHE
106#define L1_CODE_LENGTH (0xC000 - 0x4000)
107#else
108#define L1_CODE_LENGTH 0xC000
109#endif
110
111#ifdef CONFIG_BFIN_DCACHE
112
113#ifdef CONFIG_BFIN_DCACHE_BANKA
114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
115#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
116#define L1_DATA_B_LENGTH 0x4000
117#define BFIN_DCACHESIZE (16*1024)
118#define BFIN_DSUPBANKS 1
119
120#else
121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
122#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
123#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
124#define BFIN_DCACHESIZE (32*1024)
125#define BFIN_DSUPBANKS 2
126#endif
127
128#else
129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
130#define L1_DATA_A_LENGTH 0x4000
131#define L1_DATA_B_LENGTH 0x4000
132#define BFIN_DCACHESIZE (0*1024)
133#define BFIN_DSUPBANKS 0
134#endif /*CONFIG_BFIN_DCACHE*/
135#endif
136
137/* Memory Map for ADSP-BF531 processors */
138
139#ifdef CONFIG_BF531
140#define L1_CODE_START 0xFFA08000
141#define L1_DATA_A_START 0xFF804000
142#define L1_DATA_B_START 0xFF904000
143#define L1_CODE_LENGTH 0x4000
144#define L1_DATA_B_LENGTH 0x0000
145
146
147#ifdef CONFIG_BFIN_DCACHE
148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
149#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
150#define BFIN_DCACHESIZE (16*1024)
151#define BFIN_DSUPBANKS 1
152#else
153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
154#define L1_DATA_A_LENGTH 0x4000
155#define BFIN_DCACHESIZE (0*1024)
156#define BFIN_DSUPBANKS 0
157#endif
158
159#endif
160
161/* Level 2 Memory - none */
162
163#define L2_START 0
164#define L2_LENGTH 0
165
166/* Scratch Pad Memory */
167
168#define L1_SCRATCH_START 0xFFB00000
169#define L1_SCRATCH_LENGTH 0x1000
170
171#endif /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h
new file mode 100644
index 000000000000..685a2651dcda
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/portmux.h
@@ -0,0 +1,67 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
6#define P_PPI0_CLK (P_DONTCARE)
7#define P_PPI0_FS1 (P_DONTCARE)
8#define P_PPI0_FS2 (P_DONTCARE)
9#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
10#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
11#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
12#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
13#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
14#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
15#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
16#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
17#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
18#define P_PPI0_D0 (P_DONTCARE)
19#define P_PPI0_D1 (P_DONTCARE)
20#define P_PPI0_D2 (P_DONTCARE)
21#define P_PPI0_D3 (P_DONTCARE)
22#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
23#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
24#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
25#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
26
27#define P_SPORT1_TSCLK (P_DONTCARE)
28#define P_SPORT1_RSCLK (P_DONTCARE)
29#define P_SPORT0_TSCLK (P_DONTCARE)
30#define P_SPORT0_RSCLK (P_DONTCARE)
31#define P_UART0_RX (P_DONTCARE)
32#define P_UART0_TX (P_DONTCARE)
33#define P_SPORT1_DRSEC (P_DONTCARE)
34#define P_SPORT1_RFS (P_DONTCARE)
35#define P_SPORT1_DTPRI (P_DONTCARE)
36#define P_SPORT1_DTSEC (P_DONTCARE)
37#define P_SPORT1_TFS (P_DONTCARE)
38#define P_SPORT1_DRPRI (P_DONTCARE)
39#define P_SPORT0_DRSEC (P_DONTCARE)
40#define P_SPORT0_RFS (P_DONTCARE)
41#define P_SPORT0_DTPRI (P_DONTCARE)
42#define P_SPORT0_DTSEC (P_DONTCARE)
43#define P_SPORT0_TFS (P_DONTCARE)
44#define P_SPORT0_DRPRI (P_DONTCARE)
45
46#define P_SPI0_MOSI (P_DONTCARE)
47#define P_SPI0_MISO (P_DONTCARE)
48#define P_SPI0_SCK (P_DONTCARE)
49#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
50#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
51#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
52#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
53#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
54#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
55#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
56#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
57
58#define P_TMR2 (P_DONTCARE)
59#define P_TMR1 (P_DONTCARE)
60#define P_TMR0 (P_DONTCARE)
61#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
62
63
64
65
66
67#endif /* _MACH_PORTMUX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 04:01:20 -0500