1 files changed, 173 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
new file mode 100644
index 000000000000..5aa38e5da6b7
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -0,0 +1,173 @@
+/*
+ * File:         include/asm-blackfin/mach-bf533/defBF532.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#ifndef _BF533_IRQ_H_
+#define _BF533_IRQ_H_
+/*
+ * Interrupt source definitions
+             Event Source    Core Event Name
+Core        Emulation               **
+ Events         (highest priority)  EMU         0
+            Reset                   RST         1
+            NMI                     NMI         2
+            Exception               EVX         3
+            Reserved                --          4
+            Hardware Error          IVHW        5
+            Core Timer              IVTMR       6 *
+            PLL Wakeup Interrupt    IVG7        7
+            DMA Error (generic)     IVG7        8
+            PPI Error Interrupt     IVG7        9
+            SPORT0 Error Interrupt  IVG7        10
+            SPORT1 Error Interrupt  IVG7        11
+            SPI Error Interrupt     IVG7        12
+            UART Error Interrupt    IVG7        13
+            RTC Interrupt           IVG8        14
+            DMA0 Interrupt (PPI)    IVG8        15
+            DMA1 (SPORT0 RX)        IVG9        16
+            DMA2 (SPORT0 TX)        IVG9        17
+            DMA3 (SPORT1 RX)        IVG9        18
+            DMA4 (SPORT1 TX)        IVG9        19
+            DMA5 (PPI)              IVG10       20
+            DMA6 (UART RX)          IVG10       21
+            DMA7 (UART TX)          IVG10       22
+            Timer0                  IVG11       23
+            Timer1                  IVG11       24
+            Timer2                  IVG11       25
+            PF Interrupt A          IVG12       26
+            PF Interrupt B          IVG12       27
+            DMA8/9 Interrupt        IVG13       28
+            DMA10/11 Interrupt      IVG13       29
+            Watchdog Timer          IVG13       30
+            Softirq                 IVG14       31
+            System Call    --
+                 (lowest priority)  IVG15       32 *
+ */
+#define SYS_IRQS        31
+#define NR_PERI_INTS    24
+/* The ABSTRACT IRQ definitions */
+/** the first seven of the following are fixed, the rest you change if you need to **/
+#define IRQ_EMU                 0       /*Emulation */
+#define IRQ_RST                 1       /*reset */
+#define IRQ_NMI                 2       /*Non Maskable */
+#define IRQ_EVX                 3       /*Exception */
+#define IRQ_UNUSED              4       /*- unused interrupt*/
+#define IRQ_HWERR               5       /*Hardware Error */
+#define IRQ_CORETMR             6       /*Core timer */
+#define IRQ_PLL_WAKEUP          7       /*PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR           8       /*DMA Error (general) */
+#define IRQ_PPI_ERROR           9       /*PPI Error Interrupt */
+#define IRQ_SPORT0_ERROR        10      /*SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR        11      /*SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR           12      /*SPI Error Interrupt */
+#define IRQ_UART_ERROR          13      /*UART Error Interrupt */
+#define IRQ_RTC                 14      /*RTC Interrupt */
+#define IRQ_PPI                 15      /*DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX           16      /*DMA1 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
+#define         IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
+#define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
+#define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
+#define IRQ_TMR0                23      /*Timer 0 */
+#define IRQ_TMR1                24      /*Timer 1 */
+#define IRQ_TMR2                25      /*Timer 2 */
+#define IRQ_PROG_INTA           26      /*Programmable Flags A (8) */
+#define IRQ_PROG_INTB           27      /*Programmable Flags B (8) */
+#define IRQ_MEM_DMA0            28      /*DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define IRQ_WATCH               30      /*Watch Dog Timer */
+#define IRQ_PF0                 33
+#define IRQ_PF1                 34
+#define IRQ_PF2                 35
+#define IRQ_PF3                 36
+#define IRQ_PF4                 37
+#define IRQ_PF5                 38
+#define IRQ_PF6                 39
+#define IRQ_PF7                 40
+#define IRQ_PF8                 41
+#define IRQ_PF9                 42
+#define IRQ_PF10                43
+#define IRQ_PF11                44
+#define IRQ_PF12                45
+#define IRQ_PF13                46
+#define IRQ_PF14                47
+#define IRQ_PF15                48
+#define GPIO_IRQ_BASE           IRQ_PF0
+#define NR_IRQS         (IRQ_PF15+1)
+#define IVG7                    7
+#define IVG8                    8
+#define IVG9                    9
+#define IVG10                   10
+#define IVG11                   11
+#define IVG12                   12
+#define IVG13                   13
+#define IVG14                   14
+#define IVG15                   15
+/* IAR0 BIT FIELDS*/
+#define RTC_ERROR_POS                   28
+#define UART_ERROR_POS                  24
+#define SPORT1_ERROR_POS                20
+#define SPI_ERROR_POS                   16
+#define SPORT0_ERROR_POS                12
+#define PPI_ERROR_POS                   8
+#define DMA_ERROR_POS                   4
+#define PLLWAKE_ERROR_POS               0
+/* IAR1 BIT FIELDS*/
+#define DMA7_UARTTX_POS                 28
+#define DMA6_UARTRX_POS                 24
+#define DMA5_SPI_POS                    20
+#define DMA4_SPORT1TX_POS               16
+#define DMA3_SPORT1RX_POS               12
+#define DMA2_SPORT0TX_POS               8
+#define DMA1_SPORT0RX_POS               4
+#define DMA0_PPI_POS                    0
+/* IAR2 BIT FIELDS*/
+#define WDTIMER_POS                     28
+#define MEMDMA1_POS                     24
+#define MEMDMA0_POS                     20
+#define PFB_POS                         16
+#define PFA_POS                         12
+#define TIMER2_POS                      8
+#define TIMER1_POS                      4
+#define TIMER0_POS                      0
+#endif                          /* _BF533_IRQ_H_ */

diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h new file mode 100644 index 000000000000..5aa38e5da6b7 --- /dev/null +++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -0,0 +1,173 @@
	1	/*
	2	* File: include/asm-blackfin/mach-bf533/defBF532.h
	3	* Based on:
	4	* Author:
	5	*
	6	* Created:
	7	* Description:
	8	*
	9	* Rev:
	10	*
	11	* Modified:
	12	*
	13	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License as published by
	17	* the Free Software Foundation; either version 2, or (at your option)
	18	* any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; see the file COPYING.
	27	* If not, write to the Free Software Foundation,
	28	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	29	*/
	30
	31	#ifndef _BF533_IRQ_H_
	32	#define _BF533_IRQ_H_
	33
	34	/*
	35	* Interrupt source definitions
	36	Event Source Core Event Name
	37	Core Emulation **
	38	Events (highest priority) EMU 0
	39	Reset RST 1
	40	NMI NMI 2
	41	Exception EVX 3
	42	Reserved -- 4
	43	Hardware Error IVHW 5
	44	Core Timer IVTMR 6 *
	45	PLL Wakeup Interrupt IVG7 7
	46	DMA Error (generic) IVG7 8
	47	PPI Error Interrupt IVG7 9
	48	SPORT0 Error Interrupt IVG7 10
	49	SPORT1 Error Interrupt IVG7 11
	50	SPI Error Interrupt IVG7 12
	51	UART Error Interrupt IVG7 13
	52	RTC Interrupt IVG8 14
	53	DMA0 Interrupt (PPI) IVG8 15
	54	DMA1 (SPORT0 RX) IVG9 16
	55	DMA2 (SPORT0 TX) IVG9 17
	56	DMA3 (SPORT1 RX) IVG9 18
	57	DMA4 (SPORT1 TX) IVG9 19
	58	DMA5 (PPI) IVG10 20
	59	DMA6 (UART RX) IVG10 21
	60	DMA7 (UART TX) IVG10 22
	61	Timer0 IVG11 23
	62	Timer1 IVG11 24
	63	Timer2 IVG11 25
	64	PF Interrupt A IVG12 26
	65	PF Interrupt B IVG12 27
	66	DMA8/9 Interrupt IVG13 28
	67	DMA10/11 Interrupt IVG13 29
	68	Watchdog Timer IVG13 30
	69
	70	Softirq IVG14 31
	71	System Call --
	72	(lowest priority) IVG15 32 *
	73	*/
	74	#define SYS_IRQS 31
	75	#define NR_PERI_INTS 24
	76
	77	/* The ABSTRACT IRQ definitions */
	78	/ the first seven of the following are fixed, the rest you change if you need to /
	79	#define IRQ_EMU 0 /Emulation /
	80	#define IRQ_RST 1 /reset /
	81	#define IRQ_NMI 2 /Non Maskable /
	82	#define IRQ_EVX 3 /Exception /
	83	#define IRQ_UNUSED 4 /- unused interrupt/
	84	#define IRQ_HWERR 5 /Hardware Error /
	85	#define IRQ_CORETMR 6 /Core timer /
	86
	87	#define IRQ_PLL_WAKEUP 7 /PLL Wakeup Interrupt /
	88	#define IRQ_DMA_ERROR 8 /DMA Error (general) /
	89	#define IRQ_PPI_ERROR 9 /PPI Error Interrupt /
	90	#define IRQ_SPORT0_ERROR 10 /SPORT0 Error Interrupt /
	91	#define IRQ_SPORT1_ERROR 11 /SPORT1 Error Interrupt /
	92	#define IRQ_SPI_ERROR 12 /SPI Error Interrupt /
	93	#define IRQ_UART_ERROR 13 /UART Error Interrupt /
	94	#define IRQ_RTC 14 /RTC Interrupt /
	95	#define IRQ_PPI 15 /DMA0 Interrupt (PPI) /
	96	#define IRQ_SPORT0_RX 16 /DMA1 Interrupt (SPORT0 RX) /
	97	#define IRQ_SPORT0_TX 17 /DMA2 Interrupt (SPORT0 TX) /
	98	#define IRQ_SPORT1_RX 18 /DMA3 Interrupt (SPORT1 RX) /
	99	#define IRQ_SPORT1_TX 19 /DMA4 Interrupt (SPORT1 TX) /
	100	#define IRQ_SPI 20 /DMA5 Interrupt (SPI) /
	101	#define IRQ_UART_RX 21 /DMA6 Interrupt (UART RX) /
	102	#define IRQ_UART_TX 22 /DMA7 Interrupt (UART TX) /
	103	#define IRQ_TMR0 23 /Timer 0 /
	104	#define IRQ_TMR1 24 /Timer 1 /
	105	#define IRQ_TMR2 25 /Timer 2 /
	106	#define IRQ_PROG_INTA 26 /Programmable Flags A (8) /
	107	#define IRQ_PROG_INTB 27 /Programmable Flags B (8) /
	108	#define IRQ_MEM_DMA0 28 /DMA8/9 Interrupt (Memory DMA Stream 0) /
	109	#define IRQ_MEM_DMA1 29 /DMA10/11 Interrupt (Memory DMA Stream 1) /
	110	#define IRQ_WATCH 30 /Watch Dog Timer /
	111
	112	#define IRQ_PF0 33
	113	#define IRQ_PF1 34
	114	#define IRQ_PF2 35
	115	#define IRQ_PF3 36
	116	#define IRQ_PF4 37
	117	#define IRQ_PF5 38
	118	#define IRQ_PF6 39
	119	#define IRQ_PF7 40
	120	#define IRQ_PF8 41
	121	#define IRQ_PF9 42
	122	#define IRQ_PF10 43
	123	#define IRQ_PF11 44
	124	#define IRQ_PF12 45
	125	#define IRQ_PF13 46
	126	#define IRQ_PF14 47
	127	#define IRQ_PF15 48
	128
	129	#define GPIO_IRQ_BASE IRQ_PF0
	130
	131	#define NR_IRQS (IRQ_PF15+1)
	132
	133	#define IVG7 7
	134	#define IVG8 8
	135	#define IVG9 9
	136	#define IVG10 10
	137	#define IVG11 11
	138	#define IVG12 12
	139	#define IVG13 13
	140	#define IVG14 14
	141	#define IVG15 15
	142
	143	/* IAR0 BIT FIELDS*/
	144	#define RTC_ERROR_POS 28
	145	#define UART_ERROR_POS 24
	146	#define SPORT1_ERROR_POS 20
	147	#define SPI_ERROR_POS 16
	148	#define SPORT0_ERROR_POS 12
	149	#define PPI_ERROR_POS 8
	150	#define DMA_ERROR_POS 4
	151	#define PLLWAKE_ERROR_POS 0
	152
	153	/* IAR1 BIT FIELDS*/
	154	#define DMA7_UARTTX_POS 28
	155	#define DMA6_UARTRX_POS 24
	156	#define DMA5_SPI_POS 20
	157	#define DMA4_SPORT1TX_POS 16
	158	#define DMA3_SPORT1RX_POS 12
	159	#define DMA2_SPORT0TX_POS 8
	160	#define DMA1_SPORT0RX_POS 4
	161	#define DMA0_PPI_POS 0
	162
	163	/* IAR2 BIT FIELDS*/
	164	#define WDTIMER_POS 28
	165	#define MEMDMA1_POS 24
	166	#define MEMDMA0_POS 20
	167	#define PFB_POS 16
	168	#define PFA_POS 12
	169	#define TIMER2_POS 8
	170	#define TIMER1_POS 4
	171	#define TIMER0_POS 0
	172
	173	#endif /* _BF533_IRQ_H_ */