diff options
Diffstat (limited to 'arch/blackfin/mach-bf533/include/mach/irq.h')
| -rw-r--r-- | arch/blackfin/mach-bf533/include/mach/irq.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h index 5aa38e5da6b7..db1e346cd1aa 100644 --- a/arch/blackfin/mach-bf533/include/mach/irq.h +++ b/arch/blackfin/mach-bf533/include/mach/irq.h | |||
| @@ -90,19 +90,19 @@ Core Emulation ** | |||
| 90 | #define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ | 90 | #define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ |
| 91 | #define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ | 91 | #define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ |
| 92 | #define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ | 92 | #define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ |
| 93 | #define IRQ_UART_ERROR 13 /*UART Error Interrupt */ | 93 | #define IRQ_UART0_ERROR 13 /*UART Error Interrupt */ |
| 94 | #define IRQ_RTC 14 /*RTC Interrupt */ | 94 | #define IRQ_RTC 14 /*RTC Interrupt */ |
| 95 | #define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ | 95 | #define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ |
| 96 | #define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ | 96 | #define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ |
| 97 | #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ | 97 | #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ |
| 98 | #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ | 98 | #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ |
| 99 | #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ | 99 | #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ |
| 100 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ | 100 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ |
| 101 | #define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ | 101 | #define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */ |
| 102 | #define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ | 102 | #define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */ |
| 103 | #define IRQ_TMR0 23 /*Timer 0 */ | 103 | #define IRQ_TIMER0 23 /*Timer 0 */ |
| 104 | #define IRQ_TMR1 24 /*Timer 1 */ | 104 | #define IRQ_TIMER1 24 /*Timer 1 */ |
| 105 | #define IRQ_TMR2 25 /*Timer 2 */ | 105 | #define IRQ_TIMER2 25 /*Timer 2 */ |
| 106 | #define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ | 106 | #define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ |
| 107 | #define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ | 107 | #define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ |
| 108 | #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ | 108 | #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ |